Commit graph

9 commits

Author SHA1 Message Date
Rémi Denis-Courmont
f576a0835b lavc/aacpsdsp: rework R-V V hybrid_synthesis_deint
Given the size of the data set, strided memory accesses cannot be avoided.
We can still do better than the current code.

ps_hybrid_synthesis_deint_c:       12065.5
ps_hybrid_synthesis_deint_rvv_i32: 13650.2 (before)
ps_hybrid_synthesis_deint_rvv_i64:  8181.0 (after)
2023-11-12 14:03:09 +02:00
Rémi Denis-Courmont
eb508702a8 lavc/aacpsdsp: rework R-V V add_squares
Segmented loads may be slower than not. So this advantageously uses a
unit-strided load and narrowing shifts instead.

Before:
ps_add_squares_c: 60757.7
ps_add_squares_rvv_f32: 22242.5

After:
ps_add_squares_c: 60516.0
ps_add_squares_rvv_i64: 17067.7
2023-11-12 14:03:09 +02:00
Rémi Denis-Courmont
b6585eb04c lavu: add/use flag for RISC-V Zba extension
The code was blindly assuming that Zbb or V implied Zba. While the
earlier is practically always true, the later broke some QEMU setups,
as V was introduced earlier than Zba.
2023-07-19 19:29:35 +03:00
Rémi Denis-Courmont
c03f9654c9 lavc/aacpsdsp: RISC-V V stereo_interpolate[0] 2022-09-27 13:19:52 +02:00
Rémi Denis-Courmont
a15edb0bc0 lavc/aacpsdsp: RISC-V V hybrid_synthesis_deint 2022-09-27 13:19:52 +02:00
Rémi Denis-Courmont
09f907999f lavc/aacpsdsp: RISC-V V hybrid_analysis_ileave 2022-09-27 13:19:52 +02:00
Rémi Denis-Courmont
15c3a0bd6e lavc/aacpsdsp: RISC-V V hybrid_analysis
This starts with one-time initialisation of the 26 constant factors
like  08edacc248. That is done with
the scalar instruction set. While the formula can readily be vectored,
the gains would (probably) be more than lost in transfering the results
back to FP registers (or suitably reshuffling them into vector
registers).

Note that the main loop could likely be scheduled sligthly better by
expanding the filter macro and interleaving loads with arithmetic.
It is not clear yet if that would be relevant for vector processing (as
opposed to traditional SIMD).

We could also use fewer vectors, but there is not much point in sparing
them (they are *all* callee-clobbered).
2022-09-27 13:19:52 +02:00
Rémi Denis-Courmont
e180326a0b lavc/aacpsdsp: RISC-V V mul_pair_single 2022-09-27 13:19:52 +02:00
Rémi Denis-Courmont
b0cacf4c3f lavc/aacpsdsp: RISC-V V add_squares 2022-09-27 13:19:52 +02:00