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4 commits

Author SHA1 Message Date
Rémi Denis-Courmont
b6585eb04c lavu: add/use flag for RISC-V Zba extension 
The code was blindly assuming that Zbb or V implied Zba. While the
earlier is practically always true, the later broke some QEMU setups,
as V was introduced earlier than Zba.
 2023-07-19 19:29:35 +03:00
Rémi Denis-Courmont
f0d1637c11 lavc/alacdsp: RISC-V V append_extra_bits[1] 2022-10-05 06:51:11 +02:00
Rémi Denis-Courmont
55bde97f29 lavc/alacdsp: RISC-V V append_extra_bits[0] 2022-10-05 06:51:11 +02:00
Rémi Denis-Courmont
64ab577954 lavc/alacdsp: RISC-V V decorrelate_stereo 
To avoid data dependencies, this does the following unroll, which
requires one extra but probably free addition:

    coeff = (b * left_weight) >> decorr_shift;
    b += a;
    a -= coeff;
    b -= coeff;
    swap(a, b);
 2022-10-05 06:51:11 +02:00