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4 commits

Author SHA1 Message Date
Rémi Denis-Courmont
b6585eb04c lavu: add/use flag for RISC-V Zba extension 
The code was blindly assuming that Zbb or V implied Zba. While the
earlier is practically always true, the later broke some QEMU setups,
as V was introduced earlier than Zba.
 2023-07-19 19:29:35 +03:00
Martin Storsjö
6059ea2a14 riscv: Fix linking without RVV; change #ifdef into #if 
Signed-off-by: Martin Storsjö <martin@martin.st>
 2022-09-29 10:28:37 +03:00
Rémi Denis-Courmont
220dfd0945 lavc/fmtconvert: RISC-V V int32_to_float_fmul_array8 2022-09-27 13:19:52 +02:00
Rémi Denis-Courmont
47a10b9a99 lavc/fmtconvert: RISC-V V int32_to_float_fmul_scalar 2022-09-27 13:19:52 +02:00