2015-06-06 16:03:33 -07:00
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// autogenerated: do not edit!
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// generated from gen/*Ops.go
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package ssa
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2015-06-16 11:11:16 -07:00
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import "cmd/internal/obj/x86"
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2015-06-06 16:03:33 -07:00
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const (
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blockInvalid BlockKind = iota
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BlockAMD64EQ
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BlockAMD64NE
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BlockAMD64LT
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BlockAMD64LE
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BlockAMD64GT
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BlockAMD64GE
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BlockAMD64ULT
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BlockAMD64ULE
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BlockAMD64UGT
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BlockAMD64UGE
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BlockExit
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BlockPlain
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BlockIf
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BlockCall
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)
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var blockString = [...]string{
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blockInvalid: "BlockInvalid",
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BlockAMD64EQ: "EQ",
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BlockAMD64NE: "NE",
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BlockAMD64LT: "LT",
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BlockAMD64LE: "LE",
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BlockAMD64GT: "GT",
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BlockAMD64GE: "GE",
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BlockAMD64ULT: "ULT",
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BlockAMD64ULE: "ULE",
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BlockAMD64UGT: "UGT",
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BlockAMD64UGE: "UGE",
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BlockExit: "Exit",
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BlockPlain: "Plain",
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BlockIf: "If",
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BlockCall: "Call",
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}
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func (k BlockKind) String() string { return blockString[k] }
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const (
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OpInvalid Op = iota
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OpAMD64ADDQ
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OpAMD64ADDQconst
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OpAMD64SUBQ
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OpAMD64SUBQconst
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OpAMD64MULQ
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OpAMD64MULQconst
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2015-06-10 10:39:57 -07:00
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OpAMD64ANDQ
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OpAMD64ANDQconst
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OpAMD64SHLQ
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OpAMD64SHLQconst
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OpAMD64SHRQ
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OpAMD64SHRQconst
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OpAMD64SARQ
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OpAMD64SARQconst
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OpAMD64NEGQ
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OpAMD64CMPQ
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OpAMD64CMPQconst
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OpAMD64TESTQ
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OpAMD64TESTB
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OpAMD64SBBQcarrymask
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OpAMD64SETEQ
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OpAMD64SETNE
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OpAMD64SETL
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OpAMD64SETG
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OpAMD64SETGE
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OpAMD64SETB
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OpAMD64CMOVQCC
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OpAMD64MOVLQSX
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OpAMD64MOVWQSX
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OpAMD64MOVBQSX
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OpAMD64MOVQconst
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OpAMD64LEAQ
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OpAMD64LEAQ1
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OpAMD64LEAQ2
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OpAMD64LEAQ4
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OpAMD64LEAQ8
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OpAMD64MOVBload
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OpAMD64MOVBQZXload
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OpAMD64MOVBQSXload
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OpAMD64MOVWload
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OpAMD64MOVLload
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OpAMD64MOVQload
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OpAMD64MOVQloadidx8
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OpAMD64MOVBstore
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OpAMD64MOVWstore
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OpAMD64MOVLstore
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OpAMD64MOVQstore
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OpAMD64MOVQstoreidx8
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OpAMD64MOVQloadglobal
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OpAMD64MOVQstoreglobal
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OpAMD64CALLstatic
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OpAMD64CALLclosure
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OpAMD64REPMOVSB
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OpAMD64ADDL
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OpAMD64ADDW
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OpAMD64ADDB
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OpAMD64InvertFlags
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OpAdd
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OpSub
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OpMul
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OpLsh
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OpRsh
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OpLess
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OpPhi
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OpCopy
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OpConst
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OpArg
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OpAddr
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OpSP
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OpSB
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OpFunc
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OpLoad
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OpStore
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OpMove
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OpClosureCall
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OpStaticCall
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OpConvert
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OpConvNop
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OpIsNonNil
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OpIsInBounds
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OpArrayIndex
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OpPtrIndex
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OpOffPtr
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OpSliceMake
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OpSlicePtr
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OpSliceLen
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OpSliceCap
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OpStringMake
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OpStringPtr
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OpStringLen
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OpStoreReg8
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OpLoadReg8
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OpFwdRef
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)
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var opcodeTable = [...]opInfo{
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{name: "OpInvalid"},
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{
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name: "ADDQ",
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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clobbers: 0,
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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},
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},
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{
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name: "ADDQconst",
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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clobbers: 0,
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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},
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},
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{
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name: "SUBQ",
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2015-06-16 11:11:16 -07:00
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asm: x86.ASUBQ,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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clobbers: 0,
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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},
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},
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{
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name: "SUBQconst",
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2015-06-16 11:11:16 -07:00
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asm: x86.ASUBQ,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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clobbers: 0,
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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},
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},
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{
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name: "MULQ",
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2015-06-16 11:11:16 -07:00
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asm: x86.AIMULQ,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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clobbers: 0,
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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},
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},
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{
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name: "MULQconst",
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2015-06-16 11:11:16 -07:00
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asm: x86.AIMULQ,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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clobbers: 0,
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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},
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},
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2015-06-10 10:39:57 -07:00
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{
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name: "ANDQ",
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2015-06-16 11:11:16 -07:00
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asm: x86.AANDQ,
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2015-06-10 10:39:57 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-10 10:39:57 -07:00
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},
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clobbers: 0,
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-10 10:39:57 -07:00
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},
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},
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},
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{
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name: "ANDQconst",
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2015-06-16 11:11:16 -07:00
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asm: x86.AANDQ,
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2015-06-10 10:39:57 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-10 10:39:57 -07:00
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},
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clobbers: 0,
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-10 10:39:57 -07:00
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},
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},
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},
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2015-06-06 16:03:33 -07:00
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{
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name: "SHLQ",
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2015-06-16 11:11:16 -07:00
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asm: x86.ASHLQ,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2, // .CX
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2015-06-06 16:03:33 -07:00
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},
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clobbers: 0,
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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},
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},
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{
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name: "SHLQconst",
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2015-06-16 11:11:16 -07:00
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asm: x86.ASHLQ,
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2015-06-06 16:03:33 -07:00
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reg: regInfo{
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inputs: []regMask{
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2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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clobbers: 0,
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outputs: []regMask{
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2015-06-11 15:52:08 -07:00
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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2015-06-06 16:03:33 -07:00
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},
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},
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},
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2015-06-10 10:39:57 -07:00
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{
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name: "SHRQ",
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2015-06-16 11:11:16 -07:00
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asm: x86.ASHRQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
2, // .CX
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SHRQconst",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ASHRQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SARQ",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ASARQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
2, // .CX
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SARQconst",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ASARQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
|
|
|
|
name: "NEGQ",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMPQ",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ACMPQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CMPQconst",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ACMPQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "TESTQ",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ATESTQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "TESTB",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ATESTB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
|
|
|
|
name: "SBBQcarrymask",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.ASBBQ,
|
2015-06-10 10:39:57 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
|
|
|
|
name: "SETEQ",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SETNE",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SETL",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SETG",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SETGE",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SETB",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 10:39:57 -07:00
|
|
|
{
|
|
|
|
|
name: "CMOVQCC",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
8589934592, // .FLAGS
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-10 10:39:57 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-14 11:38:46 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVLQSX",
|
|
|
|
|
asm: x86.AMOVLQSX,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVWQSX",
|
|
|
|
|
asm: x86.AMOVWQSX,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBQSX",
|
|
|
|
|
asm: x86.AMOVBQSX,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVQconst",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "LEAQ",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-06-19 21:02:28 -07:00
|
|
|
name: "LEAQ1",
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-06-19 21:02:28 -07:00
|
|
|
name: "LEAQ2",
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-06-19 21:02:28 -07:00
|
|
|
name: "LEAQ4",
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-06-19 21:02:28 -07:00
|
|
|
name: "LEAQ8",
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
2015-06-19 21:02:28 -07:00
|
|
|
inputs: []regMask{
|
|
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBload",
|
2015-06-16 13:33:32 -07:00
|
|
|
asm: x86.AMOVB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-06-06 16:03:33 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBQZXload",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-06-06 16:03:33 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBQSXload",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-06-06 16:03:33 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-14 11:38:46 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVWload",
|
|
|
|
|
asm: x86.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-06-14 11:38:46 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVLload",
|
|
|
|
|
asm: x86.AMOVL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-06-14 11:38:46 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
|
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVQload",
|
2015-06-16 13:33:32 -07:00
|
|
|
asm: x86.AMOVQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
2015-06-06 16:03:33 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVQloadidx8",
|
2015-06-14 11:38:46 -07:00
|
|
|
asm: x86.AMOVQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVBstore",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.AMOVB,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-14 11:38:46 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVWstore",
|
|
|
|
|
asm: x86.AMOVW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVLstore",
|
|
|
|
|
asm: x86.AMOVL,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-06 16:03:33 -07:00
|
|
|
{
|
|
|
|
|
name: "MOVQstore",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.AMOVQ,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVQstoreidx8",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
0,
|
|
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVQloadglobal",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "MOVQstoreglobal",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
},
|
2015-06-10 15:03:06 -07:00
|
|
|
{
|
|
|
|
|
name: "CALLstatic",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "CALLclosure",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
4, // .DX
|
2015-06-10 15:03:06 -07:00
|
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0,
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|
},
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|
clobbers: 0,
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|
outputs: []regMask{},
|
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|
},
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|
},
|
2015-06-06 16:03:33 -07:00
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|
{
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|
|
name: "REPMOVSB",
|
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|
|
reg: regInfo{
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|
inputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
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|
128, // .DI
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64, // .SI
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2, // .CX
|
2015-06-06 16:03:33 -07:00
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},
|
2015-06-11 15:52:08 -07:00
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|
clobbers: 194, // .CX .SI .DI
|
2015-06-06 16:03:33 -07:00
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|
outputs: []regMask{},
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|
},
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|
},
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|
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|
|
{
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|
|
name: "ADDL",
|
2015-06-16 11:11:16 -07:00
|
|
|
asm: x86.AADDL,
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
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|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
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|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
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|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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|
},
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|
},
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|
|
{
|
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|
|
|
name: "ADDW",
|
|
|
|
|
asm: x86.AADDW,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
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|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
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|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-14 11:38:46 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
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|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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|
|
},
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|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ADDB",
|
|
|
|
|
asm: x86.AADDB,
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{
|
2015-06-19 21:02:28 -07:00
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
|
|
|
|
65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{
|
2015-06-11 15:52:08 -07:00
|
|
|
65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
2015-06-06 16:03:33 -07:00
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "InvertFlags",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
|
|
|
|
|
{
|
|
|
|
|
name: "Add",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Sub",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Mul",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Lsh",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Rsh",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Less",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Phi",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Copy",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Const",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Arg",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-06-19 21:02:28 -07:00
|
|
|
name: "Addr",
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SP",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-06-19 21:02:28 -07:00
|
|
|
name: "SB",
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Func",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Load",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Store",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Move",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
2015-06-10 15:03:06 -07:00
|
|
|
name: "ClosureCall",
|
2015-06-06 16:03:33 -07:00
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StaticCall",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "Convert",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ConvNop",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "IsNonNil",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "IsInBounds",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "ArrayIndex",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "PtrIndex",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "OffPtr",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SliceMake",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SlicePtr",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SliceLen",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "SliceCap",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StringMake",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StringPtr",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StringLen",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "StoreReg8",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "LoadReg8",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
name: "FwdRef",
|
|
|
|
|
reg: regInfo{
|
|
|
|
|
inputs: []regMask{},
|
|
|
|
|
clobbers: 0,
|
|
|
|
|
outputs: []regMask{},
|
|
|
|
|
},
|
|
|
|
|
generic: true,
|
|
|
|
|
},
|
|
|
|
|
}
|
|
|
|
|
|
2015-06-16 11:11:16 -07:00
|
|
|
func (o Op) Asm() int { return opcodeTable[o].asm }
|
2015-06-06 16:03:33 -07:00
|
|
|
func (o Op) String() string { return opcodeTable[o].name }
|