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481 lines
24 KiB
Go
481 lines
24 KiB
Go
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// Copyright 2022 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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//go:build ignore
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// +build ignore
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package main
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import "strings"
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// Notes:
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// - Integer types live in the low portion of registers. Upper portions are junk.
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// - Boolean types use the low-order byte of a register. 0=false, 1=true.
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// Upper bytes are junk.
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// - *const instructions may use a constant larger than the instruction can encode.
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// In this case the assembler expands to multiple instructions and uses tmp
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// register (R23).
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// Suffixes encode the bit width of various instructions.
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// V (vlong) = 64 bit
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// WU (word) = 32 bit unsigned
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// W (word) = 32 bit
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// H (half word) = 16 bit
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// HU = 16 bit unsigned
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// B (byte) = 8 bit
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// BU = 8 bit unsigned
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// F (float) = 32 bit float
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// D (double) = 64 bit float
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// Note: registers not used in regalloc are not included in this list,
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// so that regmask stays within int64
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// Be careful when hand coding regmasks.
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var regNamesLOONG64 = []string{
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"R0", // constant 0
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"R1",
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"SP", // aka R3
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"R4",
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"R5",
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"R6",
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"R7",
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"R8",
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"R9",
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"R10",
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"R11",
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"R12",
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"R13",
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"R14",
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"R15",
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"R16",
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"R17",
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"R18",
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"R19",
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"R20",
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"R21",
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"g", // aka R22
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"R23",
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"R24",
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"R25",
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"R26",
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"R27",
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"R28",
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"R29",
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// R30 is REGTMP not used in regalloc
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"R31",
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"F0",
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"F1",
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"F2",
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"F3",
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"F4",
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"F5",
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"F6",
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"F7",
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"F8",
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"F9",
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"F10",
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"F11",
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"F12",
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"F13",
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"F14",
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"F15",
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"F16",
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"F17",
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"F18",
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"F19",
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"F20",
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"F21",
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"F22",
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"F23",
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"F24",
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"F25",
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"F26",
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"F27",
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"F28",
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"F29",
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"F30",
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"F31",
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// If you add registers, update asyncPreempt in runtime.
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// pseudo-registers
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"SB",
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}
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func init() {
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// Make map from reg names to reg integers.
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if len(regNamesLOONG64) > 64 {
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panic("too many registers")
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}
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num := map[string]int{}
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for i, name := range regNamesLOONG64 {
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num[name] = i
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}
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buildReg := func(s string) regMask {
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m := regMask(0)
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for _, r := range strings.Split(s, " ") {
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if n, ok := num[r]; ok {
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m |= regMask(1) << uint(n)
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continue
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}
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panic("register " + r + " not found")
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}
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return m
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}
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// Common individual register masks
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var (
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gp = buildReg("R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31") // R1 is LR, R2 is thread pointer, R3 is stack pointer, R21-unused, R22 is g, R30 is REGTMP
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gps = buildReg("R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31") | buildReg("g")
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gpg = gp | buildReg("g")
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gpsp = gp | buildReg("SP")
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gpspg = gpg | buildReg("SP")
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gpspsbg = gpspg | buildReg("SB")
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fp = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31")
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callerSave = gp | fp | buildReg("g") // runtime.setg (and anything calling it) may clobber g
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r1 = buildReg("R19")
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r2 = buildReg("R18")
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r3 = buildReg("R17")
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r4 = buildReg("R4")
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)
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// Common regInfo
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var (
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gp01 = regInfo{inputs: nil, outputs: []regMask{gp}}
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gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}}
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gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}}
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gp21 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}}
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gpmuldiv = regInfo{inputs: []regMask{gps, gps}, outputs: []regMask{buildReg("R17"), buildReg("R18")}}
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gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}
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gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}}
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gpstore0 = regInfo{inputs: []regMask{gpspsbg}}
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gpxchg = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}}
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gpcas = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}, outputs: []regMask{gp}}
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fp01 = regInfo{inputs: nil, outputs: []regMask{fp}}
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fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}}
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fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}}
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fp2flags = regInfo{inputs: []regMask{fp, fp}}
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fpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{fp}}
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fpstore = regInfo{inputs: []regMask{gpspsbg, fp}}
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readflags = regInfo{inputs: nil, outputs: []regMask{gp}}
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)
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ops := []opData{
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// binary ops
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{name: "ADDV", argLength: 2, reg: gp21, asm: "ADDVU", commutative: true}, // arg0 + arg1
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{name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64"}, // arg0 + auxInt. auxInt is 32-bit, also in other *const ops.
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{name: "SUBV", argLength: 2, reg: gp21, asm: "SUBVU"}, // arg0 - arg1
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{name: "SUBVconst", argLength: 1, reg: gp11, asm: "SUBVU", aux: "Int64"}, // arg0 - auxInt
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{name: "MULV", argLength: 2, reg: gpmuldiv, commutative: true, typ: "(Int64,Int64)"}, // arg0 * arg1, signed
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{name: "MULVU", argLength: 2, reg: gpmuldiv, commutative: true, typ: "(UInt64,UInt64)"}, // arg0 * arg1, unsigned
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{name: "DIVV", argLength: 2, reg: gpmuldiv, typ: "(Int64,Int64)"}, // arg0 / arg1, signed
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{name: "DIVVU", argLength: 2, reg: gpmuldiv, typ: "(UInt64,UInt64)"}, // arg0 / arg1, unsigned
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{name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true}, // arg0 + arg1
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{name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true}, // arg0 + arg1
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{name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF"}, // arg0 - arg1
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{name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"}, // arg0 - arg1
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{name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true}, // arg0 * arg1
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{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
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{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"}, // arg0 / arg1
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{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"}, // arg0 / arg1
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{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1
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{name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int64"}, // arg0 & auxInt
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{name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true}, // arg0 | arg1
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{name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64"}, // arg0 | auxInt
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{name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, typ: "UInt64"}, // arg0 ^ arg1
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{name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64", typ: "UInt64"}, // arg0 ^ auxInt
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{name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true}, // ^(arg0 | arg1)
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{name: "NORconst", argLength: 1, reg: gp11, asm: "NOR", aux: "Int64"}, // ^(arg0 | auxInt)
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{name: "NEGV", argLength: 1, reg: gp11}, // -arg0
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{name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"}, // -arg0, float32
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{name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64
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{name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64
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{name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32
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// shifts
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{name: "SLLV", argLength: 2, reg: gp21, asm: "SLLV"}, // arg0 << arg1, shift amount is mod 64
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{name: "SLLVconst", argLength: 1, reg: gp11, asm: "SLLV", aux: "Int64"}, // arg0 << auxInt
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{name: "SRLV", argLength: 2, reg: gp21, asm: "SRLV"}, // arg0 >> arg1, unsigned, shift amount is mod 64
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{name: "SRLVconst", argLength: 1, reg: gp11, asm: "SRLV", aux: "Int64"}, // arg0 >> auxInt, unsigned
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{name: "SRAV", argLength: 2, reg: gp21, asm: "SRAV"}, // arg0 >> arg1, signed, shift amount is mod 64
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{name: "SRAVconst", argLength: 1, reg: gp11, asm: "SRAV", aux: "Int64"}, // arg0 >> auxInt, signed
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// comparisons
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{name: "SGT", argLength: 2, reg: gp21, asm: "SGT", typ: "Bool"}, // 1 if arg0 > arg1 (signed), 0 otherwise
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{name: "SGTconst", argLength: 1, reg: gp11, asm: "SGT", aux: "Int64", typ: "Bool"}, // 1 if auxInt > arg0 (signed), 0 otherwise
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{name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool"}, // 1 if arg0 > arg1 (unsigned), 0 otherwise
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{name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int64", typ: "Bool"}, // 1 if auxInt > arg0 (unsigned), 0 otherwise
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{name: "CMPEQF", argLength: 2, reg: fp2flags, asm: "CMPEQF", typ: "Flags"}, // flags=true if arg0 = arg1, float32
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{name: "CMPEQD", argLength: 2, reg: fp2flags, asm: "CMPEQD", typ: "Flags"}, // flags=true if arg0 = arg1, float64
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{name: "CMPGEF", argLength: 2, reg: fp2flags, asm: "CMPGEF", typ: "Flags"}, // flags=true if arg0 >= arg1, float32
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{name: "CMPGED", argLength: 2, reg: fp2flags, asm: "CMPGED", typ: "Flags"}, // flags=true if arg0 >= arg1, float64
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{name: "CMPGTF", argLength: 2, reg: fp2flags, asm: "CMPGTF", typ: "Flags"}, // flags=true if arg0 > arg1, float32
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{name: "CMPGTD", argLength: 2, reg: fp2flags, asm: "CMPGTD", typ: "Flags"}, // flags=true if arg0 > arg1, float64
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// moves
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{name: "MOVVconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVV", typ: "UInt64", rematerializeable: true}, // auxint
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{name: "MOVFconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVF", typ: "Float32", rematerializeable: true}, // auxint as 64-bit float, convert to 32-bit float
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{name: "MOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVD", typ: "Float64", rematerializeable: true}, // auxint as 64-bit float
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{name: "MOVVaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP") | buildReg("SB")}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVV", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB
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{name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
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{name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
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{name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
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{name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
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{name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "Int32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
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{name: "MOVWUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVWU", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
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{name: "MOVVload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVV", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
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{name: "MOVFload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVF", typ: "Float32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
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{name: "MOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVD", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
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{name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 1 byte of arg1 to arg0 + auxInt + aux. arg2=mem.
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{name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
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{name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
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{name: "MOVVstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
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{name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
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{name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
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{name: "MOVBstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 1 byte of zero to arg0 + auxInt + aux. arg1=mem.
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{name: "MOVHstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes of zero to arg0 + auxInt + aux. arg1=mem.
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{name: "MOVWstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of zero to arg0 + auxInt + aux. arg1=mem.
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|
|
{name: "MOVVstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of zero to arg0 + auxInt + aux. ar12=mem.
|
||
|
|
|
||
|
|
// conversions
|
||
|
|
{name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"}, // move from arg0, sign-extended from byte
|
||
|
|
{name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte
|
||
|
|
{name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH"}, // move from arg0, sign-extended from half
|
||
|
|
{name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half
|
||
|
|
{name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW"}, // move from arg0, sign-extended from word
|
||
|
|
{name: "MOVWUreg", argLength: 1, reg: gp11, asm: "MOVWU"}, // move from arg0, unsign-extended from word
|
||
|
|
{name: "MOVVreg", argLength: 1, reg: gp11, asm: "MOVV"}, // move from arg0
|
||
|
|
|
||
|
|
{name: "MOVVnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true}, // nop, return arg0 in same register
|
||
|
|
|
||
|
|
{name: "MOVWF", argLength: 1, reg: fp11, asm: "MOVWF"}, // int32 -> float32
|
||
|
|
{name: "MOVWD", argLength: 1, reg: fp11, asm: "MOVWD"}, // int32 -> float64
|
||
|
|
{name: "MOVVF", argLength: 1, reg: fp11, asm: "MOVVF"}, // int64 -> float32
|
||
|
|
{name: "MOVVD", argLength: 1, reg: fp11, asm: "MOVVD"}, // int64 -> float64
|
||
|
|
{name: "TRUNCFW", argLength: 1, reg: fp11, asm: "TRUNCFW"}, // float32 -> int32
|
||
|
|
{name: "TRUNCDW", argLength: 1, reg: fp11, asm: "TRUNCDW"}, // float64 -> int32
|
||
|
|
{name: "TRUNCFV", argLength: 1, reg: fp11, asm: "TRUNCFV"}, // float32 -> int64
|
||
|
|
{name: "TRUNCDV", argLength: 1, reg: fp11, asm: "TRUNCDV"}, // float64 -> int64
|
||
|
|
{name: "MOVFD", argLength: 1, reg: fp11, asm: "MOVFD"}, // float32 -> float64
|
||
|
|
{name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF"}, // float64 -> float32
|
||
|
|
|
||
|
|
// function calls
|
||
|
|
{name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem
|
||
|
|
{name: "CALLtail", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem
|
||
|
|
{name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R29"), 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
|
||
|
|
{name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
|
||
|
|
|
||
|
|
// duffzero
|
||
|
|
// arg0 = address of memory to zero
|
||
|
|
// arg1 = mem
|
||
|
|
// auxint = offset into duffzero code to start executing
|
||
|
|
// returns mem
|
||
|
|
// R19 aka loong64.REGRT1 changed as side effect
|
||
|
|
{
|
||
|
|
name: "DUFFZERO",
|
||
|
|
aux: "Int64",
|
||
|
|
argLength: 2,
|
||
|
|
reg: regInfo{
|
||
|
|
inputs: []regMask{gp},
|
||
|
|
clobbers: buildReg("R19 R1"),
|
||
|
|
},
|
||
|
|
faultOnNilArg0: true,
|
||
|
|
},
|
||
|
|
|
||
|
|
// duffcopy
|
||
|
|
// arg0 = address of dst memory (in R20, changed as side effect) REGRT2
|
||
|
|
// arg1 = address of src memory (in R19, changed as side effect) REGRT1
|
||
|
|
// arg2 = mem
|
||
|
|
// auxint = offset into duffcopy code to start executing
|
||
|
|
// returns mem
|
||
|
|
{
|
||
|
|
name: "DUFFCOPY",
|
||
|
|
aux: "Int64",
|
||
|
|
argLength: 3,
|
||
|
|
reg: regInfo{
|
||
|
|
inputs: []regMask{buildReg("R20"), buildReg("R19")},
|
||
|
|
clobbers: buildReg("R19 R20 R1"),
|
||
|
|
},
|
||
|
|
faultOnNilArg0: true,
|
||
|
|
faultOnNilArg1: true,
|
||
|
|
},
|
||
|
|
|
||
|
|
// large or unaligned zeroing
|
||
|
|
// arg0 = address of memory to zero (in R19, changed as side effect)
|
||
|
|
// arg1 = address of the last element to zero
|
||
|
|
// arg2 = mem
|
||
|
|
// auxint = alignment
|
||
|
|
// returns mem
|
||
|
|
// SUBV $8, R19
|
||
|
|
// MOVV R0, 8(R19)
|
||
|
|
// ADDV $8, R19
|
||
|
|
// BNE Rarg1, R19, -2(PC)
|
||
|
|
{
|
||
|
|
name: "LoweredZero",
|
||
|
|
aux: "Int64",
|
||
|
|
argLength: 3,
|
||
|
|
reg: regInfo{
|
||
|
|
inputs: []regMask{buildReg("R19"), gp},
|
||
|
|
clobbers: buildReg("R19"),
|
||
|
|
},
|
||
|
|
clobberFlags: true,
|
||
|
|
faultOnNilArg0: true,
|
||
|
|
},
|
||
|
|
|
||
|
|
// large or unaligned move
|
||
|
|
// arg0 = address of dst memory (in R4, changed as side effect)
|
||
|
|
// arg1 = address of src memory (in R19, changed as side effect)
|
||
|
|
// arg2 = address of the last element of src
|
||
|
|
// arg3 = mem
|
||
|
|
// auxint = alignment
|
||
|
|
// returns mem
|
||
|
|
// SUBV $8, R19
|
||
|
|
// MOVV 8(R19), Rtmp
|
||
|
|
// MOVV Rtmp, (R4)
|
||
|
|
// ADDV $8, R19
|
||
|
|
// ADDV $8, R4
|
||
|
|
// BNE Rarg2, R19, -4(PC)
|
||
|
|
{
|
||
|
|
name: "LoweredMove",
|
||
|
|
aux: "Int64",
|
||
|
|
argLength: 4,
|
||
|
|
reg: regInfo{
|
||
|
|
inputs: []regMask{buildReg("R4"), buildReg("R19"), gp},
|
||
|
|
clobbers: buildReg("R19 R4"),
|
||
|
|
},
|
||
|
|
clobberFlags: true,
|
||
|
|
faultOnNilArg0: true,
|
||
|
|
faultOnNilArg1: true,
|
||
|
|
},
|
||
|
|
|
||
|
|
// atomic loads.
|
||
|
|
// load from arg0. arg1=mem.
|
||
|
|
// returns <value,memory> so they can be properly ordered with other loads.
|
||
|
|
{name: "LoweredAtomicLoad8", argLength: 2, reg: gpload, faultOnNilArg0: true},
|
||
|
|
{name: "LoweredAtomicLoad32", argLength: 2, reg: gpload, faultOnNilArg0: true},
|
||
|
|
{name: "LoweredAtomicLoad64", argLength: 2, reg: gpload, faultOnNilArg0: true},
|
||
|
|
|
||
|
|
// atomic stores.
|
||
|
|
// store arg1 to arg0. arg2=mem. returns memory.
|
||
|
|
{name: "LoweredAtomicStore8", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
|
||
|
|
{name: "LoweredAtomicStore32", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
|
||
|
|
{name: "LoweredAtomicStore64", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
|
||
|
|
// store zero to arg0. arg1=mem. returns memory.
|
||
|
|
{name: "LoweredAtomicStorezero32", argLength: 2, reg: gpstore0, faultOnNilArg0: true, hasSideEffects: true},
|
||
|
|
{name: "LoweredAtomicStorezero64", argLength: 2, reg: gpstore0, faultOnNilArg0: true, hasSideEffects: true},
|
||
|
|
|
||
|
|
// atomic exchange.
|
||
|
|
// store arg1 to arg0. arg2=mem. returns <old content of *arg0, memory>.
|
||
|
|
// DBAR
|
||
|
|
// LL (Rarg0), Rout
|
||
|
|
// MOVV Rarg1, Rtmp
|
||
|
|
// SC Rtmp, (Rarg0)
|
||
|
|
// BEQ Rtmp, -3(PC)
|
||
|
|
// DBAR
|
||
|
|
{name: "LoweredAtomicExchange32", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||
|
|
{name: "LoweredAtomicExchange64", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||
|
|
|
||
|
|
// atomic add.
|
||
|
|
// *arg0 += arg1. arg2=mem. returns <new content of *arg0, memory>.
|
||
|
|
// DBAR
|
||
|
|
// LL (Rarg0), Rout
|
||
|
|
// ADDV Rarg1, Rout, Rtmp
|
||
|
|
// SC Rtmp, (Rarg0)
|
||
|
|
// BEQ Rtmp, -3(PC)
|
||
|
|
// DBAR
|
||
|
|
// ADDV Rarg1, Rout
|
||
|
|
{name: "LoweredAtomicAdd32", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||
|
|
{name: "LoweredAtomicAdd64", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||
|
|
// *arg0 += auxint. arg1=mem. returns <new content of *arg0, memory>. auxint is 32-bit.
|
||
|
|
{name: "LoweredAtomicAddconst32", argLength: 2, reg: regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}, aux: "Int32", resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||
|
|
{name: "LoweredAtomicAddconst64", argLength: 2, reg: regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}, aux: "Int64", resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||
|
|
|
||
|
|
// atomic compare and swap.
|
||
|
|
// arg0 = pointer, arg1 = old value, arg2 = new value, arg3 = memory.
|
||
|
|
// if *arg0 == arg1 {
|
||
|
|
// *arg0 = arg2
|
||
|
|
// return (true, memory)
|
||
|
|
// } else {
|
||
|
|
// return (false, memory)
|
||
|
|
// }
|
||
|
|
// DBAR
|
||
|
|
// MOVV $0, Rout
|
||
|
|
// LL (Rarg0), Rtmp
|
||
|
|
// BNE Rtmp, Rarg1, 4(PC)
|
||
|
|
// MOVV Rarg2, Rout
|
||
|
|
// SC Rout, (Rarg0)
|
||
|
|
// BEQ Rout, -4(PC)
|
||
|
|
// DBAR
|
||
|
|
{name: "LoweredAtomicCas32", argLength: 4, reg: gpcas, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||
|
|
{name: "LoweredAtomicCas64", argLength: 4, reg: gpcas, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||
|
|
|
||
|
|
// pseudo-ops
|
||
|
|
{name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}, nilCheck: true, faultOnNilArg0: true}, // panic if arg0 is nil. arg1=mem.
|
||
|
|
|
||
|
|
{name: "FPFlagTrue", argLength: 1, reg: readflags}, // bool, true if FP flag is true
|
||
|
|
{name: "FPFlagFalse", argLength: 1, reg: readflags}, // bool, true if FP flag is false
|
||
|
|
|
||
|
|
// Scheduler ensures LoweredGetClosurePtr occurs only in entry block,
|
||
|
|
// and sorts it to the very beginning of the block to prevent other
|
||
|
|
// use of R22 (loong64.REGCTXT, the closure pointer)
|
||
|
|
{name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{buildReg("R29")}}, zeroWidth: true},
|
||
|
|
|
||
|
|
// LoweredGetCallerSP returns the SP of the caller of the current function.
|
||
|
|
{name: "LoweredGetCallerSP", reg: gp01, rematerializeable: true},
|
||
|
|
|
||
|
|
// LoweredGetCallerPC evaluates to the PC to which its "caller" will return.
|
||
|
|
// I.e., if f calls g "calls" getcallerpc,
|
||
|
|
// the result should be the PC within f that g will return to.
|
||
|
|
// See runtime/stubs.go for a more detailed discussion.
|
||
|
|
{name: "LoweredGetCallerPC", reg: gp01, rematerializeable: true},
|
||
|
|
|
||
|
|
// LoweredWB invokes runtime.gcWriteBarrier. arg0=destptr, arg1=srcptr, arg2=mem, aux=runtime.gcWriteBarrier
|
||
|
|
// It saves all GP registers if necessary,
|
||
|
|
// but clobbers R1 (LR) because it's a call
|
||
|
|
// and R30 (REGTMP).
|
||
|
|
{name: "LoweredWB", argLength: 3, reg: regInfo{inputs: []regMask{buildReg("R27"), buildReg("R28")}, clobbers: (callerSave &^ gpg) | buildReg("R1")}, clobberFlags: true, aux: "Sym", symEffect: "None"},
|
||
|
|
|
||
|
|
// There are three of these functions so that they can have three different register inputs.
|
||
|
|
// When we check 0 <= c <= cap (A), then 0 <= b <= c (B), then 0 <= a <= b (C), we want the
|
||
|
|
// default registers to match so we don't need to copy registers around unnecessarily.
|
||
|
|
{name: "LoweredPanicBoundsA", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{r3, r4}}, typ: "Mem", call: true}, // arg0=idx, arg1=len, arg2=mem, returns memory. AuxInt contains report code (see PanicBounds in genericOps.go).
|
||
|
|
{name: "LoweredPanicBoundsB", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{r2, r3}}, typ: "Mem", call: true}, // arg0=idx, arg1=len, arg2=mem, returns memory. AuxInt contains report code (see PanicBounds in genericOps.go).
|
||
|
|
{name: "LoweredPanicBoundsC", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{r1, r2}}, typ: "Mem", call: true}, // arg0=idx, arg1=len, arg2=mem, returns memory. AuxInt contains report code (see PanicBounds in genericOps.go).
|
||
|
|
}
|
||
|
|
|
||
|
|
blocks := []blockData{
|
||
|
|
{name: "EQ", controls: 1},
|
||
|
|
{name: "NE", controls: 1},
|
||
|
|
{name: "LTZ", controls: 1}, // < 0
|
||
|
|
{name: "LEZ", controls: 1}, // <= 0
|
||
|
|
{name: "GTZ", controls: 1}, // > 0
|
||
|
|
{name: "GEZ", controls: 1}, // >= 0
|
||
|
|
{name: "FPT", controls: 1}, // FP flag is true
|
||
|
|
{name: "FPF", controls: 1}, // FP flag is false
|
||
|
|
}
|
||
|
|
|
||
|
|
archs = append(archs, arch{
|
||
|
|
name: "LOONG64",
|
||
|
|
pkg: "cmd/internal/obj/loong64",
|
||
|
|
genfile: "../../loong64/ssa.go",
|
||
|
|
ops: ops,
|
||
|
|
blocks: blocks,
|
||
|
|
regnames: regNamesLOONG64,
|
||
|
|
// TODO: support register ABI on loong64
|
||
|
|
ParamIntRegNames: "R4 R5 R6 R7 R8 R9 R10 R11",
|
||
|
|
ParamFloatRegNames: "F0 F1 F2 F3 F4 F5 F6 F7",
|
||
|
|
gpregmask: gp,
|
||
|
|
fpregmask: fp,
|
||
|
|
framepointerreg: -1, // not used
|
||
|
|
linkreg: int8(num["R1"]),
|
||
|
|
})
|
||
|
|
}
|