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528 lines
29 KiB
Go
528 lines
29 KiB
Go
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// Copyright 2016 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// +build ignore
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package main
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import "strings"
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// Notes:
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// - Integer types live in the low portion of registers. Upper portions are junk.
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// - Boolean types use the low-order byte of a register. 0=false, 1=true.
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// Upper bytes are junk.
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// - When doing sub-register operations, we try to write the whole
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// destination register to avoid a partial-register write.
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// - Unused portions of AuxInt (or the Val portion of ValAndOff) are
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// filled by sign-extending the used portion. Users of AuxInt which interpret
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// AuxInt as unsigned (e.g. shifts) must be careful.
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// Suffixes encode the bit width of various instructions.
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// D (double word) = 64 bit (frequently omitted)
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// W (word) = 32 bit
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// H (half word) = 16 bit
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// B (byte) = 8 bit
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// copied from ../../s390x/reg.go
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var regNamesS390X = []string{
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"R0",
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"R1",
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"R2",
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"R3",
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"R4",
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"R5",
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"R6",
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"R7",
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"R8",
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"R9",
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"R10",
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"R11",
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"R12",
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"g", // R13
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"R14",
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"SP", // R15
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"F0",
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"F1",
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"F2",
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"F3",
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"F4",
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"F5",
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"F6",
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"F7",
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"F8",
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"F9",
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"F10",
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"F11",
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"F12",
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"F13",
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"F14",
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"F15",
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//pseudo-registers
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"SB",
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}
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func init() {
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// Make map from reg names to reg integers.
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if len(regNamesS390X) > 64 {
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panic("too many registers")
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}
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num := map[string]int{}
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for i, name := range regNamesS390X {
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num[name] = i
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}
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buildReg := func(s string) regMask {
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m := regMask(0)
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for _, r := range strings.Split(s, " ") {
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if n, ok := num[r]; ok {
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m |= regMask(1) << uint(n)
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continue
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}
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panic("register " + r + " not found")
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}
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return m
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}
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// Common individual register masks
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var (
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sp = buildReg("SP")
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sb = buildReg("SB")
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r0 = buildReg("R0")
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// R10 and R11 are reserved by the assembler.
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gp = buildReg("R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12")
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gpsp = gp | sp
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// R0 is considered to contain the value 0 in address calculations.
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ptr = gp &^ r0
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ptrsp = ptr | sp
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ptrspsb = ptrsp | sb
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fp = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15")
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callerSave = gp | fp
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)
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// Common slices of register masks
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var (
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gponly = []regMask{gp}
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fponly = []regMask{fp}
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)
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// Common regInfo
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var (
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gp01 = regInfo{inputs: []regMask{}, outputs: gponly}
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gp11 = regInfo{inputs: []regMask{gp}, outputs: gponly}
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gp11sp = regInfo{inputs: []regMask{gpsp}, outputs: gponly}
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gp21 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly}
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gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly}
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// R0 evaluates to 0 when used as the number of bits to shift
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// so we need to exclude it from that operand.
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sh21 = regInfo{inputs: []regMask{gp, ptr}, outputs: gponly}
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addr = regInfo{inputs: []regMask{sp | sb}, outputs: gponly}
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addridx = regInfo{inputs: []regMask{sp | sb, ptrsp}, outputs: gponly}
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gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}}
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gp1flags = regInfo{inputs: []regMask{gpsp}}
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flagsgp = regInfo{outputs: gponly}
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gp2flags1 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly}
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gpload = regInfo{inputs: []regMask{ptrspsb, 0}, outputs: gponly}
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gploadidx = regInfo{inputs: []regMask{ptrspsb, ptrsp, 0}, outputs: gponly}
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gpstore = regInfo{inputs: []regMask{ptrspsb, gpsp, 0}}
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gpstoreconst = regInfo{inputs: []regMask{ptrspsb, 0}}
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gpstoreidx = regInfo{inputs: []regMask{ptrsp, ptrsp, gpsp, 0}}
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gpmvc = regInfo{inputs: []regMask{ptrsp, ptrsp, 0}}
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fp01 = regInfo{inputs: []regMask{}, outputs: fponly}
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fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: fponly}
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fp21clobber = regInfo{inputs: []regMask{fp, fp}, outputs: fponly}
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fpgp = regInfo{inputs: fponly, outputs: gponly}
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gpfp = regInfo{inputs: gponly, outputs: fponly}
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fp11 = regInfo{inputs: fponly, outputs: fponly}
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fp11clobber = regInfo{inputs: fponly, outputs: fponly}
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fp2flags = regInfo{inputs: []regMask{fp, fp}}
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fpload = regInfo{inputs: []regMask{ptrspsb, 0}, outputs: fponly}
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fploadidx = regInfo{inputs: []regMask{ptrsp, ptrsp, 0}, outputs: fponly}
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fpstore = regInfo{inputs: []regMask{ptrspsb, fp, 0}}
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fpstoreidx = regInfo{inputs: []regMask{ptrsp, ptrsp, fp, 0}}
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)
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var S390Xops = []opData{
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// fp ops
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{name: "FADDS", argLength: 2, reg: fp21clobber, asm: "FADDS", commutative: true, resultInArg0: true, clobberFlags: true}, // fp32 add
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{name: "FADD", argLength: 2, reg: fp21clobber, asm: "FADD", commutative: true, resultInArg0: true, clobberFlags: true}, // fp64 add
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{name: "FSUBS", argLength: 2, reg: fp21clobber, asm: "FSUBS", resultInArg0: true, clobberFlags: true}, // fp32 sub
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{name: "FSUB", argLength: 2, reg: fp21clobber, asm: "FSUB", resultInArg0: true, clobberFlags: true}, // fp64 sub
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{name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true, resultInArg0: true}, // fp32 mul
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{name: "FMUL", argLength: 2, reg: fp21, asm: "FMUL", commutative: true, resultInArg0: true}, // fp64 mul
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{name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS", resultInArg0: true}, // fp32 div
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{name: "FDIV", argLength: 2, reg: fp21, asm: "FDIV", resultInArg0: true}, // fp64 div
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{name: "FNEGS", argLength: 1, reg: fp11clobber, asm: "FNEGS", clobberFlags: true}, // fp32 neg
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{name: "FNEG", argLength: 1, reg: fp11clobber, asm: "FNEG", clobberFlags: true}, // fp64 neg
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{name: "FMOVSload", argLength: 2, reg: fpload, asm: "FMOVS", aux: "SymOff"}, // fp32 load
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{name: "FMOVDload", argLength: 2, reg: fpload, asm: "FMOVD", aux: "SymOff"}, // fp64 load
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{name: "FMOVSconst", reg: fp01, asm: "FMOVS", aux: "Float32", rematerializeable: true}, // fp32 constant
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{name: "FMOVDconst", reg: fp01, asm: "FMOVD", aux: "Float64", rematerializeable: true}, // fp64 constant
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{name: "FMOVSloadidx", argLength: 3, reg: fploadidx, asm: "FMOVS", aux: "SymOff"}, // fp32 load indexed by i
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{name: "FMOVDloadidx", argLength: 3, reg: fploadidx, asm: "FMOVD", aux: "SymOff"}, // fp64 load indexed by i
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{name: "FMOVSstore", argLength: 3, reg: fpstore, asm: "FMOVS", aux: "SymOff"}, // fp32 store
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{name: "FMOVDstore", argLength: 3, reg: fpstore, asm: "FMOVD", aux: "SymOff"}, // fp64 store
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{name: "FMOVSstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVS", aux: "SymOff"}, // fp32 indexed by i store
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{name: "FMOVDstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVD", aux: "SymOff"}, // fp64 indexed by i store
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// binary ops
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{name: "ADD", argLength: 2, reg: gp21sp, asm: "ADD", commutative: true, clobberFlags: true}, // arg0 + arg1
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{name: "ADDW", argLength: 2, reg: gp21sp, asm: "ADDW", commutative: true, clobberFlags: true}, // arg0 + arg1
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{name: "ADDconst", argLength: 1, reg: gp11sp, asm: "ADD", aux: "Int64", typ: "UInt64", clobberFlags: true}, // arg0 + auxint
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{name: "ADDWconst", argLength: 1, reg: gp11sp, asm: "ADDW", aux: "Int32", clobberFlags: true}, // arg0 + auxint
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{name: "SUB", argLength: 2, reg: gp21, asm: "SUB", clobberFlags: true}, // arg0 - arg1
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{name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW", clobberFlags: true}, // arg0 - arg1
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{name: "SUBconst", argLength: 1, reg: gp11, asm: "SUB", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 - auxint
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{name: "SUBWconst", argLength: 1, reg: gp11, asm: "SUBW", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 - auxint
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{name: "MULLD", argLength: 2, reg: gp21, asm: "MULLD", typ: "Int64", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 * arg1
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{name: "MULLW", argLength: 2, reg: gp21, asm: "MULLW", typ: "Int32", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 * arg1
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{name: "MULLDconst", argLength: 1, reg: gp11, asm: "MULLD", aux: "Int64", typ: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 * auxint
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{name: "MULLWconst", argLength: 1, reg: gp11, asm: "MULLW", aux: "Int32", typ: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 * auxint
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{name: "MULHD", argLength: 2, reg: gp21, asm: "MULHD", typ: "Int64", resultInArg0: true, clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "MULHDU", argLength: 2, reg: gp21, asm: "MULHDU", typ: "Int64", resultInArg0: true, clobberFlags: true}, // (arg0 * arg1) >> width
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{name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", resultInArg0: true, clobberFlags: true}, // arg0 / arg1
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{name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", resultInArg0: true, clobberFlags: true}, // arg0 / arg1
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{name: "DIVDU", argLength: 2, reg: gp21, asm: "DIVDU", resultInArg0: true, clobberFlags: true}, // arg0 / arg1
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{name: "DIVWU", argLength: 2, reg: gp21, asm: "DIVWU", resultInArg0: true, clobberFlags: true}, // arg0 / arg1
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{name: "MODD", argLength: 2, reg: gp21, asm: "MODD", resultInArg0: true, clobberFlags: true}, // arg0 % arg1
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{name: "MODW", argLength: 2, reg: gp21, asm: "MODW", resultInArg0: true, clobberFlags: true}, // arg0 % arg1
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{name: "MODDU", argLength: 2, reg: gp21, asm: "MODDU", resultInArg0: true, clobberFlags: true}, // arg0 % arg1
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{name: "MODWU", argLength: 2, reg: gp21, asm: "MODWU", resultInArg0: true, clobberFlags: true}, // arg0 % arg1
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{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true, clobberFlags: true}, // arg0 & arg1
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{name: "ANDW", argLength: 2, reg: gp21, asm: "AND", commutative: true, clobberFlags: true}, // arg0 & arg1
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{name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 & auxint
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{name: "ANDWconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 & auxint
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{name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true, clobberFlags: true}, // arg0 | arg1
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{name: "ORW", argLength: 2, reg: gp21, asm: "OR", commutative: true, clobberFlags: true}, // arg0 | arg1
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{name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 | auxint
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{name: "ORWconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 | auxint
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{name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, clobberFlags: true}, // arg0 ^ arg1
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{name: "XORW", argLength: 2, reg: gp21, asm: "XOR", commutative: true, clobberFlags: true}, // arg0 ^ arg1
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{name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64", resultInArg0: true, clobberFlags: true}, // arg0 ^ auxint
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{name: "XORWconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 ^ auxint
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{name: "CMP", argLength: 2, reg: gp2flags, asm: "CMP", typ: "Flags"}, // arg0 compare to arg1
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{name: "CMPW", argLength: 2, reg: gp2flags, asm: "CMPW", typ: "Flags"}, // arg0 compare to arg1
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{name: "CMPU", argLength: 2, reg: gp2flags, asm: "CMPU", typ: "Flags"}, // arg0 compare to arg1
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{name: "CMPWU", argLength: 2, reg: gp2flags, asm: "CMPWU", typ: "Flags"}, // arg0 compare to arg1
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{name: "CMPconst", argLength: 1, reg: gp1flags, asm: "CMP", typ: "Flags", aux: "Int64"}, // arg0 compare to auxint
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{name: "CMPWconst", argLength: 1, reg: gp1flags, asm: "CMPW", typ: "Flags", aux: "Int32"}, // arg0 compare to auxint
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{name: "CMPUconst", argLength: 1, reg: gp1flags, asm: "CMPU", typ: "Flags", aux: "Int64"}, // arg0 compare to auxint
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{name: "CMPWUconst", argLength: 1, reg: gp1flags, asm: "CMPWU", typ: "Flags", aux: "Int32"}, // arg0 compare to auxint
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{name: "FCMPS", argLength: 2, reg: fp2flags, asm: "CEBR", typ: "Flags"}, // arg0 compare to arg1, f32
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{name: "FCMP", argLength: 2, reg: fp2flags, asm: "FCMPU", typ: "Flags"}, // arg0 compare to arg1, f64
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{name: "TESTB", argLength: 1, reg: gp1flags, asm: "AND", typ: "Flags"}, // (arg0 & 0xFF) compare to 0
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{name: "SLD", argLength: 2, reg: sh21, asm: "SLD"}, // arg0 << arg1, shift amount is mod 64
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{name: "SLW", argLength: 2, reg: sh21, asm: "SLW"}, // arg0 << arg1, shift amount is mod 32
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{name: "SLDconst", argLength: 1, reg: gp11, asm: "SLD", aux: "Int64"}, // arg0 << auxint, shift amount 0-63
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{name: "SLWconst", argLength: 1, reg: gp11, asm: "SLW", aux: "Int32"}, // arg0 << auxint, shift amount 0-31
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{name: "SRD", argLength: 2, reg: sh21, asm: "SRD"}, // unsigned arg0 >> arg1, shift amount is mod 64
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{name: "SRW", argLength: 2, reg: sh21, asm: "SRW"}, // unsigned arg0 >> arg1, shift amount is mod 32
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{name: "SRDconst", argLength: 1, reg: gp11, asm: "SRD", aux: "Int64"}, // unsigned arg0 >> auxint, shift amount 0-63
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{name: "SRWconst", argLength: 1, reg: gp11, asm: "SRW", aux: "Int32"}, // unsigned arg0 >> auxint, shift amount 0-31
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// Arithmetic shifts clobber flags.
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{name: "SRAD", argLength: 2, reg: sh21, asm: "SRAD", clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 64
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{name: "SRAW", argLength: 2, reg: sh21, asm: "SRAW", clobberFlags: true}, // signed arg0 >> arg1, shift amount is mod 32
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{name: "SRADconst", argLength: 1, reg: gp11, asm: "SRAD", aux: "Int64", clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-63
|
||
|
|
{name: "SRAWconst", argLength: 1, reg: gp11, asm: "SRAW", aux: "Int32", clobberFlags: true}, // signed arg0 >> auxint, shift amount 0-31
|
||
|
|
|
||
|
|
{name: "RLLGconst", argLength: 1, reg: gp11, asm: "RLLG", aux: "Int64"}, // arg0 rotate left auxint, rotate amount 0-63
|
||
|
|
{name: "RLLconst", argLength: 1, reg: gp11, asm: "RLL", aux: "Int32"}, // arg0 rotate left auxint, rotate amount 0-31
|
||
|
|
|
||
|
|
// unary ops
|
||
|
|
{name: "NEG", argLength: 1, reg: gp11, asm: "NEG", clobberFlags: true}, // -arg0
|
||
|
|
{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW", clobberFlags: true}, // -arg0
|
||
|
|
|
||
|
|
{name: "NOT", argLength: 1, reg: gp11, resultInArg0: true, clobberFlags: true}, // ^arg0
|
||
|
|
{name: "NOTW", argLength: 1, reg: gp11, resultInArg0: true, clobberFlags: true}, // ^arg0
|
||
|
|
|
||
|
|
{name: "FSQRT", argLength: 1, reg: fp11, asm: "FSQRT"}, // sqrt(arg0)
|
||
|
|
|
||
|
|
{name: "SUBEcarrymask", argLength: 1, reg: flagsgp, asm: "SUBE"}, // (int64)(-1) if carry is set, 0 if carry is clear.
|
||
|
|
{name: "SUBEWcarrymask", argLength: 1, reg: flagsgp, asm: "SUBE"}, // (int32)(-1) if carry is set, 0 if carry is clear.
|
||
|
|
// Note: 32-bits subtraction is not implemented in S390X. Temporarily use SUBE (64-bits).
|
||
|
|
|
||
|
|
{name: "MOVDEQ", argLength: 3, reg: gp2flags1, resultInArg0: true, asm: "MOVDEQ"}, // extract == condition from arg0
|
||
|
|
{name: "MOVDNE", argLength: 3, reg: gp2flags1, resultInArg0: true, asm: "MOVDNE"}, // extract != condition from arg0
|
||
|
|
{name: "MOVDLT", argLength: 3, reg: gp2flags1, resultInArg0: true, asm: "MOVDLT"}, // extract signed < condition from arg0
|
||
|
|
{name: "MOVDLE", argLength: 3, reg: gp2flags1, resultInArg0: true, asm: "MOVDLE"}, // extract signed <= condition from arg0
|
||
|
|
{name: "MOVDGT", argLength: 3, reg: gp2flags1, resultInArg0: true, asm: "MOVDGT"}, // extract signed > condition from arg0
|
||
|
|
{name: "MOVDGE", argLength: 3, reg: gp2flags1, resultInArg0: true, asm: "MOVDGE"}, // extract signed >= condition from arg0
|
||
|
|
|
||
|
|
// Different rules for floating point conditions because
|
||
|
|
// any comparison involving a NaN is always false and thus
|
||
|
|
// the patterns for inverting conditions cannot be used.
|
||
|
|
{name: "MOVDGTnoinv", argLength: 3, reg: gp2flags1, resultInArg0: true, asm: "MOVDGT"}, // extract floating > condition from arg0
|
||
|
|
{name: "MOVDGEnoinv", argLength: 3, reg: gp2flags1, resultInArg0: true, asm: "MOVDGE"}, // extract floating >= condition from arg0
|
||
|
|
|
||
|
|
{name: "MOVBreg", argLength: 1, reg: gp11sp, asm: "MOVB", typ: "Int64"}, // sign extend arg0 from int8 to int64
|
||
|
|
{name: "MOVBZreg", argLength: 1, reg: gp11sp, asm: "MOVBZ", typ: "UInt64"}, // zero extend arg0 from int8 to int64
|
||
|
|
{name: "MOVHreg", argLength: 1, reg: gp11sp, asm: "MOVH", typ: "Int64"}, // sign extend arg0 from int16 to int64
|
||
|
|
{name: "MOVHZreg", argLength: 1, reg: gp11sp, asm: "MOVHZ", typ: "UInt64"}, // zero extend arg0 from int16 to int64
|
||
|
|
{name: "MOVWreg", argLength: 1, reg: gp11sp, asm: "MOVW", typ: "Int64"}, // sign extend arg0 from int32 to int64
|
||
|
|
{name: "MOVWZreg", argLength: 1, reg: gp11sp, asm: "MOVWZ", typ: "UInt64"}, // zero extend arg0 from int32 to int64
|
||
|
|
|
||
|
|
{name: "MOVDconst", reg: gp01, asm: "MOVD", typ: "UInt64", aux: "Int64", rematerializeable: true}, // auxint
|
||
|
|
|
||
|
|
{name: "CFDBRA", argLength: 1, reg: fpgp, asm: "CFDBRA"}, // convert float64 to int32
|
||
|
|
{name: "CGDBRA", argLength: 1, reg: fpgp, asm: "CGDBRA"}, // convert float64 to int64
|
||
|
|
{name: "CFEBRA", argLength: 1, reg: fpgp, asm: "CFEBRA"}, // convert float32 to int32
|
||
|
|
{name: "CGEBRA", argLength: 1, reg: fpgp, asm: "CGEBRA"}, // convert float32 to int64
|
||
|
|
{name: "CEFBRA", argLength: 1, reg: gpfp, asm: "CEFBRA"}, // convert int32 to float32
|
||
|
|
{name: "CDFBRA", argLength: 1, reg: gpfp, asm: "CDFBRA"}, // convert int32 to float64
|
||
|
|
{name: "CEGBRA", argLength: 1, reg: gpfp, asm: "CEGBRA"}, // convert int64 to float32
|
||
|
|
{name: "CDGBRA", argLength: 1, reg: gpfp, asm: "CDGBRA"}, // convert int64 to float64
|
||
|
|
{name: "LEDBR", argLength: 1, reg: fp11, asm: "LEDBR"}, // convert float64 to float32
|
||
|
|
{name: "LDEBR", argLength: 1, reg: fp11, asm: "LDEBR"}, // convert float32 to float64
|
||
|
|
|
||
|
|
{name: "MOVDaddr", argLength: 1, reg: addr, aux: "SymOff", rematerializeable: true, clobberFlags: true}, // arg0 + auxint + offset encoded in aux
|
||
|
|
{name: "MOVDaddridx", argLength: 2, reg: addridx, aux: "SymOff", clobberFlags: true}, // arg0 + arg1 + auxint + aux
|
||
|
|
|
||
|
|
// auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address
|
||
|
|
{name: "MOVBZload", argLength: 2, reg: gpload, asm: "MOVBZ", aux: "SymOff", typ: "UInt8", clobberFlags: true}, // load byte from arg0+auxint+aux. arg1=mem. Zero extend.
|
||
|
|
{name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVB", aux: "SymOff", clobberFlags: true}, // ditto, sign extend to int64
|
||
|
|
{name: "MOVHZload", argLength: 2, reg: gpload, asm: "MOVHZ", aux: "SymOff", typ: "UInt16", clobberFlags: true}, // load 2 bytes from arg0+auxint+aux. arg1=mem. Zero extend.
|
||
|
|
{name: "MOVHload", argLength: 2, reg: gpload, asm: "MOVH", aux: "SymOff", clobberFlags: true}, // ditto, sign extend to int64
|
||
|
|
{name: "MOVWZload", argLength: 2, reg: gpload, asm: "MOVWZ", aux: "SymOff", typ: "UInt32", clobberFlags: true}, // load 4 bytes from arg0+auxint+aux. arg1=mem. Zero extend.
|
||
|
|
{name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVW", aux: "SymOff", clobberFlags: true}, // ditto, sign extend to int64
|
||
|
|
{name: "MOVDload", argLength: 2, reg: gpload, asm: "MOVD", aux: "SymOff", typ: "UInt64", clobberFlags: true}, // load 8 bytes from arg0+auxint+aux. arg1=mem
|
||
|
|
|
||
|
|
{name: "MOVHBRload", argLength: 2, reg: gpload, asm: "MOVHBR", aux: "SymOff", typ: "UInt16", clobberFlags: true}, // load 2 bytes from arg0+auxint+aux. arg1=mem. Reverse bytes.
|
||
|
|
{name: "MOVWBRload", argLength: 2, reg: gpload, asm: "MOVWBR", aux: "SymOff", typ: "UInt32", clobberFlags: true}, // load 4 bytes from arg0+auxint+aux. arg1=mem. Reverse bytes.
|
||
|
|
{name: "MOVDBRload", argLength: 2, reg: gpload, asm: "MOVDBR", aux: "SymOff", typ: "UInt64", clobberFlags: true}, // load 8 bytes from arg0+auxint+aux. arg1=mem. Reverse bytes.
|
||
|
|
|
||
|
|
{name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", clobberFlags: true}, // store byte in arg1 to arg0+auxint+aux. arg2=mem
|
||
|
|
{name: "MOVHstore", argLength: 3, reg: gpstore, asm: "MOVH", aux: "SymOff", typ: "Mem", clobberFlags: true}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem
|
||
|
|
{name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", clobberFlags: true}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem
|
||
|
|
{name: "MOVDstore", argLength: 3, reg: gpstore, asm: "MOVD", aux: "SymOff", typ: "Mem", clobberFlags: true}, // store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem
|
||
|
|
|
||
|
|
{name: "MVC", argLength: 3, reg: gpmvc, asm: "MVC", aux: "SymValAndOff", typ: "Mem", clobberFlags: true}, // arg0=destptr, arg1=srcptr, arg2=mem, auxint=size,off
|
||
|
|
|
||
|
|
// indexed loads/stores
|
||
|
|
// TODO(mundaym): add sign-extended indexed loads
|
||
|
|
{name: "MOVBZloadidx", argLength: 3, reg: gploadidx, asm: "MOVBZ", aux: "SymOff", clobberFlags: true}, // load a byte from arg0+arg1+auxint+aux. arg2=mem
|
||
|
|
{name: "MOVHZloadidx", argLength: 3, reg: gploadidx, asm: "MOVHZ", aux: "SymOff", clobberFlags: true}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem
|
||
|
|
{name: "MOVWZloadidx", argLength: 3, reg: gploadidx, asm: "MOVWZ", aux: "SymOff", clobberFlags: true}, // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem
|
||
|
|
{name: "MOVDloadidx", argLength: 3, reg: gploadidx, asm: "MOVD", aux: "SymOff", clobberFlags: true}, // load 8 bytes from arg0+arg1+auxint+aux. arg2=mem
|
||
|
|
{name: "MOVHBRloadidx", argLength: 3, reg: gploadidx, asm: "MOVHBR", aux: "SymOff", clobberFlags: true}, // load 2 bytes from arg0+arg1+auxint+aux. arg2=mem. Reverse bytes.
|
||
|
|
{name: "MOVWBRloadidx", argLength: 3, reg: gploadidx, asm: "MOVWBR", aux: "SymOff", clobberFlags: true}, // load 4 bytes from arg0+arg1+auxint+aux. arg2=mem. Reverse bytes.
|
||
|
|
{name: "MOVDBRloadidx", argLength: 3, reg: gploadidx, asm: "MOVDBR", aux: "SymOff", clobberFlags: true}, // load 8 bytes from arg0+arg1+auxint+aux. arg2=mem. Reverse bytes.
|
||
|
|
{name: "MOVBstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVB", aux: "SymOff", clobberFlags: true}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem
|
||
|
|
{name: "MOVHstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVH", aux: "SymOff", clobberFlags: true}, // store 2 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem
|
||
|
|
{name: "MOVWstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVW", aux: "SymOff", clobberFlags: true}, // store 4 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem
|
||
|
|
{name: "MOVDstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVD", aux: "SymOff", clobberFlags: true}, // store 8 bytes in arg2 to arg0+arg1+auxint+aux. arg3=mem
|
||
|
|
|
||
|
|
// For storeconst ops, the AuxInt field encodes both
|
||
|
|
// the value to store and an address offset of the store.
|
||
|
|
// Cast AuxInt to a ValAndOff to extract Val and Off fields.
|
||
|
|
{name: "MOVBstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVB", aux: "SymValAndOff", typ: "Mem", clobberFlags: true}, // store low byte of ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux. arg1=mem
|
||
|
|
{name: "MOVHstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVH", aux: "SymValAndOff", typ: "Mem", clobberFlags: true}, // store low 2 bytes of ...
|
||
|
|
{name: "MOVWstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVW", aux: "SymValAndOff", typ: "Mem", clobberFlags: true}, // store low 4 bytes of ...
|
||
|
|
{name: "MOVDstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVD", aux: "SymValAndOff", typ: "Mem", clobberFlags: true}, // store 8 bytes of ...
|
||
|
|
|
||
|
|
{name: "CLEAR", argLength: 2, reg: regInfo{inputs: []regMask{ptr, 0}}, asm: "CLEAR", aux: "SymValAndOff", typ: "Mem", clobberFlags: true},
|
||
|
|
|
||
|
|
{name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff", clobberFlags: true, call: true}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
|
||
|
|
{name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{ptrsp, buildReg("R12"), 0}, clobbers: callerSave}, aux: "Int64", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
|
||
|
|
{name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true, call: true}, // call deferproc. arg0=mem, auxint=argsize, returns mem
|
||
|
|
{name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64", clobberFlags: true, call: true}, // call newproc. arg0=mem, auxint=argsize, returns mem
|
||
|
|
{name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{ptr}, clobbers: callerSave}, aux: "Int64", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
|
||
|
|
|
||
|
|
// (InvertFlags (CMP a b)) == (CMP b a)
|
||
|
|
// InvertFlags is a pseudo-op which can't appear in assembly output.
|
||
|
|
{name: "InvertFlags", argLength: 1}, // reverse direction of arg0
|
||
|
|
|
||
|
|
// Pseudo-ops
|
||
|
|
{name: "LoweredGetG", argLength: 1, reg: gp01}, // arg0=mem
|
||
|
|
// Scheduler ensures LoweredGetClosurePtr occurs only in entry block,
|
||
|
|
// and sorts it to the very beginning of the block to prevent other
|
||
|
|
// use of R12 (the closure pointer)
|
||
|
|
{name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{buildReg("R12")}}},
|
||
|
|
// arg0=ptr,arg1=mem, returns void. Faults if ptr is nil.
|
||
|
|
{name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{ptrsp}}, clobberFlags: true},
|
||
|
|
|
||
|
|
// MOVDconvert converts between pointers and integers.
|
||
|
|
// We have a special op for this so as to not confuse GC
|
||
|
|
// (particularly stack maps). It takes a memory arg so it
|
||
|
|
// gets correctly ordered with respect to GC safepoints.
|
||
|
|
// arg0=ptr/int arg1=mem, output=int/ptr
|
||
|
|
{name: "MOVDconvert", argLength: 2, reg: gp11sp, asm: "MOVD"},
|
||
|
|
|
||
|
|
// Constant flag values. For any comparison, there are 5 possible
|
||
|
|
// outcomes: the three from the signed total order (<,==,>) and the
|
||
|
|
// three from the unsigned total order. The == cases overlap.
|
||
|
|
// Note: there's a sixth "unordered" outcome for floating-point
|
||
|
|
// comparisons, but we don't use such a beast yet.
|
||
|
|
// These ops are for temporary use by rewrite rules. They
|
||
|
|
// cannot appear in the generated assembly.
|
||
|
|
{name: "FlagEQ"}, // equal
|
||
|
|
{name: "FlagLT"}, // <
|
||
|
|
{name: "FlagGT"}, // >
|
||
|
|
|
||
|
|
// store multiple
|
||
|
|
{
|
||
|
|
name: "STMG2",
|
||
|
|
argLength: 4,
|
||
|
|
reg: regInfo{inputs: []regMask{ptrsp, buildReg("R1"), buildReg("R2"), 0}},
|
||
|
|
aux: "SymOff",
|
||
|
|
typ: "Mem",
|
||
|
|
asm: "STMG",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
name: "STMG3",
|
||
|
|
argLength: 5,
|
||
|
|
reg: regInfo{inputs: []regMask{ptrsp, buildReg("R1"), buildReg("R2"), buildReg("R3"), 0}},
|
||
|
|
aux: "SymOff",
|
||
|
|
typ: "Mem",
|
||
|
|
asm: "STMG",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
name: "STMG4",
|
||
|
|
argLength: 6,
|
||
|
|
reg: regInfo{inputs: []regMask{
|
||
|
|
ptrsp,
|
||
|
|
buildReg("R1"),
|
||
|
|
buildReg("R2"),
|
||
|
|
buildReg("R3"),
|
||
|
|
buildReg("R4"),
|
||
|
|
0,
|
||
|
|
}},
|
||
|
|
aux: "SymOff",
|
||
|
|
typ: "Mem",
|
||
|
|
asm: "STMG",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
name: "STM2",
|
||
|
|
argLength: 4,
|
||
|
|
reg: regInfo{inputs: []regMask{ptrsp, buildReg("R1"), buildReg("R2"), 0}},
|
||
|
|
aux: "SymOff",
|
||
|
|
typ: "Mem",
|
||
|
|
asm: "STMY",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
name: "STM3",
|
||
|
|
argLength: 5,
|
||
|
|
reg: regInfo{inputs: []regMask{ptrsp, buildReg("R1"), buildReg("R2"), buildReg("R3"), 0}},
|
||
|
|
aux: "SymOff",
|
||
|
|
typ: "Mem",
|
||
|
|
asm: "STMY",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
name: "STM4",
|
||
|
|
argLength: 6,
|
||
|
|
reg: regInfo{inputs: []regMask{
|
||
|
|
ptrsp,
|
||
|
|
buildReg("R1"),
|
||
|
|
buildReg("R2"),
|
||
|
|
buildReg("R3"),
|
||
|
|
buildReg("R4"),
|
||
|
|
0,
|
||
|
|
}},
|
||
|
|
aux: "SymOff",
|
||
|
|
typ: "Mem",
|
||
|
|
asm: "STMY",
|
||
|
|
},
|
||
|
|
|
||
|
|
// large move
|
||
|
|
// auxint = remaining bytes after loop (rem)
|
||
|
|
// arg0 = address of dst memory (in R1, changed as a side effect)
|
||
|
|
// arg1 = address of src memory (in R2, changed as a side effect)
|
||
|
|
// arg2 = pointer to last address to move in loop + 256
|
||
|
|
// arg3 = mem
|
||
|
|
// returns mem
|
||
|
|
//
|
||
|
|
// mvc: MVC $256, 0(R2), 0(R1)
|
||
|
|
// MOVD $256(R1), R1
|
||
|
|
// MOVD $256(R2), R2
|
||
|
|
// CMP R2, Rarg2
|
||
|
|
// BNE mvc
|
||
|
|
// MVC $rem, 0(R2), 0(R1) // if rem > 0
|
||
|
|
{
|
||
|
|
name: "LoweredMove",
|
||
|
|
aux: "Int64",
|
||
|
|
argLength: 4,
|
||
|
|
reg: regInfo{
|
||
|
|
inputs: []regMask{buildReg("R1"), buildReg("R2"), gpsp},
|
||
|
|
clobbers: buildReg("R1 R2"),
|
||
|
|
},
|
||
|
|
clobberFlags: true,
|
||
|
|
typ: "Mem",
|
||
|
|
},
|
||
|
|
|
||
|
|
// large clear
|
||
|
|
// auxint = remaining bytes after loop (rem)
|
||
|
|
// arg0 = address of dst memory (in R1, changed as a side effect)
|
||
|
|
// arg1 = pointer to last address to zero in loop + 256
|
||
|
|
// arg2 = mem
|
||
|
|
// returns mem
|
||
|
|
//
|
||
|
|
// clear: CLEAR $256, 0(R1)
|
||
|
|
// MOVD $256(R1), R1
|
||
|
|
// CMP R1, Rarg2
|
||
|
|
// BNE clear
|
||
|
|
// CLEAR $rem, 0(R1) // if rem > 0
|
||
|
|
{
|
||
|
|
name: "LoweredZero",
|
||
|
|
aux: "Int64",
|
||
|
|
argLength: 3,
|
||
|
|
reg: regInfo{
|
||
|
|
inputs: []regMask{buildReg("R1"), gpsp},
|
||
|
|
clobbers: buildReg("R1"),
|
||
|
|
},
|
||
|
|
clobberFlags: true,
|
||
|
|
typ: "Mem",
|
||
|
|
},
|
||
|
|
}
|
||
|
|
|
||
|
|
var S390Xblocks = []blockData{
|
||
|
|
{name: "EQ"},
|
||
|
|
{name: "NE"},
|
||
|
|
{name: "LT"},
|
||
|
|
{name: "LE"},
|
||
|
|
{name: "GT"},
|
||
|
|
{name: "GE"},
|
||
|
|
{name: "GTF"}, // FP comparison
|
||
|
|
{name: "GEF"}, // FP comparison
|
||
|
|
}
|
||
|
|
|
||
|
|
archs = append(archs, arch{
|
||
|
|
name: "S390X",
|
||
|
|
pkg: "cmd/internal/obj/s390x",
|
||
|
|
genfile: "../../s390x/ssa.go",
|
||
|
|
ops: S390Xops,
|
||
|
|
blocks: S390Xblocks,
|
||
|
|
regnames: regNamesS390X,
|
||
|
|
gpregmask: gp,
|
||
|
|
fpregmask: fp,
|
||
|
|
framepointerreg: -1, // not used
|
||
|
|
})
|
||
|
|
}
|