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[dev.simd] cmd/compile, simd: rename Masked$OP to $(OP)Masked.

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This CL is generated by CL 686575.

Change-Id: I1483189a1ae9bed51446fd69daab3f7b128549ae
Reviewed-on: https://go-review.googlesource.com/c/go/+/686516
Reviewed-by: David Chase <drchase@google.com>
TryBot-Bypass: David Chase <drchase@google.com>
This commit is contained in:
Junyang Shao 2025-07-08 18:18:55 +00:00 • committed by David Chase
parent 983e81ce57
commit 029d7ec3e9
10 changed files with 34093 additions and 34093 deletions
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92
src/cmd/compile/internal/amd64/simdssa.go
View file

@ -425,12 +425,6 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMINUQMasked128,
ssa.OpAMD64VPMINUQMasked256,
ssa.OpAMD64VPMINUQMasked512,
ssa.OpAMD64VMULPSMasked128,
ssa.OpAMD64VMULPSMasked256,
ssa.OpAMD64VMULPSMasked512,
ssa.OpAMD64VMULPDMasked128,
ssa.OpAMD64VMULPDMasked256,
ssa.OpAMD64VMULPDMasked512,
ssa.OpAMD64VSCALEFPSMasked128,
ssa.OpAMD64VSCALEFPSMasked256,
ssa.OpAMD64VSCALEFPSMasked512,
@ -458,6 +452,12 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMULLQMasked128,
ssa.OpAMD64VPMULLQMasked256,
ssa.OpAMD64VPMULLQMasked512,
ssa.OpAMD64VMULPSMasked128,
ssa.OpAMD64VMULPSMasked256,
ssa.OpAMD64VMULPSMasked512,
ssa.OpAMD64VMULPDMasked128,
ssa.OpAMD64VMULPDMasked256,
ssa.OpAMD64VMULPDMasked512,
ssa.OpAMD64VPORDMasked128,
ssa.OpAMD64VPORDMasked256,
ssa.OpAMD64VPORDMasked512,
@ -888,12 +888,12 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPEXTRQ128:
p = simdFpgpImm8(s, v)
case ssa.OpAMD64VGF2P8AFFINEQBMasked128,
ssa.OpAMD64VGF2P8AFFINEQBMasked256,
ssa.OpAMD64VGF2P8AFFINEQBMasked512,
ssa.OpAMD64VGF2P8AFFINEINVQBMasked128,
case ssa.OpAMD64VGF2P8AFFINEINVQBMasked128,
ssa.OpAMD64VGF2P8AFFINEINVQBMasked256,
ssa.OpAMD64VGF2P8AFFINEINVQBMasked512,
ssa.OpAMD64VGF2P8AFFINEQBMasked128,
ssa.OpAMD64VGF2P8AFFINEQBMasked256,
ssa.OpAMD64VGF2P8AFFINEQBMasked512,
ssa.OpAMD64VPSHLDWMasked128,
ssa.OpAMD64VPSHLDWMasked256,
ssa.OpAMD64VPSHLDWMasked512,
@ -1017,12 +1017,12 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VFMSUBADD213PDMasked128,
ssa.OpAMD64VFMSUBADD213PDMasked256,
ssa.OpAMD64VFMSUBADD213PDMasked512,
ssa.OpAMD64VGF2P8AFFINEQBMasked128,
ssa.OpAMD64VGF2P8AFFINEQBMasked256,
ssa.OpAMD64VGF2P8AFFINEQBMasked512,
ssa.OpAMD64VGF2P8AFFINEINVQBMasked128,
ssa.OpAMD64VGF2P8AFFINEINVQBMasked256,
ssa.OpAMD64VGF2P8AFFINEINVQBMasked512,
ssa.OpAMD64VGF2P8AFFINEQBMasked128,
ssa.OpAMD64VGF2P8AFFINEQBMasked256,
ssa.OpAMD64VGF2P8AFFINEQBMasked512,
ssa.OpAMD64VGF2P8MULBMasked128,
ssa.OpAMD64VGF2P8MULBMasked256,
ssa.OpAMD64VGF2P8MULBMasked512,
@ -1086,12 +1086,6 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMINUQMasked128,
ssa.OpAMD64VPMINUQMasked256,
ssa.OpAMD64VPMINUQMasked512,
ssa.OpAMD64VMULPSMasked128,
ssa.OpAMD64VMULPSMasked256,
ssa.OpAMD64VMULPSMasked512,
ssa.OpAMD64VMULPDMasked128,
ssa.OpAMD64VMULPDMasked256,
ssa.OpAMD64VMULPDMasked512,
ssa.OpAMD64VSCALEFPSMasked128,
ssa.OpAMD64VSCALEFPSMasked256,
ssa.OpAMD64VSCALEFPSMasked512,
@ -1119,18 +1113,24 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMULLQMasked128,
ssa.OpAMD64VPMULLQMasked256,
ssa.OpAMD64VPMULLQMasked512,
ssa.OpAMD64VMULPSMasked128,
ssa.OpAMD64VMULPSMasked256,
ssa.OpAMD64VMULPSMasked512,
ssa.OpAMD64VMULPDMasked128,
ssa.OpAMD64VMULPDMasked256,
ssa.OpAMD64VMULPDMasked512,
ssa.OpAMD64VPORDMasked128,
ssa.OpAMD64VPORDMasked256,
ssa.OpAMD64VPORDMasked512,
ssa.OpAMD64VPORQMasked128,
ssa.OpAMD64VPORQMasked256,
ssa.OpAMD64VPORQMasked512,
ssa.OpAMD64VPMADDWDMasked128,
ssa.OpAMD64VPMADDWDMasked256,
ssa.OpAMD64VPMADDWDMasked512,
ssa.OpAMD64VPDPWSSDMasked128,
ssa.OpAMD64VPDPWSSDMasked256,
ssa.OpAMD64VPDPWSSDMasked512,
ssa.OpAMD64VPMADDWDMasked128,
ssa.OpAMD64VPMADDWDMasked256,
ssa.OpAMD64VPMADDWDMasked512,
ssa.OpAMD64VPOPCNTBMasked128,
ssa.OpAMD64VPOPCNTBMasked256,
ssa.OpAMD64VPOPCNTBMasked512,
@ -1188,9 +1188,6 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPDPBUSDSMasked128,
ssa.OpAMD64VPDPBUSDSMasked256,
ssa.OpAMD64VPDPBUSDSMasked512,
ssa.OpAMD64VPSLLQMasked128,
ssa.OpAMD64VPSLLQMasked256,
ssa.OpAMD64VPSLLQMasked512,
ssa.OpAMD64VPSHLDWMasked128,
ssa.OpAMD64VPSHLDWMasked256,
ssa.OpAMD64VPSHLDWMasked512,
@ -1200,9 +1197,9 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPSHLDQMasked128,
ssa.OpAMD64VPSHLDQMasked256,
ssa.OpAMD64VPSHLDQMasked512,
ssa.OpAMD64VPSRLQMasked128,
ssa.OpAMD64VPSRLQMasked256,
ssa.OpAMD64VPSRLQMasked512,
ssa.OpAMD64VPSLLQMasked128,
ssa.OpAMD64VPSLLQMasked256,
ssa.OpAMD64VPSLLQMasked512,
ssa.OpAMD64VPSHRDWMasked128,
ssa.OpAMD64VPSHRDWMasked256,
ssa.OpAMD64VPSHRDWMasked512,
@ -1212,18 +1209,12 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPSHRDQMasked128,
ssa.OpAMD64VPSHRDQMasked256,
ssa.OpAMD64VPSHRDQMasked512,
ssa.OpAMD64VPSRLQMasked128,
ssa.OpAMD64VPSRLQMasked256,
ssa.OpAMD64VPSRLQMasked512,
ssa.OpAMD64VPSRAQMasked128,
ssa.OpAMD64VPSRAQMasked256,
ssa.OpAMD64VPSRAQMasked512,
ssa.OpAMD64VPSLLVWMasked128,
ssa.OpAMD64VPSLLVWMasked256,
ssa.OpAMD64VPSLLVWMasked512,
ssa.OpAMD64VPSLLVDMasked128,
ssa.OpAMD64VPSLLVDMasked256,
ssa.OpAMD64VPSLLVDMasked512,
ssa.OpAMD64VPSLLVQMasked128,
ssa.OpAMD64VPSLLVQMasked256,
ssa.OpAMD64VPSLLVQMasked512,
ssa.OpAMD64VPSHLDVWMasked128,
ssa.OpAMD64VPSHLDVWMasked256,
ssa.OpAMD64VPSHLDVWMasked512,
@ -1233,15 +1224,15 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPSHLDVQMasked128,
ssa.OpAMD64VPSHLDVQMasked256,
ssa.OpAMD64VPSHLDVQMasked512,
ssa.OpAMD64VPSRLVWMasked128,
ssa.OpAMD64VPSRLVWMasked256,
ssa.OpAMD64VPSRLVWMasked512,
ssa.OpAMD64VPSRLVDMasked128,
ssa.OpAMD64VPSRLVDMasked256,
ssa.OpAMD64VPSRLVDMasked512,
ssa.OpAMD64VPSRLVQMasked128,
ssa.OpAMD64VPSRLVQMasked256,
ssa.OpAMD64VPSRLVQMasked512,
ssa.OpAMD64VPSLLVWMasked128,
ssa.OpAMD64VPSLLVWMasked256,
ssa.OpAMD64VPSLLVWMasked512,
ssa.OpAMD64VPSLLVDMasked128,
ssa.OpAMD64VPSLLVDMasked256,
ssa.OpAMD64VPSLLVDMasked512,
ssa.OpAMD64VPSLLVQMasked128,
ssa.OpAMD64VPSLLVQMasked256,
ssa.OpAMD64VPSLLVQMasked512,
ssa.OpAMD64VPSHRDVWMasked128,
ssa.OpAMD64VPSHRDVWMasked256,
ssa.OpAMD64VPSHRDVWMasked512,
@ -1251,6 +1242,15 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPSHRDVQMasked128,
ssa.OpAMD64VPSHRDVQMasked256,
ssa.OpAMD64VPSHRDVQMasked512,
ssa.OpAMD64VPSRLVWMasked128,
ssa.OpAMD64VPSRLVWMasked256,
ssa.OpAMD64VPSRLVWMasked512,
ssa.OpAMD64VPSRLVDMasked128,
ssa.OpAMD64VPSRLVDMasked256,
ssa.OpAMD64VPSRLVDMasked512,
ssa.OpAMD64VPSRLVQMasked128,
ssa.OpAMD64VPSRLVQMasked256,
ssa.OpAMD64VPSRLVQMasked512,
ssa.OpAMD64VPSRAVWMasked128,
ssa.OpAMD64VPSRAVWMasked256,
ssa.OpAMD64VPSRAVWMasked512,

1530
src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
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File diff suppressed because it is too large Load diff

708
src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
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File diff suppressed because it is too large Load diff

1530
src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
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File diff suppressed because it is too large Load diff

20182
src/cmd/compile/internal/ssa/opGen.go
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File diff suppressed because it is too large Load diff

32328
src/cmd/compile/internal/ssa/rewriteAMD64.go
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File diff suppressed because it is too large Load diff

1530
src/cmd/compile/internal/ssagen/simdintrinsics.go
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File diff suppressed because it is too large Load diff

7702
src/simd/ops_amd64.go
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File diff suppressed because it is too large Load diff

6
src/simd/simd_test.go
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@ -43,7 +43,7 @@ func TestType(t *testing.T) {
return
}
v.z = maskT(simd.LoadInt32x4(&maskv).AsMask32x4())
*v.y = v.y.MaskedAdd(v.x, simd.Mask32x4(v.z))
*v.y = v.y.AddMasked(v.x, simd.Mask32x4(v.z))
got := [4]int32{}
v.y.Store(&got)
@ -125,7 +125,7 @@ func TestMaskConversion(t *testing.T) {
mask := y.Sub(x).AsMask32x4()
v = [4]int32{5, 6, 7, 8}
y = simd.LoadInt32x4(&v)
y = y.MaskedAdd(x, mask)
y = y.AddMasked(x, mask)
got := [4]int32{6, 0, 8, 0}
y.Store(&v)
for i := range 4 {
@ -148,7 +148,7 @@ func TestMaskedAdd(t *testing.T) {
t.Skip("Test requires HasAVX512, not available on this hardware")
return
}
testInt32x4BinaryMasked(t, []int32{1, 2, 3, 4}, []int32{5, 6, 7, 8}, []int32{-1, -1, 0, 0}, []int32{6, 8, 0, 0}, "MaskedAdd")
testInt32x4BinaryMasked(t, []int32{1, 2, 3, 4}, []int32{5, 6, 7, 8}, []int32{-1, -1, 0, 0}, []int32{6, 8, 0, 0}, "AddMasked")
}
// checkInt8Slices ensures that b and a are equal, to the end of b.

2578
src/simd/simd_wrapped_test.go
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File diff suppressed because it is too large Load diff