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cmd/internal/obj/loong64: change the plan9 format of the prefetch instruction PRELDX
before:
MOVV $n + $offset, Roff
PRELDX (Rbase)(Roff), $hint
after:
PRELDX offset(Rbase), $n, $hint
This instruction is supported in CL 671875, but is not actually used
Change-Id: I943d488ea6dc77781cd796ef480a89fede666bab
Reviewed-on: https://go-review.googlesource.com/c/go/+/673155
Reviewed-by: Meidan Li <limeidan@loongson.cn>
Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
This commit is contained in:
Guoqi Chen
abner chenc
parent
4b5a64f467
commit
045b5c1bfb
5 changed files with 93 additions and 19 deletions
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@ -676,6 +676,11 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
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prog.From = a[0]
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prog.To = a[1]
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prog.RegTo2 = a[2].Reg
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case arch.IsLoong64PRELD(op):
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prog.From = a[0]
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prog.AddRestSourceArgs([]obj.Addr{a[1], a[2]})
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default:
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prog.From = a[0]
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prog.Reg = p.getRegister(prog, op, &a[1])
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@ -1035,6 +1035,3 @@ lable2:
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PRELD (R4), $0 // 8000c02a
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PRELD -1(R4), $8 // 88fcff2a
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PRELD 8(R4), $31 // 9f20c02a
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PRELDX (R4)(R5), $0 // 80142c38
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PRELDX (R4)(R6), $8 // 88182c38
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PRELDX (R4)(R7), $31 // 9f1c2c38
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@ -15,3 +15,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
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AND $0xfedcba9876543210, R4 // AND $-81985529216486896, R4 // 7ea8ec14de4388031e539717deb73f0384f81400
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AND $0xfedcba9876543210, R5, R4 // AND $-81985529216486896, R5, R4 // 7ea8ec14de4388031e539717deb73f03a4f81400
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PRELDX 0(R7), $0x80001021, $0 // PRELDX (R7), $2147487777, $0 // 1e020014de0380031e000016de130003e0782c38
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PRELDX -1(R7), $0x1021, $2 // PRELDX -1(R7), $4129, $2 // fe030014deffbf031e000016de030003e2782c38
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PRELDX 8(R7), $0x80100800, $31 // PRELDX 8(R7), $2148534272, $31 // 1ee00714de238003fe1f0016de130003ff782c38
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PRELDX 16(R7), $0x202040, $1 // PRELDX 16(R7), $2105408, $1 // 1e200014de4380033e000216de030003e1782c38
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@ -416,8 +416,8 @@ var optab = []Optab{
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{AVMOVQ, C_ELEM, C_NONE, C_NONE, C_ARNG, C_NONE, 45, 4, 0, 0},
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{APRELD, C_SOREG, C_NONE, C_U5CON, C_NONE, C_NONE, 46, 4, 0, 0},
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{APRELDX, C_ROFF, C_NONE, C_U5CON, C_NONE, C_NONE, 47, 4, 0, 0},
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{APRELD, C_SOREG, C_U5CON, C_NONE, C_NONE, C_NONE, 46, 4, 0, 0},
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{APRELDX, C_SOREG, C_DCON, C_U5CON, C_NONE, C_NONE, 47, 20, 0, 0},
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{obj.APCALIGN, C_U12CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
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{obj.APCDATA, C_32CON, C_NONE, C_NONE, C_32CON, C_NONE, 0, 0, 0, 0},
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@ -1105,6 +1105,22 @@ func (c *ctxt0) oplook(p *obj.Prog) *Optab {
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c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
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}
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restArgsIndex := 0
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restArgsLen := len(p.RestArgs)
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if restArgsLen > 2 {
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c.ctxt.Diag("too many RestArgs: got %v, maximum is 2\n", restArgsLen)
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return nil
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}
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restArgsv := [2]int{C_NONE + 1, C_NONE + 1}
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for i, ap := range p.RestArgs {
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restArgsv[i] = int(ap.Addr.Class)
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if restArgsv[i] == 0 {
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restArgsv[i] = c.aclass(&ap.Addr) + 1
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ap.Addr.Class = int8(restArgsv[i])
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}
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}
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a1 := int(p.Optab)
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if a1 != 0 {
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return &optab[a1-1]
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@ -1130,6 +1146,9 @@ func (c *ctxt0) oplook(p *obj.Prog) *Optab {
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a2 := C_NONE
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if p.Reg != 0 {
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a2 = c.rclass(p.Reg)
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} else if restArgsLen > 0 {
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a2 = restArgsv[restArgsIndex] - 1
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restArgsIndex++
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}
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// 2nd destination operand
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@ -1140,22 +1159,20 @@ func (c *ctxt0) oplook(p *obj.Prog) *Optab {
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// 3rd source operand
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a3 := C_NONE
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if len(p.RestArgs) > 0 {
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a3 = int(p.RestArgs[0].Class)
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if a3 == 0 {
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a3 = c.aclass(&p.RestArgs[0].Addr) + 1
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p.RestArgs[0].Class = int8(a3)
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}
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a3--
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if restArgsLen > 0 && restArgsIndex < restArgsLen {
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a3 = restArgsv[restArgsIndex] - 1
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restArgsIndex++
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}
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ops := oprange[p.As&obj.AMask]
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c1 := &xcmp[a1]
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c2 := &xcmp[a2]
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c3 := &xcmp[a3]
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c4 := &xcmp[a4]
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c5 := &xcmp[a5]
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for i := range ops {
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op := &ops[i]
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if (int(op.reg) == a2) && c3[op.from3] && c1[op.from1] && c4[op.to1] && (int(op.to2) == a5) {
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if c1[op.from1] && c2[op.reg] && c3[op.from3] && c4[op.to1] && c5[op.to2] {
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p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
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return op
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}
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@ -2457,16 +2474,40 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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c.checkindex(p, index, m)
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o1 = v | (index << 10) | (vj << 5) | vd
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case 46:
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// preld offset(Rbase), hint
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case 46: // preld offset(Rbase), $hint
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offs := c.regoff(&p.From)
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hint := p.GetFrom3().Offset
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o1 = OP_12IR_5I(c.opiir(p.As), uint32(offs), uint32(p.From.Reg), uint32(hint))
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case 47:
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// preldx (Rbase)(Roff), hint
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hint := p.GetFrom3().Offset
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o1 = OP_5IRR(c.opirr(p.As), uint32(p.From.Index), uint32(p.From.Reg), uint32(hint))
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case 47: // preldx offset(Rbase), $n, $hint
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offs := c.regoff(&p.From)
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hint := p.RestArgs[1].Offset
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n := uint64(p.GetFrom3().Offset)
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addrSeq := (n >> 0) & 0x1
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blkSize := (n >> 1) & 0x7ff
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blkNums := (n >> 12) & 0x1ff
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stride := (n >> 21) & 0xffff
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if blkSize > 1024 {
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c.ctxt.Diag("%v: block_size amount out of range[16, 1024]: %v\n", p, blkSize)
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}
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if blkNums > 256 {
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c.ctxt.Diag("%v: block_nums amount out of range[1, 256]: %v\n", p, blkSize)
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}
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v := (uint64(offs) & 0xffff)
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v += addrSeq << 16
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v += ((blkSize / 16) - 1) << 20
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v += (blkNums - 1) << 32
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v += stride << 44
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o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
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o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
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o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
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o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
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o5 = OP_5IRR(c.opirr(p.As), uint32(REGTMP), uint32(p.From.Reg), uint32(hint))
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case 49:
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if p.As == ANOOP {
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@ -226,5 +226,31 @@ Note: In the following sections 3.1 to 3.6, "ui4" (4-bit unsigned int immediate)
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- When using the AM*_.W[U]/D[U] instruction, registers rd and rj cannot be the same,
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otherwise an exception is triggered, and rd and rk cannot be the same, otherwise
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the execution result is uncertain.
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3. Prefetch instructions
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Instruction format:
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PRELD offset(Rbase), $hint
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PRELDX offset(Rbase), $n, $hint
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Mapping between Go and platform assembly:
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Go assembly | platform assembly
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PRELD offset(Rbase), $hint | preld hint, Rbase, offset
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PRELDX offset(Rbase), $n, $hint | move rk, $x; preldx hint, Rbase, rk
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note: $x is the value after $n and offset are reassembled
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Definition of hint value:
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0: load to L1
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2: load to L3
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8: store to L1
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The meaning of the rest of values is not defined yet, and the processor executes it as NOP
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Definition of $n in the PRELDX instruction:
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bit[0]: address sequence, 0 indicating ascending and 1 indicating descending
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bits[11:1]: block size, the value range is [16, 1024], and it must be an integer multiple of 16
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bits[20:12]: block num, the value range is [1, 256]
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bits[36:21]: stride, the value range is [0, 0xffff]
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*/
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package loong64
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