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cmd/internal/obj/loong64: add CPUCFG instructions support

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The CPUCFG instruction is used to dynamically obtain the features
supported by the current CPU during the running of the program.

Go asm syntax:
	CPUCFG RJ, RD

Equivalent platform assembler syntax:
	cpucfg rd, rj

Reference: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html

Change-Id: I545110ff837ae9c5ccd7c448a1daf2d1277f9aa1
Reviewed-on: https://go-review.googlesource.com/c/go/+/493436
Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn>
Reviewed-by: Cherry Mui <cherryyz@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
This commit is contained in:
Guoqi Chen 2023-04-07 22:37:57 +08:00 • committed by abner chenc
parent 456785ceed
commit 0a9321ad7f
4 changed files with 10 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

1
src/cmd/asm/internal/asm/testdata/loong64enc1.s vendored
View file

@ -51,6 +51,7 @@ lable2:
ROTRV R4, R5, R6 // a6901b00 ROTRV R4, R5, R6 // a6901b00
CLO R4, R5 // 85100000 CLO R4, R5 // 85100000
CLZ R4, R5 // 85140000 CLZ R4, R5 // 85140000
CPUCFG R4, R5 // 856c0000
ADDF F4, F5 // a5900001 ADDF F4, F5 // a5900001
ADDF F4, R5, F6 // a6900001 ADDF F4, R5, F6 // a6900001
CMPEQF F4, R5 // a010120c CMPEQF F4, R5 // a010120c

1
src/cmd/internal/obj/loong64/a.out.go
View file

@ -448,6 +448,7 @@ const (
ARDTIMELW ARDTIMELW
ARDTIMEHW ARDTIMEHW
ARDTIMED ARDTIMED
ACPUCFG
ALAST ALAST

1
src/cmd/internal/obj/loong64/anames.go
View file

@ -182,5 +182,6 @@ var Anames = []string{
"RDTIMELW", "RDTIMELW",
"RDTIMEHW", "RDTIMEHW",
"RDTIMED", "RDTIMED",
"CPUCFG",
"LAST", "LAST",
} }

10
src/cmd/internal/obj/loong64/asm.go
View file

@ -1230,6 +1230,7 @@ func buildop(ctxt *obj.Link) {
case ACLO: case ACLO:
opset(ACLZ, r0) opset(ACLZ, r0)
opset(ACPUCFG, r0)
case ATEQ: case ATEQ:
opset(ATNE, r0) opset(ATNE, r0)
@ -1420,14 +1421,15 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg)) o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
case 9: // sll r1,[r2],r3 case 9: // sll r1,[r2],r3
if p.As != ACLO && p.As != ACLZ { switch p.As {
case ACLO, ACLZ, ACPUCFG:
o1 = OP_RR(c.oprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg))
default:
r := int(p.Reg) r := int(p.Reg)
if r == 0 { if r == 0 {
r = int(p.To.Reg) r = int(p.To.Reg)
} }
o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg)) o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
} else { // clo r1,r2
o1 = OP_RR(c.oprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg))
} }
case 10: // add $con,[r1],r2 ==> mov $con, t; add t,[r1],r2 case 10: // add $con,[r1],r2 ==> mov $con, t; add t,[r1],r2
@ -2091,6 +2093,8 @@ func (c *ctxt0) oprr(a obj.As) uint32 {
return 0x4 << 10 return 0x4 << 10
case ACLZ: case ACLZ:
return 0x5 << 10 return 0x5 << 10
case ACPUCFG:
return 0x1b << 10
case ARDTIMELW: case ARDTIMELW:
return 0x18 << 10 return 0x18 << 10
case ARDTIMEHW: case ARDTIMEHW: