test/codegen: test negation with add/sub on riscv64

Change-Id: Ic0eca86d3c93707ebd7c716e774ebda55af4f196
Reviewed-on: https://go-review.googlesource.com/c/go/+/703755
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Julian Zhu <jz531210@gmail.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Joel Sing <joel@sing.id.au>
This commit is contained in:
Meng Zhuo 2025-11-13 16:13:31 +08:00
parent 2e509e61ef
commit 0d0d5c9a82

View file

@ -172,20 +172,26 @@ func SubAddSimplify2(a, b, c int) (int, int, int, int, int, int) {
// mips:"SUB" -"ADD" // mips:"SUB" -"ADD"
// mips64:"SUBV" -"ADDV" // mips64:"SUBV" -"ADDV"
// loong64:"SUBV" -"ADDV" // loong64:"SUBV" -"ADDV"
// riscv64:-"ADD"
r := (a + b) - (a + c) r := (a + b) - (a + c)
// amd64:-"ADDQ" // amd64:-"ADDQ"
// riscv64:-"ADD"
r1 := (a + b) - (c + a) r1 := (a + b) - (c + a)
// amd64:-"ADDQ" // amd64:-"ADDQ"
// riscv64:-"ADD"
r2 := (b + a) - (a + c) r2 := (b + a) - (a + c)
// amd64:-"ADDQ" // amd64:-"ADDQ"
// riscv64:-"ADD"
r3 := (b + a) - (c + a) r3 := (b + a) - (c + a)
// amd64:-"SUBQ" // amd64:-"SUBQ"
// arm64:-"SUB" // arm64:-"SUB"
// mips:"ADD" -"SUB" // mips:"ADD" -"SUB"
// mips64:"ADDV" -"SUBV" // mips64:"ADDV" -"SUBV"
// loong64:"ADDV" -"SUBV" // loong64:"ADDV" -"SUBV"
// riscv64:-"SUB"
r4 := (a - c) + (c + b) r4 := (a - c) + (c + b)
// amd64:-"SUBQ" // amd64:-"SUBQ"
// riscv64:-"SUB"
r5 := (a - c) + (b + c) r5 := (a - c) + (b + c)
return r, r1, r2, r3, r4, r5 return r, r1, r2, r3, r4, r5
} }