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[dev.ssa] cmd/compile: add aux typing, flags to ops

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Add the aux type to opcodes.
Add rematerializeable as a flag.

Change-Id: I906e19281498f3ee51bb136299bf26e13a54b2ec
Reviewed-on: https://go-review.googlesource.com/19088
Run-TryBot: Keith Randall <khr@golang.org>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Todd Neal <todd@tneal.org>
This commit is contained in:
Keith Randall 2016-01-31 11:39:39 -08:00
parent c87a62f32b
commit 16b1fce921
19 changed files with 685 additions and 476 deletions
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8
src/cmd/compile/internal/gc/ssa.go
View file

@ -4022,11 +4022,11 @@ func (s *genState) genValue(v *ssa.Value) {
var i int64
switch v.Op {
case ssa.OpAMD64MOVBconst:
i = int64(int8(v.AuxInt))
i = int64(v.AuxInt8())
case ssa.OpAMD64MOVWconst:
i = int64(int16(v.AuxInt))
i = int64(v.AuxInt16())
case ssa.OpAMD64MOVLconst:
i = int64(int32(v.AuxInt))
i = int64(v.AuxInt32())
case ssa.OpAMD64MOVQconst:
i = v.AuxInt
}
@ -4116,7 +4116,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64MOVQstoreconst, ssa.OpAMD64MOVLstoreconst, ssa.OpAMD64MOVWstoreconst, ssa.OpAMD64MOVBstoreconst:
p := Prog(v.Op.Asm())
p.From.Type = obj.TYPE_CONST
sc := ssa.ValAndOff(v.AuxInt)
sc := v.AuxValAndOff()
i := sc.Val()
switch v.Op {
case ssa.OpAMD64MOVBstoreconst:

24
src/cmd/compile/internal/ssa/check.go
View file

@ -148,9 +148,27 @@ func checkFunc(f *Func) {
}
for _, v := range b.Values {
switch v.Aux.(type) {
case bool, float32, float64:
f.Fatalf("value %v has an Aux value of type %T, should be AuxInt", v.LongString(), v.Aux)
// Check to make sure aux values make sense.
canHaveAux := false
canHaveAuxInt := false
switch opcodeTable[v.Op].auxType {
case auxNone:
case auxBool, auxInt8, auxInt16, auxInt32, auxInt64, auxFloat:
canHaveAuxInt = true
case auxString, auxSym:
canHaveAux = true
case auxSymOff, auxSymValAndOff:
canHaveAuxInt = true
canHaveAux = true
default:
f.Fatalf("unknown aux type for %s", v.Op)
}
if !canHaveAux && v.Aux != nil {
f.Fatalf("value %v has an Aux value %v but shouldn't", v.LongString(), v.Aux)
}
if !canHaveAuxInt && v.AuxInt != 0 {
f.Fatalf("value %v has an AuxInt value %d but shouldn't", v.LongString(), v.AuxInt)
}
for _, arg := range v.Args {

8
src/cmd/compile/internal/ssa/deadcode_test.go
View file

@ -10,7 +10,7 @@ func TestDeadLoop(t *testing.T) {
c := testConfig(t)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit")),
Bloc("exit",
Exit("mem")),
@ -40,7 +40,7 @@ func TestDeadValue(t *testing.T) {
c := testConfig(t)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("deadval", OpConst64, TypeInt64, 37, nil),
Goto("exit")),
Bloc("exit",
@ -64,7 +64,7 @@ func TestNeverTaken(t *testing.T) {
fun := Fun(c, "entry",
Bloc("entry",
Valu("cond", OpConstBool, TypeBool, 0, nil),
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
If("cond", "then", "else")),
Bloc("then",
Goto("exit")),
@ -98,7 +98,7 @@ func TestNestedDeadBlocks(t *testing.T) {
c := testConfig(t)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("cond", OpConstBool, TypeBool, 0, nil),
If("cond", "b2", "b4")),
Bloc("b2",

6
src/cmd/compile/internal/ssa/deadstore_test.go
View file

@ -12,7 +12,7 @@ func TestDeadStore(t *testing.T) {
ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr", Elem_: elemType} // dummy for testing
fun := Fun(c, "entry",
Bloc("entry",
Valu("start", OpInitMem, TypeMem, 0, ".mem"),
Valu("start", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Valu("v", OpConstBool, TypeBool, 1, nil),
Valu("addr1", OpAddr, ptrType, 0, nil, "sb"),
@ -47,7 +47,7 @@ func TestDeadStorePhi(t *testing.T) {
ptrType := &TypeImpl{Size_: 8, Ptr: true, Name: "testptr"} // dummy for testing
fun := Fun(c, "entry",
Bloc("entry",
Valu("start", OpInitMem, TypeMem, 0, ".mem"),
Valu("start", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Valu("v", OpConstBool, TypeBool, 1, nil),
Valu("addr", OpAddr, ptrType, 0, nil, "sb"),
@ -74,7 +74,7 @@ func TestDeadStoreTypes(t *testing.T) {
t2 := &TypeImpl{Size_: 4, Ptr: true, Name: "t2"}
fun := Fun(c, "entry",
Bloc("entry",
Valu("start", OpInitMem, TypeMem, 0, ".mem"),
Valu("start", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Valu("v", OpConstBool, TypeBool, 1, nil),
Valu("addr1", OpAddr, t1, 0, nil, "sb"),

26
src/cmd/compile/internal/ssa/dom_test.go
View file

@ -20,7 +20,7 @@ func genLinear(size int) []bloc {
var blocs []bloc
blocs = append(blocs,
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto(blockn(0)),
),
)
@ -43,7 +43,7 @@ func genFwdBack(size int) []bloc {
var blocs []bloc
blocs = append(blocs,
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil),
Goto(blockn(0)),
),
@ -73,7 +73,7 @@ func genManyPred(size int) []bloc {
var blocs []bloc
blocs = append(blocs,
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil),
Goto(blockn(0)),
),
@ -111,7 +111,7 @@ func genMaxPred(size int) []bloc {
var blocs []bloc
blocs = append(blocs,
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil),
Goto(blockn(0)),
),
@ -136,7 +136,7 @@ func genMaxPredValue(size int) []bloc {
var blocs []bloc
blocs = append(blocs,
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil),
Goto(blockn(0)),
),
@ -223,7 +223,7 @@ func TestDominatorsSingleBlock(t *testing.T) {
c := testConfig(t)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Exit("mem")))
doms := map[string]string{}
@ -238,7 +238,7 @@ func TestDominatorsSimple(t *testing.T) {
c := testConfig(t)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("a")),
Bloc("a",
Goto("b")),
@ -266,7 +266,7 @@ func TestDominatorsMultPredFwd(t *testing.T) {
c := testConfig(t)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil),
If("p", "a", "c")),
Bloc("a",
@ -294,7 +294,7 @@ func TestDominatorsDeadCode(t *testing.T) {
c := testConfig(t)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 0, nil),
If("p", "b3", "b5")),
Bloc("b2", Exit("mem")),
@ -319,7 +319,7 @@ func TestDominatorsMultPredRev(t *testing.T) {
Bloc("entry",
Goto("first")),
Bloc("first",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil),
Goto("a")),
Bloc("a",
@ -348,7 +348,7 @@ func TestDominatorsMultPred(t *testing.T) {
c := testConfig(t)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil),
If("p", "a", "c")),
Bloc("a",
@ -376,7 +376,7 @@ func TestPostDominators(t *testing.T) {
c := testConfig(t)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil),
If("p", "a", "c")),
Bloc("a",
@ -403,7 +403,7 @@ func TestInfiniteLoop(t *testing.T) {
// note lack of an exit block
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("p", OpConstBool, TypeBool, 1, nil),
Goto("a")),
Bloc("a",

34
src/cmd/compile/internal/ssa/func_test.go
View file

@ -6,7 +6,7 @@
// As an example, the following func
//
// b1:
// v1 = Arg <mem> [.mem]
// v1 = InitMem <mem>
// Plain -> b2
// b2:
// Exit v1
@ -18,7 +18,7 @@
//
// fun := Fun("entry",
// Bloc("entry",
// Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
// Valu("mem", OpInitMem, TypeMem, 0, nil),
// Goto("exit")),
// Bloc("exit",
// Exit("mem")),
@ -267,7 +267,7 @@ func TestArgs(t *testing.T) {
Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"),
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit")),
Bloc("exit",
Exit("mem")))
@ -289,7 +289,7 @@ func TestEquiv(t *testing.T) {
Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"),
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit")),
Bloc("exit",
Exit("mem"))),
@ -298,7 +298,7 @@ func TestEquiv(t *testing.T) {
Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"),
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit")),
Bloc("exit",
Exit("mem"))),
@ -310,7 +310,7 @@ func TestEquiv(t *testing.T) {
Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"),
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit")),
Bloc("exit",
Exit("mem"))),
@ -321,7 +321,7 @@ func TestEquiv(t *testing.T) {
Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"),
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit"))),
},
}
@ -338,26 +338,26 @@ func TestEquiv(t *testing.T) {
{
Fun(testConfig(t), "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Goto("exit")),
Bloc("exit",
Exit("mem"))),
Fun(testConfig(t), "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Exit("mem"))),
},
// value order changed
{
Fun(testConfig(t), "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("a", OpConst64, TypeInt64, 14, nil),
Exit("mem"))),
Fun(testConfig(t), "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil),
Exit("mem"))),
@ -366,12 +366,12 @@ func TestEquiv(t *testing.T) {
{
Fun(testConfig(t), "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 14, nil),
Exit("mem"))),
Fun(testConfig(t), "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 26, nil),
Exit("mem"))),
},
@ -379,12 +379,12 @@ func TestEquiv(t *testing.T) {
{
Fun(testConfig(t), "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 0, 14),
Exit("mem"))),
Fun(testConfig(t), "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 0, 26),
Exit("mem"))),
},
@ -392,14 +392,14 @@ func TestEquiv(t *testing.T) {
{
Fun(testConfig(t), "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 14, nil),
Valu("b", OpConst64, TypeInt64, 26, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "a", "b"),
Exit("mem"))),
Fun(testConfig(t), "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("a", OpConst64, TypeInt64, 0, nil),
Valu("b", OpConst64, TypeInt64, 14, nil),
Valu("sum", OpAdd64, TypeInt64, 0, nil, "b", "a"),

198
src/cmd/compile/internal/ssa/gen/AMD64Ops.go
View file

@ -152,45 +152,45 @@ func init() {
{name: "DIVSS", reg: fp21x15, asm: "DIVSS"}, // fp32 div
{name: "DIVSD", reg: fp21x15, asm: "DIVSD"}, // fp64 div
{name: "MOVSSload", reg: fpload, asm: "MOVSS"}, // fp32 load
{name: "MOVSDload", reg: fpload, asm: "MOVSD"}, // fp64 load
{name: "MOVSSconst", reg: fp01, asm: "MOVSS"}, // fp32 constant
{name: "MOVSDconst", reg: fp01, asm: "MOVSD"}, // fp64 constant
{name: "MOVSSloadidx4", reg: fploadidx, asm: "MOVSS"}, // fp32 load
{name: "MOVSDloadidx8", reg: fploadidx, asm: "MOVSD"}, // fp64 load
{name: "MOVSSload", reg: fpload, asm: "MOVSS", aux: "SymOff"}, // fp32 load
{name: "MOVSDload", reg: fpload, asm: "MOVSD", aux: "SymOff"}, // fp64 load
{name: "MOVSSconst", reg: fp01, asm: "MOVSS", aux: "Float", rematerializeable: true}, // fp32 constant
{name: "MOVSDconst", reg: fp01, asm: "MOVSD", aux: "Float", rematerializeable: true}, // fp64 constant
{name: "MOVSSloadidx4", reg: fploadidx, asm: "MOVSS", aux: "SymOff"}, // fp32 load
{name: "MOVSDloadidx8", reg: fploadidx, asm: "MOVSD", aux: "SymOff"}, // fp64 load
{name: "MOVSSstore", reg: fpstore, asm: "MOVSS"}, // fp32 store
{name: "MOVSDstore", reg: fpstore, asm: "MOVSD"}, // fp64 store
{name: "MOVSSstoreidx4", reg: fpstoreidx, asm: "MOVSS"}, // fp32 indexed by 4i store
{name: "MOVSDstoreidx8", reg: fpstoreidx, asm: "MOVSD"}, // fp64 indexed by 8i store
{name: "MOVSSstore", reg: fpstore, asm: "MOVSS", aux: "SymOff"}, // fp32 store
{name: "MOVSDstore", reg: fpstore, asm: "MOVSD", aux: "SymOff"}, // fp64 store
{name: "MOVSSstoreidx4", reg: fpstoreidx, asm: "MOVSS", aux: "SymOff"}, // fp32 indexed by 4i store
{name: "MOVSDstoreidx8", reg: fpstoreidx, asm: "MOVSD", aux: "SymOff"}, // fp64 indexed by 8i store
// binary ops
{name: "ADDQ", reg: gp21, asm: "ADDQ"}, // arg0 + arg1
{name: "ADDL", reg: gp21, asm: "ADDL"}, // arg0 + arg1
{name: "ADDW", reg: gp21, asm: "ADDW"}, // arg0 + arg1
{name: "ADDB", reg: gp21, asm: "ADDB"}, // arg0 + arg1
{name: "ADDQconst", reg: gp11, asm: "ADDQ", typ: "UInt64"}, // arg0 + auxint
{name: "ADDLconst", reg: gp11, asm: "ADDL"}, // arg0 + auxint
{name: "ADDWconst", reg: gp11, asm: "ADDW"}, // arg0 + auxint
{name: "ADDBconst", reg: gp11, asm: "ADDB"}, // arg0 + auxint
{name: "ADDQconst", reg: gp11, asm: "ADDQ", aux: "Int64", typ: "UInt64"}, // arg0 + auxint
{name: "ADDLconst", reg: gp11, asm: "ADDL", aux: "Int32"}, // arg0 + auxint
{name: "ADDWconst", reg: gp11, asm: "ADDW", aux: "Int16"}, // arg0 + auxint
{name: "ADDBconst", reg: gp11, asm: "ADDB", aux: "Int8"}, // arg0 + auxint
{name: "SUBQ", reg: gp21, asm: "SUBQ"}, // arg0 - arg1
{name: "SUBL", reg: gp21, asm: "SUBL"}, // arg0 - arg1
{name: "SUBW", reg: gp21, asm: "SUBW"}, // arg0 - arg1
{name: "SUBB", reg: gp21, asm: "SUBB"}, // arg0 - arg1
{name: "SUBQconst", reg: gp11, asm: "SUBQ"}, // arg0 - auxint
{name: "SUBLconst", reg: gp11, asm: "SUBL"}, // arg0 - auxint
{name: "SUBWconst", reg: gp11, asm: "SUBW"}, // arg0 - auxint
{name: "SUBBconst", reg: gp11, asm: "SUBB"}, // arg0 - auxint
{name: "SUBQconst", reg: gp11, asm: "SUBQ", aux: "Int64"}, // arg0 - auxint
{name: "SUBLconst", reg: gp11, asm: "SUBL", aux: "Int32"}, // arg0 - auxint
{name: "SUBWconst", reg: gp11, asm: "SUBW", aux: "Int16"}, // arg0 - auxint
{name: "SUBBconst", reg: gp11, asm: "SUBB", aux: "Int8"}, // arg0 - auxint
{name: "MULQ", reg: gp21, asm: "IMULQ"}, // arg0 * arg1
{name: "MULL", reg: gp21, asm: "IMULL"}, // arg0 * arg1
{name: "MULW", reg: gp21, asm: "IMULW"}, // arg0 * arg1
{name: "MULB", reg: gp21, asm: "IMULW"}, // arg0 * arg1
{name: "MULQconst", reg: gp11, asm: "IMULQ"}, // arg0 * auxint
{name: "MULLconst", reg: gp11, asm: "IMULL"}, // arg0 * auxint
{name: "MULWconst", reg: gp11, asm: "IMULW"}, // arg0 * auxint
{name: "MULBconst", reg: gp11, asm: "IMULW"}, // arg0 * auxint
{name: "MULQconst", reg: gp11, asm: "IMULQ", aux: "Int64"}, // arg0 * auxint
{name: "MULLconst", reg: gp11, asm: "IMULL", aux: "Int32"}, // arg0 * auxint
{name: "MULWconst", reg: gp11, asm: "IMULW", aux: "Int16"}, // arg0 * auxint
{name: "MULBconst", reg: gp11, asm: "IMULW", aux: "Int8"}, // arg0 * auxint
{name: "HMULL", reg: gp11hmul, asm: "IMULL"}, // (arg0 * arg1) >> width
{name: "HMULW", reg: gp11hmul, asm: "IMULW"}, // (arg0 * arg1) >> width
@ -217,37 +217,37 @@ func init() {
{name: "ANDL", reg: gp21, asm: "ANDL"}, // arg0 & arg1
{name: "ANDW", reg: gp21, asm: "ANDW"}, // arg0 & arg1
{name: "ANDB", reg: gp21, asm: "ANDB"}, // arg0 & arg1
{name: "ANDQconst", reg: gp11, asm: "ANDQ"}, // arg0 & auxint
{name: "ANDLconst", reg: gp11, asm: "ANDL"}, // arg0 & auxint
{name: "ANDWconst", reg: gp11, asm: "ANDW"}, // arg0 & auxint
{name: "ANDBconst", reg: gp11, asm: "ANDB"}, // arg0 & auxint
{name: "ANDQconst", reg: gp11, asm: "ANDQ", aux: "Int64"}, // arg0 & auxint
{name: "ANDLconst", reg: gp11, asm: "ANDL", aux: "Int32"}, // arg0 & auxint
{name: "ANDWconst", reg: gp11, asm: "ANDW", aux: "Int16"}, // arg0 & auxint
{name: "ANDBconst", reg: gp11, asm: "ANDB", aux: "Int8"}, // arg0 & auxint
{name: "ORQ", reg: gp21, asm: "ORQ"}, // arg0 | arg1
{name: "ORL", reg: gp21, asm: "ORL"}, // arg0 | arg1
{name: "ORW", reg: gp21, asm: "ORW"}, // arg0 | arg1
{name: "ORB", reg: gp21, asm: "ORB"}, // arg0 | arg1
{name: "ORQconst", reg: gp11, asm: "ORQ"}, // arg0 | auxint
{name: "ORLconst", reg: gp11, asm: "ORL"}, // arg0 | auxint
{name: "ORWconst", reg: gp11, asm: "ORW"}, // arg0 | auxint
{name: "ORBconst", reg: gp11, asm: "ORB"}, // arg0 | auxint
{name: "ORQconst", reg: gp11, asm: "ORQ", aux: "Int64"}, // arg0 | auxint
{name: "ORLconst", reg: gp11, asm: "ORL", aux: "Int32"}, // arg0 | auxint
{name: "ORWconst", reg: gp11, asm: "ORW", aux: "Int16"}, // arg0 | auxint
{name: "ORBconst", reg: gp11, asm: "ORB", aux: "Int8"}, // arg0 | auxint
{name: "XORQ", reg: gp21, asm: "XORQ"}, // arg0 ^ arg1
{name: "XORL", reg: gp21, asm: "XORL"}, // arg0 ^ arg1
{name: "XORW", reg: gp21, asm: "XORW"}, // arg0 ^ arg1
{name: "XORB", reg: gp21, asm: "XORB"}, // arg0 ^ arg1
{name: "XORQconst", reg: gp11, asm: "XORQ"}, // arg0 ^ auxint
{name: "XORLconst", reg: gp11, asm: "XORL"}, // arg0 ^ auxint
{name: "XORWconst", reg: gp11, asm: "XORW"}, // arg0 ^ auxint
{name: "XORBconst", reg: gp11, asm: "XORB"}, // arg0 ^ auxint
{name: "XORQconst", reg: gp11, asm: "XORQ", aux: "Int64"}, // arg0 ^ auxint
{name: "XORLconst", reg: gp11, asm: "XORL", aux: "Int32"}, // arg0 ^ auxint
{name: "XORWconst", reg: gp11, asm: "XORW", aux: "Int16"}, // arg0 ^ auxint
{name: "XORBconst", reg: gp11, asm: "XORB", aux: "Int8"}, // arg0 ^ auxint
{name: "CMPQ", reg: gp2flags, asm: "CMPQ", typ: "Flags"}, // arg0 compare to arg1
{name: "CMPL", reg: gp2flags, asm: "CMPL", typ: "Flags"}, // arg0 compare to arg1
{name: "CMPW", reg: gp2flags, asm: "CMPW", typ: "Flags"}, // arg0 compare to arg1
{name: "CMPB", reg: gp2flags, asm: "CMPB", typ: "Flags"}, // arg0 compare to arg1
{name: "CMPQconst", reg: gp1flags, asm: "CMPQ", typ: "Flags"}, // arg0 compare to auxint
{name: "CMPLconst", reg: gp1flags, asm: "CMPL", typ: "Flags"}, // arg0 compare to auxint
{name: "CMPWconst", reg: gp1flags, asm: "CMPW", typ: "Flags"}, // arg0 compare to auxint
{name: "CMPBconst", reg: gp1flags, asm: "CMPB", typ: "Flags"}, // arg0 compare to auxint
{name: "CMPQconst", reg: gp1flags, asm: "CMPQ", typ: "Flags", aux: "Int64"}, // arg0 compare to auxint
{name: "CMPLconst", reg: gp1flags, asm: "CMPL", typ: "Flags", aux: "Int32"}, // arg0 compare to auxint
{name: "CMPWconst", reg: gp1flags, asm: "CMPW", typ: "Flags", aux: "Int16"}, // arg0 compare to auxint
{name: "CMPBconst", reg: gp1flags, asm: "CMPB", typ: "Flags", aux: "Int8"}, // arg0 compare to auxint
{name: "UCOMISS", reg: fp2flags, asm: "UCOMISS", typ: "Flags"}, // arg0 compare to arg1, f32
{name: "UCOMISD", reg: fp2flags, asm: "UCOMISD", typ: "Flags"}, // arg0 compare to arg1, f64
@ -256,43 +256,43 @@ func init() {
{name: "TESTL", reg: gp2flags, asm: "TESTL", typ: "Flags"}, // (arg0 & arg1) compare to 0
{name: "TESTW", reg: gp2flags, asm: "TESTW", typ: "Flags"}, // (arg0 & arg1) compare to 0
{name: "TESTB", reg: gp2flags, asm: "TESTB", typ: "Flags"}, // (arg0 & arg1) compare to 0
{name: "TESTQconst", reg: gp1flags, asm: "TESTQ", typ: "Flags"}, // (arg0 & auxint) compare to 0
{name: "TESTLconst", reg: gp1flags, asm: "TESTL", typ: "Flags"}, // (arg0 & auxint) compare to 0
{name: "TESTWconst", reg: gp1flags, asm: "TESTW", typ: "Flags"}, // (arg0 & auxint) compare to 0
{name: "TESTBconst", reg: gp1flags, asm: "TESTB", typ: "Flags"}, // (arg0 & auxint) compare to 0
{name: "TESTQconst", reg: gp1flags, asm: "TESTQ", typ: "Flags", aux: "Int64"}, // (arg0 & auxint) compare to 0
{name: "TESTLconst", reg: gp1flags, asm: "TESTL", typ: "Flags", aux: "Int32"}, // (arg0 & auxint) compare to 0
{name: "TESTWconst", reg: gp1flags, asm: "TESTW", typ: "Flags", aux: "Int16"}, // (arg0 & auxint) compare to 0
{name: "TESTBconst", reg: gp1flags, asm: "TESTB", typ: "Flags", aux: "Int8"}, // (arg0 & auxint) compare to 0
{name: "SHLQ", reg: gp21shift, asm: "SHLQ"}, // arg0 << arg1, shift amount is mod 64
{name: "SHLL", reg: gp21shift, asm: "SHLL"}, // arg0 << arg1, shift amount is mod 32
{name: "SHLW", reg: gp21shift, asm: "SHLW"}, // arg0 << arg1, shift amount is mod 32
{name: "SHLB", reg: gp21shift, asm: "SHLB"}, // arg0 << arg1, shift amount is mod 32
{name: "SHLQconst", reg: gp11, asm: "SHLQ"}, // arg0 << auxint, shift amount 0-63
{name: "SHLLconst", reg: gp11, asm: "SHLL"}, // arg0 << auxint, shift amount 0-31
{name: "SHLWconst", reg: gp11, asm: "SHLW"}, // arg0 << auxint, shift amount 0-31
{name: "SHLBconst", reg: gp11, asm: "SHLB"}, // arg0 << auxint, shift amount 0-31
{name: "SHLQconst", reg: gp11, asm: "SHLQ", aux: "Int64"}, // arg0 << auxint, shift amount 0-63
{name: "SHLLconst", reg: gp11, asm: "SHLL", aux: "Int32"}, // arg0 << auxint, shift amount 0-31
{name: "SHLWconst", reg: gp11, asm: "SHLW", aux: "Int16"}, // arg0 << auxint, shift amount 0-31
{name: "SHLBconst", reg: gp11, asm: "SHLB", aux: "Int8"}, // arg0 << auxint, shift amount 0-31
// Note: x86 is weird, the 16 and 8 byte shifts still use all 5 bits of shift amount!
{name: "SHRQ", reg: gp21shift, asm: "SHRQ"}, // unsigned arg0 >> arg1, shift amount is mod 64
{name: "SHRL", reg: gp21shift, asm: "SHRL"}, // unsigned arg0 >> arg1, shift amount is mod 32
{name: "SHRW", reg: gp21shift, asm: "SHRW"}, // unsigned arg0 >> arg1, shift amount is mod 32
{name: "SHRB", reg: gp21shift, asm: "SHRB"}, // unsigned arg0 >> arg1, shift amount is mod 32
{name: "SHRQconst", reg: gp11, asm: "SHRQ"}, // unsigned arg0 >> auxint, shift amount 0-63
{name: "SHRLconst", reg: gp11, asm: "SHRL"}, // unsigned arg0 >> auxint, shift amount 0-31
{name: "SHRWconst", reg: gp11, asm: "SHRW"}, // unsigned arg0 >> auxint, shift amount 0-31
{name: "SHRBconst", reg: gp11, asm: "SHRB"}, // unsigned arg0 >> auxint, shift amount 0-31
{name: "SHRQconst", reg: gp11, asm: "SHRQ", aux: "Int64"}, // unsigned arg0 >> auxint, shift amount 0-63
{name: "SHRLconst", reg: gp11, asm: "SHRL", aux: "Int32"}, // unsigned arg0 >> auxint, shift amount 0-31
{name: "SHRWconst", reg: gp11, asm: "SHRW", aux: "Int16"}, // unsigned arg0 >> auxint, shift amount 0-31
{name: "SHRBconst", reg: gp11, asm: "SHRB", aux: "Int8"}, // unsigned arg0 >> auxint, shift amount 0-31
{name: "SARQ", reg: gp21shift, asm: "SARQ"}, // signed arg0 >> arg1, shift amount is mod 64
{name: "SARL", reg: gp21shift, asm: "SARL"}, // signed arg0 >> arg1, shift amount is mod 32
{name: "SARW", reg: gp21shift, asm: "SARW"}, // signed arg0 >> arg1, shift amount is mod 32
{name: "SARB", reg: gp21shift, asm: "SARB"}, // signed arg0 >> arg1, shift amount is mod 32
{name: "SARQconst", reg: gp11, asm: "SARQ"}, // signed arg0 >> auxint, shift amount 0-63
{name: "SARLconst", reg: gp11, asm: "SARL"}, // signed arg0 >> auxint, shift amount 0-31
{name: "SARWconst", reg: gp11, asm: "SARW"}, // signed arg0 >> auxint, shift amount 0-31
{name: "SARBconst", reg: gp11, asm: "SARB"}, // signed arg0 >> auxint, shift amount 0-31
{name: "SARQconst", reg: gp11, asm: "SARQ", aux: "Int64"}, // signed arg0 >> auxint, shift amount 0-63
{name: "SARLconst", reg: gp11, asm: "SARL", aux: "Int32"}, // signed arg0 >> auxint, shift amount 0-31
{name: "SARWconst", reg: gp11, asm: "SARW", aux: "Int16"}, // signed arg0 >> auxint, shift amount 0-31
{name: "SARBconst", reg: gp11, asm: "SARB", aux: "Int8"}, // signed arg0 >> auxint, shift amount 0-31
{name: "ROLQconst", reg: gp11, asm: "ROLQ"}, // arg0 rotate left auxint, rotate amount 0-63
{name: "ROLLconst", reg: gp11, asm: "ROLL"}, // arg0 rotate left auxint, rotate amount 0-31
{name: "ROLWconst", reg: gp11, asm: "ROLW"}, // arg0 rotate left auxint, rotate amount 0-15
{name: "ROLBconst", reg: gp11, asm: "ROLB"}, // arg0 rotate left auxint, rotate amount 0-7
{name: "ROLQconst", reg: gp11, asm: "ROLQ", aux: "Int64"}, // arg0 rotate left auxint, rotate amount 0-63
{name: "ROLLconst", reg: gp11, asm: "ROLL", aux: "Int32"}, // arg0 rotate left auxint, rotate amount 0-31
{name: "ROLWconst", reg: gp11, asm: "ROLW", aux: "Int16"}, // arg0 rotate left auxint, rotate amount 0-15
{name: "ROLBconst", reg: gp11, asm: "ROLB", aux: "Int8"}, // arg0 rotate left auxint, rotate amount 0-7
// unary ops
{name: "NEGQ", reg: gp11, asm: "NEGQ"}, // -arg0
@ -339,10 +339,10 @@ func init() {
{name: "MOVLQSX", reg: gp11nf, asm: "MOVLQSX"}, // sign extend arg0 from int32 to int64
{name: "MOVLQZX", reg: gp11nf, asm: "MOVLQZX"}, // zero extend arg0 from int32 to int64
{name: "MOVBconst", reg: gp01, asm: "MOVB", typ: "UInt8"}, // 8 low bits of auxint
{name: "MOVWconst", reg: gp01, asm: "MOVW", typ: "UInt16"}, // 16 low bits of auxint
{name: "MOVLconst", reg: gp01, asm: "MOVL", typ: "UInt32"}, // 32 low bits of auxint
{name: "MOVQconst", reg: gp01, asm: "MOVQ", typ: "UInt64"}, // auxint
{name: "MOVBconst", reg: gp01, asm: "MOVB", typ: "UInt8", aux: "Int8", rematerializeable: true}, // 8 low bits of auxint
{name: "MOVWconst", reg: gp01, asm: "MOVW", typ: "UInt16", aux: "Int16", rematerializeable: true}, // 16 low bits of auxint
{name: "MOVLconst", reg: gp01, asm: "MOVL", typ: "UInt32", aux: "Int32", rematerializeable: true}, // 32 low bits of auxint
{name: "MOVQconst", reg: gp01, asm: "MOVQ", typ: "UInt64", aux: "Int64", rematerializeable: true}, // auxint
{name: "CVTTSD2SL", reg: fpgp, asm: "CVTTSD2SL"}, // convert float64 to int32
{name: "CVTTSD2SQ", reg: fpgp, asm: "CVTTSD2SQ"}, // convert float64 to int64
@ -357,44 +357,44 @@ func init() {
{name: "PXOR", reg: fp21, asm: "PXOR"}, // exclusive or, applied to X regs for float negation.
{name: "LEAQ", reg: gp11sb}, // arg0 + auxint + offset encoded in aux
{name: "LEAQ1", reg: gp21sb}, // arg0 + arg1 + auxint
{name: "LEAQ2", reg: gp21sb}, // arg0 + 2*arg1 + auxint
{name: "LEAQ4", reg: gp21sb}, // arg0 + 4*arg1 + auxint
{name: "LEAQ8", reg: gp21sb}, // arg0 + 8*arg1 + auxint
{name: "LEAQ", reg: gp11sb, aux: "SymOff", rematerializeable: true}, // arg0 + auxint + offset encoded in aux
{name: "LEAQ1", reg: gp21sb, aux: "SymOff"}, // arg0 + arg1 + auxint + aux
{name: "LEAQ2", reg: gp21sb, aux: "SymOff"}, // arg0 + 2*arg1 + auxint + aux
{name: "LEAQ4", reg: gp21sb, aux: "SymOff"}, // arg0 + 4*arg1 + auxint + aux
{name: "LEAQ8", reg: gp21sb, aux: "SymOff"}, // arg0 + 8*arg1 + auxint + aux
// auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address
{name: "MOVBload", reg: gpload, asm: "MOVB", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem
{name: "MOVBQSXload", reg: gpload, asm: "MOVBQSX"}, // ditto, extend to int64
{name: "MOVBQZXload", reg: gpload, asm: "MOVBQZX"}, // ditto, extend to uint64
{name: "MOVWload", reg: gpload, asm: "MOVW", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVWQSXload", reg: gpload, asm: "MOVWQSX"}, // ditto, extend to int64
{name: "MOVWQZXload", reg: gpload, asm: "MOVWQZX"}, // ditto, extend to uint64
{name: "MOVLload", reg: gpload, asm: "MOVL", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVLQSXload", reg: gpload, asm: "MOVLQSX"}, // ditto, extend to int64
{name: "MOVLQZXload", reg: gpload, asm: "MOVLQZX"}, // ditto, extend to uint64
{name: "MOVQload", reg: gpload, asm: "MOVQ", typ: "UInt64"}, // load 8 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVQloadidx8", reg: gploadidx, asm: "MOVQ"}, // load 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem
{name: "MOVBstore", reg: gpstore, asm: "MOVB", typ: "Mem"}, // store byte in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVWstore", reg: gpstore, asm: "MOVW", typ: "Mem"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVLstore", reg: gpstore, asm: "MOVL", typ: "Mem"}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVQstore", reg: gpstore, asm: "MOVQ", typ: "Mem"}, // store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVBload", reg: gpload, asm: "MOVB", aux: "SymOff", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem
{name: "MOVBQSXload", reg: gpload, asm: "MOVBQSX", aux: "SymOff"}, // ditto, extend to int64
{name: "MOVBQZXload", reg: gpload, asm: "MOVBQZX", aux: "SymOff"}, // ditto, extend to uint64
{name: "MOVWload", reg: gpload, asm: "MOVW", aux: "SymOff", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVWQSXload", reg: gpload, asm: "MOVWQSX", aux: "SymOff"}, // ditto, extend to int64
{name: "MOVWQZXload", reg: gpload, asm: "MOVWQZX", aux: "SymOff"}, // ditto, extend to uint64
{name: "MOVLload", reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVLQSXload", reg: gpload, asm: "MOVLQSX", aux: "SymOff"}, // ditto, extend to int64
{name: "MOVLQZXload", reg: gpload, asm: "MOVLQZX", aux: "SymOff"}, // ditto, extend to uint64
{name: "MOVQload", reg: gpload, asm: "MOVQ", aux: "SymOff", typ: "UInt64"}, // load 8 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVQloadidx8", reg: gploadidx, asm: "MOVQ", aux: "SymOff"}, // load 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem
{name: "MOVBstore", reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem"}, // store byte in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVWstore", reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVLstore", reg: gpstore, asm: "MOVL", aux: "SymOff", typ: "Mem"}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVQstore", reg: gpstore, asm: "MOVQ", aux: "SymOff", typ: "Mem"}, // store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVBstoreidx1", reg: gpstoreidx, asm: "MOVB"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem
{name: "MOVWstoreidx2", reg: gpstoreidx, asm: "MOVW"}, // store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem
{name: "MOVLstoreidx4", reg: gpstoreidx, asm: "MOVL"}, // store 4 bytes in arg2 to arg0+4*arg1+auxint+aux. arg3=mem
{name: "MOVQstoreidx8", reg: gpstoreidx, asm: "MOVQ"}, // store 8 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem
{name: "MOVBstoreidx1", reg: gpstoreidx, asm: "MOVB", aux: "SymOff"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem
{name: "MOVWstoreidx2", reg: gpstoreidx, asm: "MOVW", aux: "SymOff"}, // store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem
{name: "MOVLstoreidx4", reg: gpstoreidx, asm: "MOVL", aux: "SymOff"}, // store 4 bytes in arg2 to arg0+4*arg1+auxint+aux. arg3=mem
{name: "MOVQstoreidx8", reg: gpstoreidx, asm: "MOVQ", aux: "SymOff"}, // store 8 bytes in arg2 to arg0+8*arg1+auxint+aux. arg3=mem
{name: "MOVOload", reg: fpload, asm: "MOVUPS", typ: "Int128"}, // load 16 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVOstore", reg: fpstore, asm: "MOVUPS", typ: "Mem"}, // store 16 bytes in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVOload", reg: fpload, asm: "MOVUPS", aux: "SymOff", typ: "Int128"}, // load 16 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVOstore", reg: fpstore, asm: "MOVUPS", aux: "SymOff", typ: "Mem"}, // store 16 bytes in arg1 to arg0+auxint+aux. arg2=mem
// For storeconst ops, the AuxInt field encodes both
// the value to store and an address offset of the store.
// Cast AuxInt to a ValAndOff to extract Val and Off fields.
{name: "MOVBstoreconst", reg: gpstoreconst, asm: "MOVB", typ: "Mem"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux. arg1=mem
{name: "MOVWstoreconst", reg: gpstoreconst, asm: "MOVW", typ: "Mem"}, // store low 2 bytes of ...
{name: "MOVLstoreconst", reg: gpstoreconst, asm: "MOVL", typ: "Mem"}, // store low 4 bytes of ...
{name: "MOVQstoreconst", reg: gpstoreconst, asm: "MOVQ", typ: "Mem"}, // store 8 bytes of ...
{name: "MOVBstoreconst", reg: gpstoreconst, asm: "MOVB", aux: "SymValAndOff", typ: "Mem"}, // store low byte of ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux. arg1=mem
{name: "MOVWstoreconst", reg: gpstoreconst, asm: "MOVW", aux: "SymValAndOff", typ: "Mem"}, // store low 2 bytes of ...
{name: "MOVLstoreconst", reg: gpstoreconst, asm: "MOVL", aux: "SymValAndOff", typ: "Mem"}, // store low 4 bytes of ...
{name: "MOVQstoreconst", reg: gpstoreconst, asm: "MOVQ", aux: "SymValAndOff", typ: "Mem"}, // store 8 bytes of ...
// arg0 = (duff-adjusted) pointer to start of memory to zero
// arg1 = value to store (will always be zero)
@ -403,12 +403,13 @@ func init() {
// returns mem
{
name: "DUFFZERO",
aux: "Int64",
reg: regInfo{
inputs: []regMask{buildReg("DI"), buildReg("X0")},
clobbers: buildReg("DI FLAGS"),
},
},
{name: "MOVOconst", reg: regInfo{nil, 0, []regMask{fp}}, typ: "Int128"},
{name: "MOVOconst", reg: regInfo{nil, 0, []regMask{fp}}, typ: "Int128", rematerializeable: true},
// arg0 = address of memory to zero
// arg1 = # of 8-byte words to zero
@ -423,11 +424,11 @@ func init() {
},
},
{name: "CALLstatic", reg: regInfo{clobbers: callerSave}}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
{name: "CALLclosure", reg: regInfo{[]regMask{gpsp, buildReg("DX"), 0}, callerSave, nil}}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
{name: "CALLdefer", reg: regInfo{clobbers: callerSave}}, // call deferproc. arg0=mem, auxint=argsize, returns mem
{name: "CALLgo", reg: regInfo{clobbers: callerSave}}, // call newproc. arg0=mem, auxint=argsize, returns mem
{name: "CALLinter", reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
{name: "CALLstatic", reg: regInfo{clobbers: callerSave}, aux: "SymOff"}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
{name: "CALLclosure", reg: regInfo{[]regMask{gpsp, buildReg("DX"), 0}, callerSave, nil}, aux: "Int64"}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
{name: "CALLdefer", reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call deferproc. arg0=mem, auxint=argsize, returns mem
{name: "CALLgo", reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call newproc. arg0=mem, auxint=argsize, returns mem
{name: "CALLinter", reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64"}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
// arg0 = destination pointer
// arg1 = source pointer
@ -436,6 +437,7 @@ func init() {
// returns memory
{
name: "DUFFCOPY",
aux: "Int64",
reg: regInfo{
inputs: []regMask{buildReg("DI"), buildReg("SI")},
clobbers: buildReg("DI SI X0 FLAGS"), // uses X0 as a temporary

56
src/cmd/compile/internal/ssa/gen/genericOps.go
View file

@ -148,10 +148,10 @@ var genericOps = []opData{
// for rotates is hashing and crypto code with constant
// distance, rotate instructions are only substituted
// when arg1 is a constant between 1 and A-1, inclusive.
{name: "Lrot8"},
{name: "Lrot16"},
{name: "Lrot32"},
{name: "Lrot64"},
{name: "Lrot8", aux: "Int64"},
{name: "Lrot16", aux: "Int64"},
{name: "Lrot32", aux: "Int64"},
{name: "Lrot64", aux: "Int64"},
// 2-input comparisons
{name: "Eq8"}, // arg0 == arg1
@ -247,46 +247,46 @@ var genericOps = []opData{
// constants. Constant values are stored in the aux or
// auxint fields.
{name: "ConstBool"}, // auxint is 0 for false and 1 for true
{name: "ConstString"}, // value is aux.(string)
{name: "ConstBool", aux: "Bool"}, // auxint is 0 for false and 1 for true
{name: "ConstString", aux: "String"}, // value is aux.(string)
{name: "ConstNil", typ: "BytePtr"}, // nil pointer
{name: "Const8"}, // value is low 8 bits of auxint
{name: "Const16"}, // value is low 16 bits of auxint
{name: "Const32"}, // value is low 32 bits of auxint
{name: "Const64"}, // value is auxint
{name: "Const32F"}, // value is math.Float64frombits(uint64(auxint))
{name: "Const64F"}, // value is math.Float64frombits(uint64(auxint))
{name: "Const8", aux: "Int8"}, // value is low 8 bits of auxint
{name: "Const16", aux: "Int16"}, // value is low 16 bits of auxint
{name: "Const32", aux: "Int32"}, // value is low 32 bits of auxint
{name: "Const64", aux: "Int64"}, // value is auxint
{name: "Const32F", aux: "Float"}, // value is math.Float64frombits(uint64(auxint))
{name: "Const64F", aux: "Float"}, // value is math.Float64frombits(uint64(auxint))
{name: "ConstInterface"}, // nil interface
{name: "ConstSlice"}, // nil slice
// Constant-like things
{name: "InitMem"}, // memory input to the function.
{name: "Arg"}, // argument to the function. aux=GCNode of arg, off = offset in that arg.
{name: "Arg", aux: "SymOff"}, // argument to the function. aux=GCNode of arg, off = offset in that arg.
// The address of a variable. arg0 is the base pointer (SB or SP, depending
// on whether it is a global or stack variable). The Aux field identifies the
// variable. It will be either an *ExternSymbol (with arg0=SB), *ArgSymbol (arg0=SP),
// or *AutoSymbol (arg0=SP).
{name: "Addr"}, // Address of a variable. Arg0=SP or SB. Aux identifies the variable.
{name: "Addr", aux: "Sym"}, // Address of a variable. Arg0=SP or SB. Aux identifies the variable.
{name: "SP"}, // stack pointer
{name: "SB", typ: "Uintptr"}, // static base pointer (a.k.a. globals pointer)
{name: "Func"}, // entry address of a function
{name: "Func", aux: "Sym"}, // entry address of a function
// Memory operations
{name: "Load"}, // Load from arg0. arg1=memory
{name: "Store", typ: "Mem"}, // Store arg1 to arg0. arg2=memory, auxint=size. Returns memory.
{name: "Move"}, // arg0=destptr, arg1=srcptr, arg2=mem, auxint=size. Returns memory.
{name: "Zero"}, // arg0=destptr, arg1=mem, auxint=size. Returns memory.
{name: "Store", typ: "Mem", aux: "Int64"}, // Store arg1 to arg0. arg2=memory, auxint=size. Returns memory.
{name: "Move", aux: "Int64"}, // arg0=destptr, arg1=srcptr, arg2=mem, auxint=size. Returns memory.
{name: "Zero", aux: "Int64"}, // arg0=destptr, arg1=mem, auxint=size. Returns memory.
// Function calls. Arguments to the call have already been written to the stack.
// Return values appear on the stack. The method receiver, if any, is treated
// as a phantom first argument.
{name: "ClosureCall"}, // arg0=code pointer, arg1=context ptr, arg2=memory. auxint=arg size. Returns memory.
{name: "StaticCall"}, // call function aux.(*gc.Sym), arg0=memory. auxint=arg size. Returns memory.
{name: "DeferCall"}, // defer call. arg0=memory, auxint=arg size. Returns memory.
{name: "GoCall"}, // go call. arg0=memory, auxint=arg size. Returns memory.
{name: "InterCall"}, // interface call. arg0=code pointer, arg1=memory, auxint=arg size. Returns memory.
{name: "ClosureCall", aux: "Int64"}, // arg0=code pointer, arg1=context ptr, arg2=memory. auxint=arg size. Returns memory.
{name: "StaticCall", aux: "SymOff"}, // call function aux.(*gc.Sym), arg0=memory. auxint=arg size. Returns memory.
{name: "DeferCall", aux: "Int64"}, // defer call. arg0=memory, auxint=arg size. Returns memory.
{name: "GoCall", aux: "Int64"}, // go call. arg0=memory, auxint=arg size. Returns memory.
{name: "InterCall", aux: "Int64"}, // interface call. arg0=code pointer, arg1=memory, auxint=arg size. Returns memory.
// Conversions: signed extensions, zero (unsigned) extensions, truncations
{name: "SignExt8to16", typ: "Int16"},
@ -332,7 +332,7 @@ var genericOps = []opData{
// Indexing operations
{name: "ArrayIndex"}, // arg0=array, arg1=index. Returns a[i]
{name: "PtrIndex"}, // arg0=ptr, arg1=index. Computes ptr+sizeof(*v.type)*index, where index is extended to ptrwidth type
{name: "OffPtr"}, // arg0 + auxint (arg0 and result are pointers)
{name: "OffPtr", aux: "Int64"}, // arg0 + auxint (arg0 and result are pointers)
// Slices
{name: "SliceMake"}, // arg0=ptr, arg1=len, arg2=cap
@ -361,7 +361,7 @@ var genericOps = []opData{
{name: "StructMake2"}, // arg0,arg1=field0,field1. Returns struct.
{name: "StructMake3"}, // arg0..2=field0..2. Returns struct.
{name: "StructMake4"}, // arg0..3=field0..3. Returns struct.
{name: "StructSelect"}, // arg0=struct, auxint=field index. Returns the auxint'th field.
{name: "StructSelect", aux: "Int64"}, // arg0=struct, auxint=field index. Returns the auxint'th field.
// Spill&restore ops for the register allocator. These are
// semantically identical to OpCopy; they do not take/return
@ -376,9 +376,9 @@ var genericOps = []opData{
// Unknown value. Used for Values whose values don't matter because they are dead code.
{name: "Unknown"},
{name: "VarDef", typ: "Mem"}, // aux is a *gc.Node of a variable that is about to be initialized. arg0=mem, returns mem
{name: "VarKill"}, // aux is a *gc.Node of a variable that is known to be dead. arg0=mem, returns mem
{name: "VarLive"}, // aux is a *gc.Node of a variable that must be kept live. arg0=mem, returns mem
{name: "VarDef", aux: "Sym", typ: "Mem"}, // aux is a *gc.Node of a variable that is about to be initialized. arg0=mem, returns mem
{name: "VarKill", aux: "Sym"}, // aux is a *gc.Node of a variable that is known to be dead. arg0=mem, returns mem
{name: "VarLive", aux: "Sym"}, // aux is a *gc.Node of a variable that must be kept live. arg0=mem, returns mem
}
// kind control successors implicit exit

13
src/cmd/compile/internal/ssa/gen/main.go
View file

@ -30,6 +30,8 @@ type opData struct {
reg regInfo
asm string
typ string // default result type
aux string
rematerializeable bool
}
type blockData struct {
@ -117,6 +119,17 @@ func genOp() {
for _, v := range a.ops {
fmt.Fprintln(w, "{")
fmt.Fprintf(w, "name:\"%s\",\n", v.name)
// flags
if v.aux != "" {
fmt.Fprintf(w, "auxType: aux%s,\n", v.aux)
}
if v.rematerializeable {
if v.reg.clobbers != 0 {
log.Fatalf("%s is rematerializeable and clobbers registers", v.name)
}
fmt.Fprintln(w, "rematerializeable: true,")
}
if a.name == "generic" {
fmt.Fprintln(w, "generic:true,")
fmt.Fprintln(w, "},") // close op

20
src/cmd/compile/internal/ssa/nilcheck_test.go
View file

@ -21,7 +21,7 @@ func benchmarkNilCheckDeep(b *testing.B, depth int) {
var blocs []bloc
blocs = append(blocs,
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto(blockn(0)),
),
@ -67,7 +67,7 @@ func TestNilcheckSimple(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")),
Bloc("checkPtr",
@ -104,7 +104,7 @@ func TestNilcheckDomOrder(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")),
Bloc("checkPtr",
@ -140,7 +140,7 @@ func TestNilcheckAddr(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")),
Bloc("checkPtr",
@ -173,7 +173,7 @@ func TestNilcheckAddPtr(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")),
Bloc("checkPtr",
@ -207,7 +207,7 @@ func TestNilcheckPhi(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Valu("sp", OpSP, TypeInvalid, 0, nil),
Valu("baddr", OpAddr, TypeBool, 0, "b", "sp"),
@ -251,7 +251,7 @@ func TestNilcheckKeepRemove(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")),
Bloc("checkPtr",
@ -299,7 +299,7 @@ func TestNilcheckInFalseBranch(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")),
Bloc("checkPtr",
@ -350,7 +350,7 @@ func TestNilcheckUser(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")),
Bloc("checkPtr",
@ -389,7 +389,7 @@ func TestNilcheckBug(t *testing.T) {
c := NewConfig("amd64", DummyFrontend{t}, nil, true)
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto("checkPtr")),
Bloc("checkPtr",

18
src/cmd/compile/internal/ssa/op.go
View file

@ -18,7 +18,9 @@ type opInfo struct {
name string
asm int
reg regInfo
auxType auxType
generic bool // this is a generic (arch-independent) opcode
rematerializeable bool // this op is rematerializeable
}
type inputInfo struct {
@ -32,6 +34,22 @@ type regInfo struct {
outputs []regMask // NOTE: values can only have 1 output for now.
}
type auxType int8
const (
auxNone auxType = iota
auxBool // auxInt is 0/1 for false/true
auxInt8 // auxInt is an 8-bit integer
auxInt16 // auxInt is a 16-bit integer
auxInt32 // auxInt is a 32-bit integer
auxInt64 // auxInt is a 64-bit integer
auxFloat // auxInt is a float64 (encoded with math.Float64bits)
auxString // auxInt is a string
auxSym // aux is a symbol
auxSymOff // aux is a symbol, auxInt is an offset
auxSymValAndOff // aux is a symbol, auxInt is a ValAndOff
)
// A ValAndOff is used by the several opcodes. It holds
// both a value and a pointer offset.
// A ValAndOff is intended to be encoded into an AuxInt field.

135
src/cmd/compile/internal/ssa/opGen.go
View file

@ -681,6 +681,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVSSload",
auxType: auxSymOff,
asm: x86.AMOVSS,
reg: regInfo{
inputs: []inputInfo{
@ -693,6 +694,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVSDload",
auxType: auxSymOff,
asm: x86.AMOVSD,
reg: regInfo{
inputs: []inputInfo{
@ -705,6 +707,8 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVSSconst",
auxType: auxFloat,
rematerializeable: true,
asm: x86.AMOVSS,
reg: regInfo{
outputs: []regMask{
@ -714,6 +718,8 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVSDconst",
auxType: auxFloat,
rematerializeable: true,
asm: x86.AMOVSD,
reg: regInfo{
outputs: []regMask{
@ -723,6 +729,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVSSloadidx4",
auxType: auxSymOff,
asm: x86.AMOVSS,
reg: regInfo{
inputs: []inputInfo{
@ -736,6 +743,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVSDloadidx8",
auxType: auxSymOff,
asm: x86.AMOVSD,
reg: regInfo{
inputs: []inputInfo{
@ -749,6 +757,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVSSstore",
auxType: auxSymOff,
asm: x86.AMOVSS,
reg: regInfo{
inputs: []inputInfo{
@ -759,6 +768,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVSDstore",
auxType: auxSymOff,
asm: x86.AMOVSD,
reg: regInfo{
inputs: []inputInfo{
@ -769,6 +779,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVSSstoreidx4",
auxType: auxSymOff,
asm: x86.AMOVSS,
reg: regInfo{
inputs: []inputInfo{
@ -780,6 +791,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVSDstoreidx8",
auxType: auxSymOff,
asm: x86.AMOVSD,
reg: regInfo{
inputs: []inputInfo{
@ -847,6 +859,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ADDQconst",
auxType: auxInt64,
asm: x86.AADDQ,
reg: regInfo{
inputs: []inputInfo{
@ -860,6 +873,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ADDLconst",
auxType: auxInt32,
asm: x86.AADDL,
reg: regInfo{
inputs: []inputInfo{
@ -873,6 +887,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ADDWconst",
auxType: auxInt16,
asm: x86.AADDW,
reg: regInfo{
inputs: []inputInfo{
@ -886,6 +901,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ADDBconst",
auxType: auxInt8,
asm: x86.AADDB,
reg: regInfo{
inputs: []inputInfo{
@ -955,6 +971,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SUBQconst",
auxType: auxInt64,
asm: x86.ASUBQ,
reg: regInfo{
inputs: []inputInfo{
@ -968,6 +985,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SUBLconst",
auxType: auxInt32,
asm: x86.ASUBL,
reg: regInfo{
inputs: []inputInfo{
@ -981,6 +999,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SUBWconst",
auxType: auxInt16,
asm: x86.ASUBW,
reg: regInfo{
inputs: []inputInfo{
@ -994,6 +1013,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SUBBconst",
auxType: auxInt8,
asm: x86.ASUBB,
reg: regInfo{
inputs: []inputInfo{
@ -1063,6 +1083,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MULQconst",
auxType: auxInt64,
asm: x86.AIMULQ,
reg: regInfo{
inputs: []inputInfo{
@ -1076,6 +1097,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MULLconst",
auxType: auxInt32,
asm: x86.AIMULL,
reg: regInfo{
inputs: []inputInfo{
@ -1089,6 +1111,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MULWconst",
auxType: auxInt16,
asm: x86.AIMULW,
reg: regInfo{
inputs: []inputInfo{
@ -1102,6 +1125,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MULBconst",
auxType: auxInt8,
asm: x86.AIMULW,
reg: regInfo{
inputs: []inputInfo{
@ -1423,6 +1447,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ANDQconst",
auxType: auxInt64,
asm: x86.AANDQ,
reg: regInfo{
inputs: []inputInfo{
@ -1436,6 +1461,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ANDLconst",
auxType: auxInt32,
asm: x86.AANDL,
reg: regInfo{
inputs: []inputInfo{
@ -1449,6 +1475,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ANDWconst",
auxType: auxInt16,
asm: x86.AANDW,
reg: regInfo{
inputs: []inputInfo{
@ -1462,6 +1489,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ANDBconst",
auxType: auxInt8,
asm: x86.AANDB,
reg: regInfo{
inputs: []inputInfo{
@ -1531,6 +1559,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ORQconst",
auxType: auxInt64,
asm: x86.AORQ,
reg: regInfo{
inputs: []inputInfo{
@ -1544,6 +1573,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ORLconst",
auxType: auxInt32,
asm: x86.AORL,
reg: regInfo{
inputs: []inputInfo{
@ -1557,6 +1587,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ORWconst",
auxType: auxInt16,
asm: x86.AORW,
reg: regInfo{
inputs: []inputInfo{
@ -1570,6 +1601,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ORBconst",
auxType: auxInt8,
asm: x86.AORB,
reg: regInfo{
inputs: []inputInfo{
@ -1639,6 +1671,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "XORQconst",
auxType: auxInt64,
asm: x86.AXORQ,
reg: regInfo{
inputs: []inputInfo{
@ -1652,6 +1685,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "XORLconst",
auxType: auxInt32,
asm: x86.AXORL,
reg: regInfo{
inputs: []inputInfo{
@ -1665,6 +1699,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "XORWconst",
auxType: auxInt16,
asm: x86.AXORW,
reg: regInfo{
inputs: []inputInfo{
@ -1678,6 +1713,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "XORBconst",
auxType: auxInt8,
asm: x86.AXORB,
reg: regInfo{
inputs: []inputInfo{
@ -1743,6 +1779,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "CMPQconst",
auxType: auxInt64,
asm: x86.ACMPQ,
reg: regInfo{
inputs: []inputInfo{
@ -1755,6 +1792,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "CMPLconst",
auxType: auxInt32,
asm: x86.ACMPL,
reg: regInfo{
inputs: []inputInfo{
@ -1767,6 +1805,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "CMPWconst",
auxType: auxInt16,
asm: x86.ACMPW,
reg: regInfo{
inputs: []inputInfo{
@ -1779,6 +1818,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "CMPBconst",
auxType: auxInt8,
asm: x86.ACMPB,
reg: regInfo{
inputs: []inputInfo{
@ -1869,6 +1909,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "TESTQconst",
auxType: auxInt64,
asm: x86.ATESTQ,
reg: regInfo{
inputs: []inputInfo{
@ -1881,6 +1922,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "TESTLconst",
auxType: auxInt32,
asm: x86.ATESTL,
reg: regInfo{
inputs: []inputInfo{
@ -1893,6 +1935,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "TESTWconst",
auxType: auxInt16,
asm: x86.ATESTW,
reg: regInfo{
inputs: []inputInfo{
@ -1905,6 +1948,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "TESTBconst",
auxType: auxInt8,
asm: x86.ATESTB,
reg: regInfo{
inputs: []inputInfo{
@ -1973,6 +2017,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SHLQconst",
auxType: auxInt64,
asm: x86.ASHLQ,
reg: regInfo{
inputs: []inputInfo{
@ -1986,6 +2031,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SHLLconst",
auxType: auxInt32,
asm: x86.ASHLL,
reg: regInfo{
inputs: []inputInfo{
@ -1999,6 +2045,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SHLWconst",
auxType: auxInt16,
asm: x86.ASHLW,
reg: regInfo{
inputs: []inputInfo{
@ -2012,6 +2059,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SHLBconst",
auxType: auxInt8,
asm: x86.ASHLB,
reg: regInfo{
inputs: []inputInfo{
@ -2081,6 +2129,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SHRQconst",
auxType: auxInt64,
asm: x86.ASHRQ,
reg: regInfo{
inputs: []inputInfo{
@ -2094,6 +2143,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SHRLconst",
auxType: auxInt32,
asm: x86.ASHRL,
reg: regInfo{
inputs: []inputInfo{
@ -2107,6 +2157,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SHRWconst",
auxType: auxInt16,
asm: x86.ASHRW,
reg: regInfo{
inputs: []inputInfo{
@ -2120,6 +2171,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SHRBconst",
auxType: auxInt8,
asm: x86.ASHRB,
reg: regInfo{
inputs: []inputInfo{
@ -2189,6 +2241,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SARQconst",
auxType: auxInt64,
asm: x86.ASARQ,
reg: regInfo{
inputs: []inputInfo{
@ -2202,6 +2255,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SARLconst",
auxType: auxInt32,
asm: x86.ASARL,
reg: regInfo{
inputs: []inputInfo{
@ -2215,6 +2269,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SARWconst",
auxType: auxInt16,
asm: x86.ASARW,
reg: regInfo{
inputs: []inputInfo{
@ -2228,6 +2283,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "SARBconst",
auxType: auxInt8,
asm: x86.ASARB,
reg: regInfo{
inputs: []inputInfo{
@ -2241,6 +2297,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ROLQconst",
auxType: auxInt64,
asm: x86.AROLQ,
reg: regInfo{
inputs: []inputInfo{
@ -2254,6 +2311,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ROLLconst",
auxType: auxInt32,
asm: x86.AROLL,
reg: regInfo{
inputs: []inputInfo{
@ -2267,6 +2325,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ROLWconst",
auxType: auxInt16,
asm: x86.AROLW,
reg: regInfo{
inputs: []inputInfo{
@ -2280,6 +2339,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "ROLBconst",
auxType: auxInt8,
asm: x86.AROLB,
reg: regInfo{
inputs: []inputInfo{
@ -2699,6 +2759,8 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVBconst",
auxType: auxInt8,
rematerializeable: true,
asm: x86.AMOVB,
reg: regInfo{
outputs: []regMask{
@ -2708,6 +2770,8 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVWconst",
auxType: auxInt16,
rematerializeable: true,
asm: x86.AMOVW,
reg: regInfo{
outputs: []regMask{
@ -2717,6 +2781,8 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVLconst",
auxType: auxInt32,
rematerializeable: true,
asm: x86.AMOVL,
reg: regInfo{
outputs: []regMask{
@ -2726,6 +2792,8 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVQconst",
auxType: auxInt64,
rematerializeable: true,
asm: x86.AMOVQ,
reg: regInfo{
outputs: []regMask{
@ -2868,6 +2936,8 @@ var opcodeTable = [...]opInfo{
},
{
name: "LEAQ",
auxType: auxSymOff,
rematerializeable: true,
reg: regInfo{
inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
@ -2879,6 +2949,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "LEAQ1",
auxType: auxSymOff,
reg: regInfo{
inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -2891,6 +2962,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "LEAQ2",
auxType: auxSymOff,
reg: regInfo{
inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -2903,6 +2975,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "LEAQ4",
auxType: auxSymOff,
reg: regInfo{
inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -2915,6 +2988,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "LEAQ8",
auxType: auxSymOff,
reg: regInfo{
inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -2927,6 +3001,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVBload",
auxType: auxSymOff,
asm: x86.AMOVB,
reg: regInfo{
inputs: []inputInfo{
@ -2939,6 +3014,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVBQSXload",
auxType: auxSymOff,
asm: x86.AMOVBQSX,
reg: regInfo{
inputs: []inputInfo{
@ -2951,6 +3027,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVBQZXload",
auxType: auxSymOff,
asm: x86.AMOVBQZX,
reg: regInfo{
inputs: []inputInfo{
@ -2963,6 +3040,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVWload",
auxType: auxSymOff,
asm: x86.AMOVW,
reg: regInfo{
inputs: []inputInfo{
@ -2975,6 +3053,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVWQSXload",
auxType: auxSymOff,
asm: x86.AMOVWQSX,
reg: regInfo{
inputs: []inputInfo{
@ -2987,6 +3066,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVWQZXload",
auxType: auxSymOff,
asm: x86.AMOVWQZX,
reg: regInfo{
inputs: []inputInfo{
@ -2999,6 +3079,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVLload",
auxType: auxSymOff,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
@ -3011,6 +3092,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVLQSXload",
auxType: auxSymOff,
asm: x86.AMOVLQSX,
reg: regInfo{
inputs: []inputInfo{
@ -3023,6 +3105,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVLQZXload",
auxType: auxSymOff,
asm: x86.AMOVLQZX,
reg: regInfo{
inputs: []inputInfo{
@ -3035,6 +3118,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVQload",
auxType: auxSymOff,
asm: x86.AMOVQ,
reg: regInfo{
inputs: []inputInfo{
@ -3047,6 +3131,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVQloadidx8",
auxType: auxSymOff,
asm: x86.AMOVQ,
reg: regInfo{
inputs: []inputInfo{
@ -3060,6 +3145,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVBstore",
auxType: auxSymOff,
asm: x86.AMOVB,
reg: regInfo{
inputs: []inputInfo{
@ -3070,6 +3156,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVWstore",
auxType: auxSymOff,
asm: x86.AMOVW,
reg: regInfo{
inputs: []inputInfo{
@ -3080,6 +3167,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVLstore",
auxType: auxSymOff,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
@ -3090,6 +3178,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVQstore",
auxType: auxSymOff,
asm: x86.AMOVQ,
reg: regInfo{
inputs: []inputInfo{
@ -3100,6 +3189,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVBstoreidx1",
auxType: auxSymOff,
asm: x86.AMOVB,
reg: regInfo{
inputs: []inputInfo{
@ -3111,6 +3201,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVWstoreidx2",
auxType: auxSymOff,
asm: x86.AMOVW,
reg: regInfo{
inputs: []inputInfo{
@ -3122,6 +3213,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVLstoreidx4",
auxType: auxSymOff,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
@ -3133,6 +3225,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVQstoreidx8",
auxType: auxSymOff,
asm: x86.AMOVQ,
reg: regInfo{
inputs: []inputInfo{
@ -3144,6 +3237,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVOload",
auxType: auxSymOff,
asm: x86.AMOVUPS,
reg: regInfo{
inputs: []inputInfo{
@ -3156,6 +3250,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVOstore",
auxType: auxSymOff,
asm: x86.AMOVUPS,
reg: regInfo{
inputs: []inputInfo{
@ -3166,6 +3261,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVBstoreconst",
auxType: auxSymValAndOff,
asm: x86.AMOVB,
reg: regInfo{
inputs: []inputInfo{
@ -3175,6 +3271,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVWstoreconst",
auxType: auxSymValAndOff,
asm: x86.AMOVW,
reg: regInfo{
inputs: []inputInfo{
@ -3184,6 +3281,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVLstoreconst",
auxType: auxSymValAndOff,
asm: x86.AMOVL,
reg: regInfo{
inputs: []inputInfo{
@ -3193,6 +3291,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVQstoreconst",
auxType: auxSymValAndOff,
asm: x86.AMOVQ,
reg: regInfo{
inputs: []inputInfo{
@ -3202,6 +3301,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "DUFFZERO",
auxType: auxInt64,
reg: regInfo{
inputs: []inputInfo{
{0, 128}, // .DI
@ -3212,6 +3312,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "MOVOconst",
rematerializeable: true,
reg: regInfo{
outputs: []regMask{
4294901760, // .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15
@ -3231,12 +3332,14 @@ var opcodeTable = [...]opInfo{
},
{
name: "CALLstatic",
auxType: auxSymOff,
reg: regInfo{
clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
},
},
{
name: "CALLclosure",
auxType: auxInt64,
reg: regInfo{
inputs: []inputInfo{
{1, 4}, // .DX
@ -3247,18 +3350,21 @@ var opcodeTable = [...]opInfo{
},
{
name: "CALLdefer",
auxType: auxInt64,
reg: regInfo{
clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
},
},
{
name: "CALLgo",
auxType: auxInt64,
reg: regInfo{
clobbers: 12884901871, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .X0 .X1 .X2 .X3 .X4 .X5 .X6 .X7 .X8 .X9 .X10 .X11 .X12 .X13 .X14 .X15 .FLAGS
},
},
{
name: "CALLinter",
auxType: auxInt64,
reg: regInfo{
inputs: []inputInfo{
{0, 65519}, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -3268,6 +3374,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "DUFFCOPY",
auxType: auxInt64,
reg: regInfo{
inputs: []inputInfo{
{0, 128}, // .DI
@ -3767,18 +3874,22 @@ var opcodeTable = [...]opInfo{
},
{
name: "Lrot8",
auxType: auxInt64,
generic: true,
},
{
name: "Lrot16",
auxType: auxInt64,
generic: true,
},
{
name: "Lrot32",
auxType: auxInt64,
generic: true,
},
{
name: "Lrot64",
auxType: auxInt64,
generic: true,
},
{
@ -4075,10 +4186,12 @@ var opcodeTable = [...]opInfo{
},
{
name: "ConstBool",
auxType: auxBool,
generic: true,
},
{
name: "ConstString",
auxType: auxString,
generic: true,
},
{
@ -4087,26 +4200,32 @@ var opcodeTable = [...]opInfo{
},
{
name: "Const8",
auxType: auxInt8,
generic: true,
},
{
name: "Const16",
auxType: auxInt16,
generic: true,
},
{
name: "Const32",
auxType: auxInt32,
generic: true,
},
{
name: "Const64",
auxType: auxInt64,
generic: true,
},
{
name: "Const32F",
auxType: auxFloat,
generic: true,
},
{
name: "Const64F",
auxType: auxFloat,
generic: true,
},
{
@ -4123,10 +4242,12 @@ var opcodeTable = [...]opInfo{
},
{
name: "Arg",
auxType: auxSymOff,
generic: true,
},
{
name: "Addr",
auxType: auxSym,
generic: true,
},
{
@ -4139,6 +4260,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "Func",
auxType: auxSym,
generic: true,
},
{
@ -4147,34 +4269,42 @@ var opcodeTable = [...]opInfo{
},
{
name: "Store",
auxType: auxInt64,
generic: true,
},
{
name: "Move",
auxType: auxInt64,
generic: true,
},
{
name: "Zero",
auxType: auxInt64,
generic: true,
},
{
name: "ClosureCall",
auxType: auxInt64,
generic: true,
},
{
name: "StaticCall",
auxType: auxSymOff,
generic: true,
},
{
name: "DeferCall",
auxType: auxInt64,
generic: true,
},
{
name: "GoCall",
auxType: auxInt64,
generic: true,
},
{
name: "InterCall",
auxType: auxInt64,
generic: true,
},
{
@ -4323,6 +4453,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "OffPtr",
auxType: auxInt64,
generic: true,
},
{
@ -4399,6 +4530,7 @@ var opcodeTable = [...]opInfo{
},
{
name: "StructSelect",
auxType: auxInt64,
generic: true,
},
{
@ -4419,14 +4551,17 @@ var opcodeTable = [...]opInfo{
},
{
name: "VarDef",
auxType: auxSym,
generic: true,
},
{
name: "VarKill",
auxType: auxSym,
generic: true,
},
{
name: "VarLive",
auxType: auxSym,
generic: true,
},
}

2
src/cmd/compile/internal/ssa/passbm_test.go
View file

@ -68,7 +68,7 @@ func genFunction(size int) []bloc {
valn := func(s string, m, n int) string { return fmt.Sprintf("%s%d-%d", s, m, n) }
blocs = append(blocs,
Bloc("entry",
Valu(valn("store", 0, 4), OpArg, TypeMem, 0, ".mem"),
Valu(valn("store", 0, 4), OpInitMem, TypeMem, 0, nil),
Valu("sb", OpSB, TypeInvalid, 0, nil),
Goto(blockn(1)),
),

27
src/cmd/compile/internal/ssa/regalloc.go
View file

@ -1481,31 +1481,16 @@ func (e *edgeState) findRegFor(typ Type) Location {
}
func (v *Value) rematerializeable() bool {
// TODO: add a flags field to opInfo for this test?
regspec := opcodeTable[v.Op].reg
// rematerializeable ops must be able to fill any register.
outputs := regspec.outputs
if len(outputs) == 0 || countRegs(outputs[0]) <= 1 {
// Note: this case handles OpAMD64LoweredGetClosurePtr
// which can't be moved.
if !opcodeTable[v.Op].rematerializeable {
return false
}
// We can't rematerialize instructions which
// clobber the flags register.
if regspec.clobbers&flagRegMask != 0 {
return false
}
if len(v.Args) == 0 {
return true
}
if len(v.Args) == 1 && (v.Args[0].Op == OpSP || v.Args[0].Op == OpSB) {
for _, a := range v.Args {
// SP and SB (generated by OpSP and OpSB) are always available.
return true
}
if a.Op != OpSP && a.Op != OpSB {
return false
}
}
return true
}
type liveInfo struct {

6
src/cmd/compile/internal/ssa/regalloc_test.go
View file

@ -10,9 +10,9 @@ func TestLiveControlOps(t *testing.T) {
c := testConfig(t)
f := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("x", OpAMD64MOVBconst, TypeInt8, 0, 1),
Valu("y", OpAMD64MOVBconst, TypeInt8, 0, 2),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("x", OpAMD64MOVBconst, TypeInt8, 1, nil),
Valu("y", OpAMD64MOVBconst, TypeInt8, 2, nil),
Valu("a", OpAMD64TESTB, TypeFlags, 0, nil, "x", "y"),
Valu("b", OpAMD64TESTB, TypeFlags, 0, nil, "y", "x"),
Eq("a", "if", "exit"),

2
src/cmd/compile/internal/ssa/schedule_test.go
View file

@ -11,7 +11,7 @@ func TestSchedule(t *testing.T) {
cases := []fun{
Fun(c, "entry",
Bloc("entry",
Valu("mem0", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem0", OpInitMem, TypeMem, 0, nil),
Valu("ptr", OpConst64, TypeInt64, 0xABCD, nil),
Valu("v", OpConst64, TypeInt64, 12, nil),
Valu("mem1", OpStore, TypeMem, 8, nil, "ptr", "v", "mem0"),

2
src/cmd/compile/internal/ssa/shift_test.go
View file

@ -34,7 +34,7 @@ func makeConstShiftFunc(c *Config, amount int64, op Op, typ Type) fun {
ptyp := &TypeImpl{Size_: 8, Ptr: true, Name: "ptr"}
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("SP", OpSP, TypeUInt64, 0, nil),
Valu("argptr", OpOffPtr, ptyp, 8, nil, "SP"),
Valu("resptr", OpOffPtr, ptyp, 16, nil, "SP"),

2
src/cmd/compile/internal/ssa/shortcircuit_test.go
View file

@ -11,7 +11,7 @@ func TestShortCircuit(t *testing.T) {
fun := Fun(c, "entry",
Bloc("entry",
Valu("mem", OpInitMem, TypeMem, 0, ".mem"),
Valu("mem", OpInitMem, TypeMem, 0, nil),
Valu("arg1", OpArg, TypeInt64, 0, nil),
Valu("arg2", OpArg, TypeInt64, 0, nil),
Valu("arg3", OpArg, TypeInt64, 0, nil),

70
src/cmd/compile/internal/ssa/value.go
View file

@ -57,34 +57,72 @@ func (v *Value) String() string {
return fmt.Sprintf("v%d", v.ID)
}
func (v *Value) AuxInt8() int8 {
if opcodeTable[v.Op].auxType != auxInt8 {
v.Fatalf("op %s doesn't have an int8 aux field", v.Op)
}
return int8(v.AuxInt)
}
func (v *Value) AuxInt16() int16 {
if opcodeTable[v.Op].auxType != auxInt16 {
v.Fatalf("op %s doesn't have an int16 aux field", v.Op)
}
return int16(v.AuxInt)
}
func (v *Value) AuxInt32() int32 {
if opcodeTable[v.Op].auxType != auxInt32 {
v.Fatalf("op %s doesn't have an int32 aux field", v.Op)
}
return int32(v.AuxInt)
}
func (v *Value) AuxFloat() float64 {
if opcodeTable[v.Op].auxType != auxFloat {
v.Fatalf("op %s doesn't have a float aux field", v.Op)
}
return math.Float64frombits(uint64(v.AuxInt))
}
func (v *Value) AuxValAndOff() ValAndOff {
if opcodeTable[v.Op].auxType != auxSymValAndOff {
v.Fatalf("op %s doesn't have a ValAndOff aux field", v.Op)
}
return ValAndOff(v.AuxInt)
}
// long form print. v# = opcode <type> [aux] args [: reg]
func (v *Value) LongString() string {
s := fmt.Sprintf("v%d = %s", v.ID, v.Op.String())
s += " <" + v.Type.String() + ">"
// TODO: use some operator property flags to decide
// what is encoded in the AuxInt field.
switch v.Op {
case OpConst32F, OpConst64F:
s += fmt.Sprintf(" [%g]", math.Float64frombits(uint64(v.AuxInt)))
case OpConstBool:
switch opcodeTable[v.Op].auxType {
case auxBool:
if v.AuxInt == 0 {
s += " [false]"
} else {
s += " [true]"
}
case OpAMD64MOVBstoreconst, OpAMD64MOVWstoreconst, OpAMD64MOVLstoreconst, OpAMD64MOVQstoreconst:
s += fmt.Sprintf(" [%s]", ValAndOff(v.AuxInt))
default:
if v.AuxInt != 0 {
case auxInt8:
s += fmt.Sprintf(" [%d]", v.AuxInt8())
case auxInt16:
s += fmt.Sprintf(" [%d]", v.AuxInt16())
case auxInt32:
s += fmt.Sprintf(" [%d]", v.AuxInt32())
case auxInt64:
s += fmt.Sprintf(" [%d]", v.AuxInt)
}
}
case auxFloat:
s += fmt.Sprintf(" [%g]", v.AuxFloat())
case auxString:
s += fmt.Sprintf(" {%s}", v.Aux)
case auxSymOff:
if v.Aux != nil {
if _, ok := v.Aux.(string); ok {
s += fmt.Sprintf(" {%q}", v.Aux)
} else {
s += fmt.Sprintf(" {%v}", v.Aux)
s += fmt.Sprintf(" {%s}", v.Aux)
}
s += fmt.Sprintf(" [%s]", v.AuxInt)
case auxSymValAndOff:
if v.Aux != nil {
s += fmt.Sprintf(" {%s}", v.Aux)
}
s += fmt.Sprintf(" [%s]", v.AuxValAndOff())
}
for _, a := range v.Args {
s += fmt.Sprintf(" %v", a)