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cmd/internal/obj/loong64: clean up code for short conditional branches

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Untangle the logic so the preparation of operands and actual assembling
(branch range checking included) are properly separated, making future
changes easier to review and maintain. No functional change intended.

Change-Id: I1f73282f9d92ff23d84846453d3597ba66d207d1
Reviewed-on: https://go-review.googlesource.com/c/go/+/478376
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
Auto-Submit: Ian Lance Taylor <iant@golang.org>
Run-TryBot: Cherry Mui <cherryyz@google.com>
Reviewed-by: Heschi Kreinick <heschi@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
This commit is contained in:
WANG Xuerui 2023-03-22 13:28:08 +08:00 • committed by Gopher Robot
parent abe4e7a446
commit 1ae306a5be
1 changed files with 15 additions and 15 deletions
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26
src/cmd/internal/obj/loong64/asm.go
View file

@ -1179,26 +1179,26 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
case 6: // beq r1,[r2],sbra
v := int32(0)
vcmp := int32(0)
if p.To.Target() != nil {
v = int32(p.To.Target().Pc-p.Pc) >> 2
}
if v < 0 {
vcmp = -v
rd, rj := p.Reg, p.From.Reg
if p.As == ABGTZ || p.As == ABLEZ {
rd, rj = rj, rd
}
if (p.As == ABFPT || p.As == ABFPF) && ((uint32(vcmp))>>21)&0x7FF != 0 {
switch p.As {
case ABFPT, ABFPF:
if (v<<11)>>11 != v {
c.ctxt.Diag("21 bit-width, short branch too far\n%v", p)
} else if p.As != ABFPT && p.As != ABFPF && (v<<16)>>16 != v {
}
// FCC0 is the implicit source operand, now that we
// don't register-allocate from the FCC bank.
o1 = OP_16IR_5I(c.opirr(p.As), uint32(v), uint32(REG_FCC0))
default:
if (v<<16)>>16 != v {
c.ctxt.Diag("16 bit-width, short branch too far\n%v", p)
}
if p.As == ABGTZ || p.As == ABLEZ {
o1 = OP_16IRR(c.opirr(p.As), uint32(v), uint32(p.Reg), uint32(p.From.Reg))
} else if p.As == ABFPT || p.As == ABFPF {
// BCNEZ cj offset21 ,cj = fcc0
// BCEQZ cj offset21 ,cj = fcc0
o1 = OP_16IR_5I(c.opirr(p.As), uint32(v), uint32(REG_FCC0))
} else {
o1 = OP_16IRR(c.opirr(p.As), uint32(v), uint32(p.From.Reg), uint32(p.Reg))
o1 = OP_16IRR(c.opirr(p.As), uint32(v), uint32(rj), uint32(rd))
}
case 7: // mov r, soreg