Stowage/go
2
0
Fork 0
mirror of https://github.com/golang/go.git synced 2025-12-08 06:10:04 +00:00
Code Issues Projects Releases Packages Wiki Activity

[dev.simd] cmd/compile: add fp1gp1fp1 register mask for AMD64

Browse source 
This is paired with a matching simdgen CL 682679

Change-Id: Id494d40b5e64b723a47c1682b71e523a77b0eb87
Reviewed-on: https://go-review.googlesource.com/c/go/+/682656
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
This commit is contained in:
David Chase 2025-06-18 14:11:38 -04:00
parent 1313521f75
commit 1b87d52549
2 changed files with 11 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

19
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
View file

@ -182,14 +182,15 @@ func init() {
fpstore = regInfo{inputs: []regMask{gpspsb, fp, 0}}
fpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, fp, 0}}
fp1k1 = regInfo{inputs: fponly, outputs: maskonly}
k1fp1 = regInfo{inputs: maskonly, outputs: fponly}
fp2k1 = regInfo{inputs: []regMask{fp, fp}, outputs: maskonly}
fp1k1fp1 = regInfo{inputs: []regMask{fp, mask}, outputs: fponly}
fp2k1fp1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: fponly}
fp2k1k1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: maskonly}
fp3fp1 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: fponly}
fp3k1fp1 = regInfo{inputs: []regMask{fp, fp, fp, mask}, outputs: fponly}
fp1k1 = regInfo{inputs: fponly, outputs: maskonly}
k1fp1 = regInfo{inputs: maskonly, outputs: fponly}
fp2k1 = regInfo{inputs: []regMask{fp, fp}, outputs: maskonly}
fp1k1fp1 = regInfo{inputs: []regMask{fp, mask}, outputs: fponly}
fp2k1fp1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: fponly}
fp2k1k1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: maskonly}
fp3fp1 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: fponly}
fp3k1fp1 = regInfo{inputs: []regMask{fp, fp, fp, mask}, outputs: fponly}
fp1gp1fp1 = regInfo{inputs: []regMask{fp, gp}, outputs: fponly}
prefreg = regInfo{inputs: []regMask{gpspsbg}}
)
@ -1300,7 +1301,7 @@ func init() {
pkg: "cmd/internal/obj/x86",
genfile: "../../amd64/ssa.go",
genSIMDfile: "../../amd64/simdssa.go",
ops: append(AMD64ops, simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp3fp1, fp3k1fp1)...), // AMD64ops,
ops: append(AMD64ops, simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp3fp1, fp3k1fp1, fp1gp1fp1)...), // AMD64ops,
blocks: AMD64blocks,
regnames: regNamesAMD64,
ParamIntRegNames: "AX BX CX DI SI R8 R9 R10 R11",

2
src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
View file

@ -1,7 +1,7 @@
// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT.
package main
func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1 regInfo) []opData {
func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1, fp1gp1fp1 regInfo) []opData {
return []opData{
{name: "VADDPS512", argLength: 2, reg: fp21, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDPS512", argLength: 2, reg: fp21, asm: "VANDPS", commutative: true, typ: "Vec512", resultInArg0: false},