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cmd/internal/obj/arm64: add assembler support for load with register offset
The patch adds support for LDR(register offset) instruction. And add the test cases and negative tests. Change-Id: I5b32c6a5065afc4571116d4896f7ebec3c0416d3 Reviewed-on: https://go-review.googlesource.com/87955 Reviewed-by: Cherry Zhang <cherryyz@google.com>
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parent
14393c5cd4
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31700b83b5
9 changed files with 251 additions and 87 deletions
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@ -214,7 +214,12 @@ func Dconv(p *Prog, a *Addr) string {
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case TYPE_MEM:
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str = Mconv(a)
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if a.Index != REG_NONE {
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str += fmt.Sprintf("(%v*%d)", Rconv(int(a.Index)), int(a.Scale))
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if a.Scale == 0 {
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// arm64 shifted or extended register offset, scale = 0.
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str += fmt.Sprintf("(%v)", Rconv(int(a.Index)))
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} else {
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str += fmt.Sprintf("(%v*%d)", Rconv(int(a.Index)), int(a.Scale))
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}
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}
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case TYPE_CONST:
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@ -294,7 +299,17 @@ func Mconv(a *Addr) string {
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case a.Offset == 0:
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str = fmt.Sprintf("(%v)", Rconv(int(a.Reg)))
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case a.Offset != 0:
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str = fmt.Sprintf("%d(%v)", a.Offset, Rconv(int(a.Reg)))
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switch objabi.GOARCH {
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case "arm64":
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// the register and the extension/shift are encoded in a.Offset.
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if a.Index != 0 {
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str = fmt.Sprintf("(%v)", Rconv(int(a.Reg)))
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return str
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}
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fallthrough
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default:
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str = fmt.Sprintf("%d(%v)", a.Offset, Rconv(int(a.Reg)))
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}
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}
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// Note: a.Reg == REG_NONE encodes the default base register for the NAME_ type.
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