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[dev.simd] cmd/compile: add round simd ops
This CL is generated by CL 678195. Change-Id: Ica600229a4e9623fa45f3b5aa370cdd6d9c31686 Reviewed-on: https://go-review.googlesource.com/c/go/+/681295 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Junyang Shao
parent
5289e0f24e
commit
34a9cdef87
8 changed files with 6904 additions and 0 deletions
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@ -74,6 +74,10 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPADDD512,
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ssa.OpAMD64VPADDQ512,
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ssa.OpAMD64VPADDB512,
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ssa.OpAMD64VADDSUBPS128,
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ssa.OpAMD64VADDSUBPS256,
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ssa.OpAMD64VADDSUBPD128,
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ssa.OpAMD64VADDSUBPD256,
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ssa.OpAMD64VANDPS128,
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ssa.OpAMD64VANDPS256,
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ssa.OpAMD64VANDPD128,
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@ -564,6 +568,38 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VSQRTPDMasked512:
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p = simdFp1k1fp1(s, v)
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case ssa.OpAMD64VROUNDPS128,
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ssa.OpAMD64VROUNDPS256,
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ssa.OpAMD64VROUNDPD128,
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ssa.OpAMD64VROUNDPD256,
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ssa.OpAMD64VRNDSCALEPS512,
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ssa.OpAMD64VRNDSCALEPS128,
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ssa.OpAMD64VRNDSCALEPS256,
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ssa.OpAMD64VRNDSCALEPD128,
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ssa.OpAMD64VRNDSCALEPD256,
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ssa.OpAMD64VRNDSCALEPD512,
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ssa.OpAMD64VREDUCEPS512,
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ssa.OpAMD64VREDUCEPS128,
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ssa.OpAMD64VREDUCEPS256,
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ssa.OpAMD64VREDUCEPD128,
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ssa.OpAMD64VREDUCEPD256,
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ssa.OpAMD64VREDUCEPD512:
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p = simdFp11Imm8(s, v)
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case ssa.OpAMD64VRNDSCALEPSMasked512,
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ssa.OpAMD64VRNDSCALEPSMasked128,
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ssa.OpAMD64VRNDSCALEPSMasked256,
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ssa.OpAMD64VRNDSCALEPDMasked128,
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ssa.OpAMD64VRNDSCALEPDMasked256,
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ssa.OpAMD64VRNDSCALEPDMasked512,
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ssa.OpAMD64VREDUCEPSMasked512,
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ssa.OpAMD64VREDUCEPSMasked128,
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ssa.OpAMD64VREDUCEPSMasked256,
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ssa.OpAMD64VREDUCEPDMasked128,
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ssa.OpAMD64VREDUCEPDMasked256,
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ssa.OpAMD64VREDUCEPDMasked512:
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p = simdFp1k1fp1Imm8(s, v)
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case ssa.OpAMD64VCMPPS128,
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ssa.OpAMD64VCMPPS256,
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ssa.OpAMD64VCMPPD128,
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@ -709,6 +745,18 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPAVGBMasked128,
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ssa.OpAMD64VPAVGBMasked256,
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ssa.OpAMD64VPAVGBMasked512,
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ssa.OpAMD64VRNDSCALEPSMasked512,
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ssa.OpAMD64VRNDSCALEPSMasked128,
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ssa.OpAMD64VRNDSCALEPSMasked256,
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ssa.OpAMD64VRNDSCALEPDMasked128,
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ssa.OpAMD64VRNDSCALEPDMasked256,
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ssa.OpAMD64VRNDSCALEPDMasked512,
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ssa.OpAMD64VREDUCEPSMasked512,
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ssa.OpAMD64VREDUCEPSMasked128,
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ssa.OpAMD64VREDUCEPSMasked256,
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ssa.OpAMD64VREDUCEPDMasked128,
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ssa.OpAMD64VREDUCEPDMasked256,
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ssa.OpAMD64VREDUCEPDMasked512,
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ssa.OpAMD64VDIVPSMasked512,
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ssa.OpAMD64VDIVPSMasked128,
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ssa.OpAMD64VDIVPSMasked256,
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@ -42,6 +42,10 @@
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(AddUint8x16 ...) => (VPADDB128 ...)
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(AddUint8x32 ...) => (VPADDB256 ...)
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(AddUint8x64 ...) => (VPADDB512 ...)
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(AddSubFloat32x4 ...) => (VADDSUBPS128 ...)
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(AddSubFloat32x8 ...) => (VADDSUBPS256 ...)
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(AddSubFloat64x2 ...) => (VADDSUBPD128 ...)
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(AddSubFloat64x4 ...) => (VADDSUBPD256 ...)
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(AndFloat32x16 ...) => (VANDPS512 ...)
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(AndFloat32x4 ...) => (VANDPS128 ...)
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(AndFloat32x8 ...) => (VANDPS256 ...)
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@ -112,6 +116,70 @@
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(AverageUint8x16 ...) => (VPAVGB128 ...)
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(AverageUint8x32 ...) => (VPAVGB256 ...)
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(AverageUint8x64 ...) => (VPAVGB512 ...)
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(CeilFloat32x4 x) => (VROUNDPS128 [2] x)
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(CeilFloat32x8 x) => (VROUNDPS256 [2] x)
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(CeilFloat64x2 x) => (VROUNDPD128 [2] x)
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(CeilFloat64x4 x) => (VROUNDPD256 [2] x)
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(CeilSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+10] x)
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(CeilSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+10] x)
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(CeilSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+10] x)
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(CeilSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+10] x)
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(CeilSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+10] x)
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(CeilSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+10] x)
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(CeilWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+2] x)
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(CeilWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+2] x)
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(CeilWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+2] x)
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(CeilWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+2] x)
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(CeilWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+2] x)
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(CeilWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+2] x)
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(DiffWithCeilSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+10] x)
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(DiffWithCeilSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+10] x)
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(DiffWithCeilSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+10] x)
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(DiffWithCeilSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+10] x)
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(DiffWithCeilSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+10] x)
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(DiffWithCeilSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+10] x)
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(DiffWithCeilWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+2] x)
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(DiffWithCeilWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+2] x)
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(DiffWithCeilWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+2] x)
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(DiffWithCeilWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+2] x)
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(DiffWithCeilWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+2] x)
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(DiffWithCeilWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+2] x)
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(DiffWithFloorSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+9] x)
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(DiffWithFloorSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+9] x)
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(DiffWithFloorSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+9] x)
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(DiffWithFloorSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+9] x)
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(DiffWithFloorSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+9] x)
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(DiffWithFloorSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+9] x)
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(DiffWithFloorWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+1] x)
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(DiffWithFloorWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+1] x)
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(DiffWithFloorWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+1] x)
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(DiffWithFloorWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+1] x)
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(DiffWithFloorWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+1] x)
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(DiffWithFloorWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+1] x)
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(DiffWithRoundSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+8] x)
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(DiffWithRoundSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+8] x)
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(DiffWithRoundSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+8] x)
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(DiffWithRoundSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+8] x)
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(DiffWithRoundSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+8] x)
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(DiffWithRoundSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+8] x)
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(DiffWithRoundWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+0] x)
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(DiffWithRoundWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+0] x)
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(DiffWithRoundWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+0] x)
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(DiffWithRoundWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+0] x)
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(DiffWithRoundWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+0] x)
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(DiffWithRoundWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+0] x)
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(DiffWithTruncSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+11] x)
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(DiffWithTruncSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+11] x)
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(DiffWithTruncSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+11] x)
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(DiffWithTruncSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+11] x)
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(DiffWithTruncSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+11] x)
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(DiffWithTruncSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+11] x)
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(DiffWithTruncWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+3] x)
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(DiffWithTruncWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+3] x)
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(DiffWithTruncWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+3] x)
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(DiffWithTruncWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+3] x)
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(DiffWithTruncWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+3] x)
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(DiffWithTruncWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+3] x)
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(DivFloat32x16 ...) => (VDIVPS512 ...)
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(DivFloat32x4 ...) => (VDIVPS128 ...)
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(DivFloat32x8 ...) => (VDIVPS256 ...)
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@ -148,6 +216,22 @@
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(EqualUint8x16 x y) => (VPMOVMToVec8x16 (VPCMPUB128 [0] x y))
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(EqualUint8x32 x y) => (VPMOVMToVec8x32 (VPCMPUB256 [0] x y))
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(EqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [0] x y))
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(FloorFloat32x4 x) => (VROUNDPS128 [1] x)
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(FloorFloat32x8 x) => (VROUNDPS256 [1] x)
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(FloorFloat64x2 x) => (VROUNDPD128 [1] x)
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(FloorFloat64x4 x) => (VROUNDPD256 [1] x)
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(FloorSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+9] x)
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(FloorSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+9] x)
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(FloorSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+9] x)
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(FloorSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+9] x)
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(FloorSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+9] x)
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(FloorSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+9] x)
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(FloorWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+1] x)
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(FloorWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+1] x)
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(FloorWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+1] x)
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(FloorWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+1] x)
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(FloorWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+1] x)
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(FloorWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+1] x)
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(GreaterFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [6] x y))
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(GreaterFloat32x4 x y) => (VCMPPS128 [6] x y)
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(GreaterFloat32x8 x y) => (VCMPPS256 [6] x y)
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@ -370,6 +454,66 @@
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(MaskedAverageUint8x16 x y mask) => (VPAVGBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
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(MaskedAverageUint8x32 x y mask) => (VPAVGBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
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(MaskedAverageUint8x64 x y mask) => (VPAVGBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
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(MaskedCeilSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+10] x (VPMOVVec32x16ToM <types.TypeMask> mask))
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(MaskedCeilSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+10] x (VPMOVVec32x4ToM <types.TypeMask> mask))
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(MaskedCeilSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+10] x (VPMOVVec32x8ToM <types.TypeMask> mask))
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(MaskedCeilSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+10] x (VPMOVVec64x2ToM <types.TypeMask> mask))
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(MaskedCeilSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+10] x (VPMOVVec64x4ToM <types.TypeMask> mask))
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(MaskedCeilSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+10] x (VPMOVVec64x8ToM <types.TypeMask> mask))
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(MaskedCeilWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+2] x (VPMOVVec32x16ToM <types.TypeMask> mask))
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(MaskedCeilWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+2] x (VPMOVVec32x4ToM <types.TypeMask> mask))
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(MaskedCeilWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+2] x (VPMOVVec32x8ToM <types.TypeMask> mask))
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(MaskedCeilWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+2] x (VPMOVVec64x2ToM <types.TypeMask> mask))
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(MaskedCeilWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+2] x (VPMOVVec64x4ToM <types.TypeMask> mask))
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(MaskedCeilWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+2] x (VPMOVVec64x8ToM <types.TypeMask> mask))
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(MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+10] x (VPMOVVec32x16ToM <types.TypeMask> mask))
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(MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+10] x (VPMOVVec32x4ToM <types.TypeMask> mask))
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(MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+10] x (VPMOVVec32x8ToM <types.TypeMask> mask))
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(MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+10] x (VPMOVVec64x2ToM <types.TypeMask> mask))
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(MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+10] x (VPMOVVec64x4ToM <types.TypeMask> mask))
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(MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+10] x (VPMOVVec64x8ToM <types.TypeMask> mask))
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(MaskedDiffWithCeilWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+2] x (VPMOVVec32x16ToM <types.TypeMask> mask))
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(MaskedDiffWithCeilWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+2] x (VPMOVVec32x4ToM <types.TypeMask> mask))
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(MaskedDiffWithCeilWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+2] x (VPMOVVec32x8ToM <types.TypeMask> mask))
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(MaskedDiffWithCeilWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+2] x (VPMOVVec64x2ToM <types.TypeMask> mask))
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(MaskedDiffWithCeilWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+2] x (VPMOVVec64x4ToM <types.TypeMask> mask))
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(MaskedDiffWithCeilWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+2] x (VPMOVVec64x8ToM <types.TypeMask> mask))
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(MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+9] x (VPMOVVec32x16ToM <types.TypeMask> mask))
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(MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+9] x (VPMOVVec32x4ToM <types.TypeMask> mask))
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(MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+9] x (VPMOVVec32x8ToM <types.TypeMask> mask))
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(MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+9] x (VPMOVVec64x2ToM <types.TypeMask> mask))
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(MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+9] x (VPMOVVec64x4ToM <types.TypeMask> mask))
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(MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+9] x (VPMOVVec64x8ToM <types.TypeMask> mask))
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(MaskedDiffWithFloorWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+1] x (VPMOVVec32x16ToM <types.TypeMask> mask))
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(MaskedDiffWithFloorWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+1] x (VPMOVVec32x4ToM <types.TypeMask> mask))
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(MaskedDiffWithFloorWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+1] x (VPMOVVec32x8ToM <types.TypeMask> mask))
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(MaskedDiffWithFloorWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+1] x (VPMOVVec64x2ToM <types.TypeMask> mask))
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(MaskedDiffWithFloorWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+1] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithFloorWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+1] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+8] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+8] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+8] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+8] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+8] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+8] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithRoundWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+0] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithRoundWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+0] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithRoundWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+0] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithRoundWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+0] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithRoundWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+0] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithRoundWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+0] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+11] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+11] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+11] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+11] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+11] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+11] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithTruncWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+3] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithTruncWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+3] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithTruncWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+3] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithTruncWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+3] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithTruncWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+3] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedDiffWithTruncWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+3] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedDivFloat32x16 x y mask) => (VDIVPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedDivFloat32x4 x y mask) => (VDIVPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedDivFloat32x8 x y mask) => (VDIVPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
|
|
@ -406,6 +550,18 @@
|
|||
(MaskedEqualUint8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPUBMasked128 [0] x y (VPMOVVec8x16ToM <types.TypeMask> mask)))
|
||||
(MaskedEqualUint8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPUBMasked256 [0] x y (VPMOVVec8x32ToM <types.TypeMask> mask)))
|
||||
(MaskedEqualUint8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPUBMasked512 [0] x y (VPMOVVec8x64ToM <types.TypeMask> mask)))
|
||||
(MaskedFloorSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+9] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFloorSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+9] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFloorSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+9] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFloorSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+9] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFloorSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+9] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFloorSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+9] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFloorWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+1] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFloorWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+1] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFloorWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+1] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFloorWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+1] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFloorWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+1] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFloorWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+1] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedGreaterFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [6] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
|
||||
(MaskedGreaterFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [6] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
|
||||
(MaskedGreaterFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [6] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
|
||||
|
|
@ -697,6 +853,18 @@
|
|||
(MaskedPopCountUint8x16 x mask) => (VPOPCNTBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
|
||||
(MaskedPopCountUint8x32 x mask) => (VPOPCNTBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
|
||||
(MaskedPopCountUint8x64 x mask) => (VPOPCNTBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
|
||||
(MaskedRoundSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+8] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedRoundSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+8] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedRoundSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+8] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedRoundSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+8] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedRoundSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+8] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedRoundSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+8] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedRoundWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+0] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedRoundWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+0] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedRoundWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+0] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedRoundWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+0] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedRoundWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+0] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedRoundWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+0] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedSaturatedAddInt16x16 x y mask) => (VPADDSWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||
(MaskedSaturatedAddInt16x32 x y mask) => (VPADDSWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||
(MaskedSaturatedAddInt16x8 x y mask) => (VPADDSWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||
|
|
@ -757,6 +925,18 @@
|
|||
(MaskedSubUint8x16 x y mask) => (VPSUBBMasked128 x y (VPMOVVec8x16ToM <types.TypeMask> mask))
|
||||
(MaskedSubUint8x32 x y mask) => (VPSUBBMasked256 x y (VPMOVVec8x32ToM <types.TypeMask> mask))
|
||||
(MaskedSubUint8x64 x y mask) => (VPSUBBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
|
||||
(MaskedTruncSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+11] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedTruncSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+11] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedTruncSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+11] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedTruncSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+11] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedTruncSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+11] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedTruncSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+11] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedTruncWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+3] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedTruncWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+3] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedTruncWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+3] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedTruncWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+3] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedTruncWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+3] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedTruncWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+3] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedXorFloat32x16 x y mask) => (VXORPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedXorFloat32x4 x y mask) => (VXORPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedXorFloat32x8 x y mask) => (VXORPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
|
|
@ -976,6 +1156,22 @@
|
|||
(PopCountUint8x16 ...) => (VPOPCNTB128 ...)
|
||||
(PopCountUint8x32 ...) => (VPOPCNTB256 ...)
|
||||
(PopCountUint8x64 ...) => (VPOPCNTB512 ...)
|
||||
(RoundFloat32x4 x) => (VROUNDPS128 [0] x)
|
||||
(RoundFloat32x8 x) => (VROUNDPS256 [0] x)
|
||||
(RoundFloat64x2 x) => (VROUNDPD128 [0] x)
|
||||
(RoundFloat64x4 x) => (VROUNDPD256 [0] x)
|
||||
(RoundSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+8] x)
|
||||
(RoundSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+8] x)
|
||||
(RoundSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+8] x)
|
||||
(RoundSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+8] x)
|
||||
(RoundSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+8] x)
|
||||
(RoundSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+8] x)
|
||||
(RoundWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+0] x)
|
||||
(RoundWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+0] x)
|
||||
(RoundWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+0] x)
|
||||
(RoundWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+0] x)
|
||||
(RoundWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+0] x)
|
||||
(RoundWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+0] x)
|
||||
(SaturatedAddInt16x16 ...) => (VPADDSW256 ...)
|
||||
(SaturatedAddInt16x32 ...) => (VPADDSW512 ...)
|
||||
(SaturatedAddInt16x8 ...) => (VPADDSW128 ...)
|
||||
|
|
@ -1046,6 +1242,22 @@
|
|||
(SubUint8x16 ...) => (VPSUBB128 ...)
|
||||
(SubUint8x32 ...) => (VPSUBB256 ...)
|
||||
(SubUint8x64 ...) => (VPSUBB512 ...)
|
||||
(TruncFloat32x4 x) => (VROUNDPS128 [3] x)
|
||||
(TruncFloat32x8 x) => (VROUNDPS256 [3] x)
|
||||
(TruncFloat64x2 x) => (VROUNDPD128 [3] x)
|
||||
(TruncFloat64x4 x) => (VROUNDPD256 [3] x)
|
||||
(TruncSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+11] x)
|
||||
(TruncSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+11] x)
|
||||
(TruncSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+11] x)
|
||||
(TruncSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+11] x)
|
||||
(TruncSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+11] x)
|
||||
(TruncSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+11] x)
|
||||
(TruncWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+3] x)
|
||||
(TruncWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+3] x)
|
||||
(TruncWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+3] x)
|
||||
(TruncWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+3] x)
|
||||
(TruncWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+3] x)
|
||||
(TruncWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+3] x)
|
||||
(XorFloat32x16 ...) => (VXORPS512 ...)
|
||||
(XorFloat32x4 ...) => (VXORPS128 ...)
|
||||
(XorFloat32x8 ...) => (VXORPS256 ...)
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
|
|||
{name: "VSQRTPS512", argLength: 1, reg: fp11, asm: "VSQRTPS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VXORPS512", argLength: 2, reg: fp21, asm: "VXORPS", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VADDPS128", argLength: 2, reg: fp21, asm: "VADDPS", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VADDSUBPS128", argLength: 2, reg: fp21, asm: "VADDSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VANDPS128", argLength: 2, reg: fp21, asm: "VANDPS", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VANDNPS128", argLength: 2, reg: fp21, asm: "VANDNPS", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VRCP14PS128", argLength: 1, reg: fp11, asm: "VRCP14PS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
|
|
@ -58,6 +59,7 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
|
|||
{name: "VSQRTPS128", argLength: 1, reg: fp11, asm: "VSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VXORPS128", argLength: 2, reg: fp21, asm: "VXORPS", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VADDPS256", argLength: 2, reg: fp21, asm: "VADDPS", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VADDSUBPS256", argLength: 2, reg: fp21, asm: "VADDSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VANDPS256", argLength: 2, reg: fp21, asm: "VANDPS", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VANDNPS256", argLength: 2, reg: fp21, asm: "VANDNPS", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VRCP14PS256", argLength: 1, reg: fp11, asm: "VRCP14PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
|
|
@ -86,6 +88,7 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
|
|||
{name: "VSQRTPS256", argLength: 1, reg: fp11, asm: "VSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VXORPS256", argLength: 2, reg: fp21, asm: "VXORPS", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VADDPD128", argLength: 2, reg: fp21, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VADDSUBPD128", argLength: 2, reg: fp21, asm: "VADDSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VANDPD128", argLength: 2, reg: fp21, asm: "VANDPD", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VANDNPD128", argLength: 2, reg: fp21, asm: "VANDNPD", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VRCP14PD128", argLength: 1, reg: fp11, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
|
|
@ -114,6 +117,7 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
|
|||
{name: "VSQRTPD128", argLength: 1, reg: fp11, asm: "VSQRTPD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VXORPD128", argLength: 2, reg: fp21, asm: "VXORPD", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VADDPD256", argLength: 2, reg: fp21, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VADDSUBPD256", argLength: 2, reg: fp21, asm: "VADDSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VANDPD256", argLength: 2, reg: fp21, asm: "VANDPD", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VANDNPD256", argLength: 2, reg: fp21, asm: "VANDNPD", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VRCP14PD256", argLength: 1, reg: fp11, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
|
|
@ -543,17 +547,45 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
|
|||
{name: "VPMINUBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINUB", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPMAXUB512", argLength: 2, reg: fp21, asm: "VPMAXUB", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VPMINUB512", argLength: 2, reg: fp21, asm: "VPMINUB", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VRNDSCALEPS512", argLength: 1, reg: fp11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VREDUCEPS512", argLength: 1, reg: fp11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCMPPS512", argLength: 2, reg: fp2k1, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VRNDSCALEPSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VREDUCEPSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCMPPSMasked512", argLength: 3, reg: fp2k1k1, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VROUNDPS128", argLength: 1, reg: fp11, asm: "VROUNDPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VRNDSCALEPS128", argLength: 1, reg: fp11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VREDUCEPS128", argLength: 1, reg: fp11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCMPPS128", argLength: 2, reg: fp21, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VRNDSCALEPSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VREDUCEPSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCMPPSMasked128", argLength: 3, reg: fp2k1k1, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VROUNDPS256", argLength: 1, reg: fp11, asm: "VROUNDPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VRNDSCALEPS256", argLength: 1, reg: fp11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VREDUCEPS256", argLength: 1, reg: fp11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCMPPS256", argLength: 2, reg: fp21, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VRNDSCALEPSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VREDUCEPSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCMPPSMasked256", argLength: 3, reg: fp2k1k1, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VROUNDPD128", argLength: 1, reg: fp11, asm: "VROUNDPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VRNDSCALEPD128", argLength: 1, reg: fp11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VREDUCEPD128", argLength: 1, reg: fp11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCMPPD128", argLength: 2, reg: fp21, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VRNDSCALEPDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VREDUCEPDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCMPPDMasked128", argLength: 3, reg: fp2k1k1, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VROUNDPD256", argLength: 1, reg: fp11, asm: "VROUNDPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VRNDSCALEPD256", argLength: 1, reg: fp11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VREDUCEPD256", argLength: 1, reg: fp11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCMPPD256", argLength: 2, reg: fp21, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VRNDSCALEPDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VREDUCEPDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCMPPDMasked256", argLength: 3, reg: fp2k1k1, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VRNDSCALEPD512", argLength: 1, reg: fp11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VREDUCEPD512", argLength: 1, reg: fp11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCMPPD512", argLength: 2, reg: fp2k1, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VRNDSCALEPDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VREDUCEPDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCMPPDMasked512", argLength: 3, reg: fp2k1k1, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPW256", argLength: 2, reg: fp2k1, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
{name: "VPCMPWMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||
|
|
|
|||
|
|
@ -46,12 +46,15 @@ func simdGenericOps() []opData {
|
|||
{name: "SubFloat32x16", argLength: 2, commutative: false},
|
||||
{name: "XorFloat32x16", argLength: 2, commutative: true},
|
||||
{name: "AddFloat32x4", argLength: 2, commutative: true},
|
||||
{name: "AddSubFloat32x4", argLength: 2, commutative: false},
|
||||
{name: "AndFloat32x4", argLength: 2, commutative: true},
|
||||
{name: "AndNotFloat32x4", argLength: 2, commutative: true},
|
||||
{name: "ApproximateReciprocalFloat32x4", argLength: 1, commutative: false},
|
||||
{name: "ApproximateReciprocalOfSqrtFloat32x4", argLength: 1, commutative: false},
|
||||
{name: "CeilFloat32x4", argLength: 1, commutative: false},
|
||||
{name: "DivFloat32x4", argLength: 2, commutative: false},
|
||||
{name: "EqualFloat32x4", argLength: 2, commutative: true},
|
||||
{name: "FloorFloat32x4", argLength: 1, commutative: false},
|
||||
{name: "GreaterFloat32x4", argLength: 2, commutative: false},
|
||||
{name: "GreaterEqualFloat32x4", argLength: 2, commutative: false},
|
||||
{name: "IsNanFloat32x4", argLength: 2, commutative: true},
|
||||
|
|
@ -86,16 +89,21 @@ func simdGenericOps() []opData {
|
|||
{name: "OrFloat32x4", argLength: 2, commutative: true},
|
||||
{name: "PairwiseAddFloat32x4", argLength: 2, commutative: false},
|
||||
{name: "PairwiseSubFloat32x4", argLength: 2, commutative: false},
|
||||
{name: "RoundFloat32x4", argLength: 1, commutative: false},
|
||||
{name: "SqrtFloat32x4", argLength: 1, commutative: false},
|
||||
{name: "SubFloat32x4", argLength: 2, commutative: false},
|
||||
{name: "TruncFloat32x4", argLength: 1, commutative: false},
|
||||
{name: "XorFloat32x4", argLength: 2, commutative: true},
|
||||
{name: "AddFloat32x8", argLength: 2, commutative: true},
|
||||
{name: "AddSubFloat32x8", argLength: 2, commutative: false},
|
||||
{name: "AndFloat32x8", argLength: 2, commutative: true},
|
||||
{name: "AndNotFloat32x8", argLength: 2, commutative: true},
|
||||
{name: "ApproximateReciprocalFloat32x8", argLength: 1, commutative: false},
|
||||
{name: "ApproximateReciprocalOfSqrtFloat32x8", argLength: 1, commutative: false},
|
||||
{name: "CeilFloat32x8", argLength: 1, commutative: false},
|
||||
{name: "DivFloat32x8", argLength: 2, commutative: false},
|
||||
{name: "EqualFloat32x8", argLength: 2, commutative: true},
|
||||
{name: "FloorFloat32x8", argLength: 1, commutative: false},
|
||||
{name: "GreaterFloat32x8", argLength: 2, commutative: false},
|
||||
{name: "GreaterEqualFloat32x8", argLength: 2, commutative: false},
|
||||
{name: "IsNanFloat32x8", argLength: 2, commutative: true},
|
||||
|
|
@ -130,16 +138,21 @@ func simdGenericOps() []opData {
|
|||
{name: "OrFloat32x8", argLength: 2, commutative: true},
|
||||
{name: "PairwiseAddFloat32x8", argLength: 2, commutative: false},
|
||||
{name: "PairwiseSubFloat32x8", argLength: 2, commutative: false},
|
||||
{name: "RoundFloat32x8", argLength: 1, commutative: false},
|
||||
{name: "SqrtFloat32x8", argLength: 1, commutative: false},
|
||||
{name: "SubFloat32x8", argLength: 2, commutative: false},
|
||||
{name: "TruncFloat32x8", argLength: 1, commutative: false},
|
||||
{name: "XorFloat32x8", argLength: 2, commutative: true},
|
||||
{name: "AddFloat64x2", argLength: 2, commutative: true},
|
||||
{name: "AddSubFloat64x2", argLength: 2, commutative: false},
|
||||
{name: "AndFloat64x2", argLength: 2, commutative: true},
|
||||
{name: "AndNotFloat64x2", argLength: 2, commutative: true},
|
||||
{name: "ApproximateReciprocalFloat64x2", argLength: 1, commutative: false},
|
||||
{name: "ApproximateReciprocalOfSqrtFloat64x2", argLength: 1, commutative: false},
|
||||
{name: "CeilFloat64x2", argLength: 1, commutative: false},
|
||||
{name: "DivFloat64x2", argLength: 2, commutative: false},
|
||||
{name: "EqualFloat64x2", argLength: 2, commutative: true},
|
||||
{name: "FloorFloat64x2", argLength: 1, commutative: false},
|
||||
{name: "GreaterFloat64x2", argLength: 2, commutative: false},
|
||||
{name: "GreaterEqualFloat64x2", argLength: 2, commutative: false},
|
||||
{name: "IsNanFloat64x2", argLength: 2, commutative: true},
|
||||
|
|
@ -174,16 +187,21 @@ func simdGenericOps() []opData {
|
|||
{name: "OrFloat64x2", argLength: 2, commutative: true},
|
||||
{name: "PairwiseAddFloat64x2", argLength: 2, commutative: false},
|
||||
{name: "PairwiseSubFloat64x2", argLength: 2, commutative: false},
|
||||
{name: "RoundFloat64x2", argLength: 1, commutative: false},
|
||||
{name: "SqrtFloat64x2", argLength: 1, commutative: false},
|
||||
{name: "SubFloat64x2", argLength: 2, commutative: false},
|
||||
{name: "TruncFloat64x2", argLength: 1, commutative: false},
|
||||
{name: "XorFloat64x2", argLength: 2, commutative: true},
|
||||
{name: "AddFloat64x4", argLength: 2, commutative: true},
|
||||
{name: "AddSubFloat64x4", argLength: 2, commutative: false},
|
||||
{name: "AndFloat64x4", argLength: 2, commutative: true},
|
||||
{name: "AndNotFloat64x4", argLength: 2, commutative: true},
|
||||
{name: "ApproximateReciprocalFloat64x4", argLength: 1, commutative: false},
|
||||
{name: "ApproximateReciprocalOfSqrtFloat64x4", argLength: 1, commutative: false},
|
||||
{name: "CeilFloat64x4", argLength: 1, commutative: false},
|
||||
{name: "DivFloat64x4", argLength: 2, commutative: false},
|
||||
{name: "EqualFloat64x4", argLength: 2, commutative: true},
|
||||
{name: "FloorFloat64x4", argLength: 1, commutative: false},
|
||||
{name: "GreaterFloat64x4", argLength: 2, commutative: false},
|
||||
{name: "GreaterEqualFloat64x4", argLength: 2, commutative: false},
|
||||
{name: "IsNanFloat64x4", argLength: 2, commutative: true},
|
||||
|
|
@ -218,8 +236,10 @@ func simdGenericOps() []opData {
|
|||
{name: "OrFloat64x4", argLength: 2, commutative: true},
|
||||
{name: "PairwiseAddFloat64x4", argLength: 2, commutative: false},
|
||||
{name: "PairwiseSubFloat64x4", argLength: 2, commutative: false},
|
||||
{name: "RoundFloat64x4", argLength: 1, commutative: false},
|
||||
{name: "SqrtFloat64x4", argLength: 1, commutative: false},
|
||||
{name: "SubFloat64x4", argLength: 2, commutative: false},
|
||||
{name: "TruncFloat64x4", argLength: 1, commutative: false},
|
||||
{name: "XorFloat64x4", argLength: 2, commutative: true},
|
||||
{name: "AddFloat64x8", argLength: 2, commutative: true},
|
||||
{name: "AndFloat64x8", argLength: 2, commutative: true},
|
||||
|
|
@ -1075,5 +1095,197 @@ func simdGenericOps() []opData {
|
|||
{name: "SaturatedAddUint8x64", argLength: 2, commutative: true},
|
||||
{name: "SaturatedSubUint8x64", argLength: 2, commutative: false},
|
||||
{name: "SubUint8x64", argLength: 2, commutative: false},
|
||||
{name: "CeilSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "CeilWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithCeilSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithCeilWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithFloorSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithFloorWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithRoundSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithRoundWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithTruncSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithTruncWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "FloorSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "FloorWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedCeilSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedCeilWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithCeilWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithFloorWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithRoundWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithTruncWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedFloorSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedFloorWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedRoundSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedRoundWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedTruncSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedTruncWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "RoundSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "RoundWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "TruncSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "TruncWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "CeilSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "CeilWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithCeilSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithCeilWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithFloorSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithFloorWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithRoundSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithRoundWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithTruncSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithTruncWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "FloorSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "FloorWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedCeilSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedCeilWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithCeilWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithFloorWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithRoundWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithTruncWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedFloorSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedFloorWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedRoundSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedRoundWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedTruncSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedTruncWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "RoundSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "RoundWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "TruncSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "TruncWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "CeilSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "CeilWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithCeilSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithCeilWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithFloorSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithFloorWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithRoundSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithRoundWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithTruncSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithTruncWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "FloorSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "FloorWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedCeilSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedCeilWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithCeilWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithFloorWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithRoundWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithTruncWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedFloorSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedFloorWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedRoundSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedRoundWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedTruncSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedTruncWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "RoundSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "RoundWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "TruncSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "TruncWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "CeilSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "CeilWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithCeilSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithCeilWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithFloorSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithFloorWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithRoundSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithRoundWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithTruncSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithTruncWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "FloorSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "FloorWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedCeilSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedCeilWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithCeilWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithFloorWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithRoundWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithTruncWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedFloorSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedFloorWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedRoundSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedRoundWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedTruncSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedTruncWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "RoundSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "RoundWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "TruncSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "TruncWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "CeilSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "CeilWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithCeilSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithCeilWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithFloorSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithFloorWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithRoundSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithRoundWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithTruncSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithTruncWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "FloorSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "FloorWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedCeilSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedCeilWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithCeilWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithFloorWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithRoundWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithTruncWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedFloorSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedFloorWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedRoundSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedRoundWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedTruncSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedTruncWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "RoundSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "RoundWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "TruncSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "TruncWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "CeilSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "CeilWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithCeilSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithCeilWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithFloorSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithFloorWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithRoundSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithRoundWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithTruncSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "DiffWithTruncWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "FloorSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "FloorWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedCeilSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedCeilWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithCeilWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithFloorWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithRoundWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedDiffWithTruncWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedFloorSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedFloorWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedRoundSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedRoundWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedTruncSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "MaskedTruncWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||
{name: "RoundSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "RoundWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "TruncSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
{name: "TruncWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||
}
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -16,16 +16,32 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Float32x16.Sqrt", opLen1(ssa.OpSqrtFloat32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.ApproximateReciprocal", opLen1(ssa.OpApproximateReciprocalFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.ApproximateReciprocalOfSqrt", opLen1(ssa.OpApproximateReciprocalOfSqrtFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.Ceil", opLen1(ssa.OpCeilFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.Floor", opLen1(ssa.OpFloorFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.Round", opLen1(ssa.OpRoundFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.Sqrt", opLen1(ssa.OpSqrtFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.Trunc", opLen1(ssa.OpTruncFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.ApproximateReciprocal", opLen1(ssa.OpApproximateReciprocalFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.ApproximateReciprocalOfSqrt", opLen1(ssa.OpApproximateReciprocalOfSqrtFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.Ceil", opLen1(ssa.OpCeilFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.Floor", opLen1(ssa.OpFloorFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.Round", opLen1(ssa.OpRoundFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.Sqrt", opLen1(ssa.OpSqrtFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.Trunc", opLen1(ssa.OpTruncFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.ApproximateReciprocal", opLen1(ssa.OpApproximateReciprocalFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.ApproximateReciprocalOfSqrt", opLen1(ssa.OpApproximateReciprocalOfSqrtFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.Ceil", opLen1(ssa.OpCeilFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.Floor", opLen1(ssa.OpFloorFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.Round", opLen1(ssa.OpRoundFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.Sqrt", opLen1(ssa.OpSqrtFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.Trunc", opLen1(ssa.OpTruncFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.ApproximateReciprocal", opLen1(ssa.OpApproximateReciprocalFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.ApproximateReciprocalOfSqrt", opLen1(ssa.OpApproximateReciprocalOfSqrtFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.Ceil", opLen1(ssa.OpCeilFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.Floor", opLen1(ssa.OpFloorFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.Round", opLen1(ssa.OpRoundFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.Sqrt", opLen1(ssa.OpSqrtFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.Trunc", opLen1(ssa.OpTruncFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.ApproximateReciprocal", opLen1(ssa.OpApproximateReciprocalFloat64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.ApproximateReciprocalOfSqrt", opLen1(ssa.OpApproximateReciprocalOfSqrtFloat64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.Sqrt", opLen1(ssa.OpSqrtFloat64x8, types.TypeVec512), sys.AMD64)
|
||||
|
|
@ -87,6 +103,7 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Float32x16.Sub", opLen2(ssa.OpSubFloat32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.Xor", opLen2(ssa.OpXorFloat32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.Add", opLen2(ssa.OpAddFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.AddSub", opLen2(ssa.OpAddSubFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.And", opLen2(ssa.OpAndFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.AndNot", opLen2(ssa.OpAndNotFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.Div", opLen2(ssa.OpDivFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
|
|
@ -110,6 +127,7 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Float32x4.Sub", opLen2(ssa.OpSubFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.Xor", opLen2(ssa.OpXorFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.Add", opLen2(ssa.OpAddFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.AddSub", opLen2(ssa.OpAddSubFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.And", opLen2(ssa.OpAndFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.AndNot", opLen2(ssa.OpAndNotFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.Div", opLen2(ssa.OpDivFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
|
|
@ -133,6 +151,7 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Float32x8.Sub", opLen2(ssa.OpSubFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.Xor", opLen2(ssa.OpXorFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.Add", opLen2(ssa.OpAddFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.AddSub", opLen2(ssa.OpAddSubFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.And", opLen2(ssa.OpAndFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.AndNot", opLen2(ssa.OpAndNotFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.Div", opLen2(ssa.OpDivFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
|
|
@ -156,6 +175,7 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Float64x2.Sub", opLen2(ssa.OpSubFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.Xor", opLen2(ssa.OpXorFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.Add", opLen2(ssa.OpAddFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.AddSub", opLen2(ssa.OpAddSubFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.And", opLen2(ssa.OpAndFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.AndNot", opLen2(ssa.OpAndNotFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.Div", opLen2(ssa.OpDivFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
|
|
@ -1083,6 +1103,198 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Uint8x64.MaskedSaturatedAdd", opLen3(ssa.OpMaskedSaturatedAddUint8x64, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Uint8x64.MaskedSaturatedSub", opLen3(ssa.OpMaskedSaturatedSubUint8x64, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Uint8x64.MaskedSub", opLen3(ssa.OpMaskedSubUint8x64, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.CeilSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpCeilSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.CeilSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpCeilSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.CeilSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpCeilSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.CeilSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpCeilSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.CeilSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpCeilSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.CeilSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpCeilSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.CeilWithPrecision", opLen1Imm8(ssa.OpCeilWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.CeilWithPrecision", opLen1Imm8(ssa.OpCeilWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.CeilWithPrecision", opLen1Imm8(ssa.OpCeilWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.CeilWithPrecision", opLen1Imm8(ssa.OpCeilWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.CeilWithPrecision", opLen1Imm8(ssa.OpCeilWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.CeilWithPrecision", opLen1Imm8(ssa.OpCeilWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.DiffWithCeilSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.DiffWithCeilSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.DiffWithCeilSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.DiffWithCeilSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.DiffWithCeilSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.DiffWithCeilSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.DiffWithCeilWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.DiffWithCeilWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.DiffWithCeilWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.DiffWithCeilWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.DiffWithCeilWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.DiffWithCeilWithPrecision", opLen1Imm8(ssa.OpDiffWithCeilWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.DiffWithFloorSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.DiffWithFloorSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.DiffWithFloorSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.DiffWithFloorSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.DiffWithFloorSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.DiffWithFloorSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.DiffWithFloorWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.DiffWithFloorWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.DiffWithFloorWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.DiffWithFloorWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.DiffWithFloorWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.DiffWithFloorWithPrecision", opLen1Imm8(ssa.OpDiffWithFloorWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.DiffWithRoundSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.DiffWithRoundSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.DiffWithRoundSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.DiffWithRoundSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.DiffWithRoundSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.DiffWithRoundSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.DiffWithRoundWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.DiffWithRoundWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.DiffWithRoundWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.DiffWithRoundWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.DiffWithRoundWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.DiffWithRoundWithPrecision", opLen1Imm8(ssa.OpDiffWithRoundWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.DiffWithTruncSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.DiffWithTruncSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.DiffWithTruncSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.DiffWithTruncSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.DiffWithTruncSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.DiffWithTruncSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.DiffWithTruncWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.DiffWithTruncWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.DiffWithTruncWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.DiffWithTruncWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.DiffWithTruncWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.DiffWithTruncWithPrecision", opLen1Imm8(ssa.OpDiffWithTruncWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FloorSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpFloorSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FloorSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpFloorSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FloorSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpFloorSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FloorSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpFloorSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FloorSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpFloorSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FloorSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpFloorSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FloorWithPrecision", opLen1Imm8(ssa.OpFloorWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FloorWithPrecision", opLen1Imm8(ssa.OpFloorWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FloorWithPrecision", opLen1Imm8(ssa.OpFloorWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FloorWithPrecision", opLen1Imm8(ssa.OpFloorWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FloorWithPrecision", opLen1Imm8(ssa.OpFloorWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FloorWithPrecision", opLen1Imm8(ssa.OpFloorWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.RoundSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpRoundSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.RoundSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpRoundSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.RoundSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpRoundSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.RoundSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpRoundSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.RoundSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpRoundSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.RoundSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpRoundSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.RoundWithPrecision", opLen1Imm8(ssa.OpRoundWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.RoundWithPrecision", opLen1Imm8(ssa.OpRoundWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.RoundWithPrecision", opLen1Imm8(ssa.OpRoundWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.RoundWithPrecision", opLen1Imm8(ssa.OpRoundWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.RoundWithPrecision", opLen1Imm8(ssa.OpRoundWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.RoundWithPrecision", opLen1Imm8(ssa.OpRoundWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.TruncSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpTruncSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.TruncSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpTruncSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.TruncSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpTruncSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.TruncSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpTruncSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.TruncSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpTruncSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.TruncSuppressExceptionWithPrecision", opLen1Imm8(ssa.OpTruncSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.TruncWithPrecision", opLen1Imm8(ssa.OpTruncWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.TruncWithPrecision", opLen1Imm8(ssa.OpTruncWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.TruncWithPrecision", opLen1Imm8(ssa.OpTruncWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.TruncWithPrecision", opLen1Imm8(ssa.OpTruncWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.TruncWithPrecision", opLen1Imm8(ssa.OpTruncWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.TruncWithPrecision", opLen1Imm8(ssa.OpTruncWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedCeilSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedCeilSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedCeilSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedCeilSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedCeilSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedCeilSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedCeilSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedCeilSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedCeilSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedCeilSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedCeilSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedCeilSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedCeilWithPrecision", opLen2Imm8(ssa.OpMaskedCeilWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedCeilWithPrecision", opLen2Imm8(ssa.OpMaskedCeilWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedCeilWithPrecision", opLen2Imm8(ssa.OpMaskedCeilWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedCeilWithPrecision", opLen2Imm8(ssa.OpMaskedCeilWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedCeilWithPrecision", opLen2Imm8(ssa.OpMaskedCeilWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedCeilWithPrecision", opLen2Imm8(ssa.OpMaskedCeilWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedDiffWithCeilSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedDiffWithCeilSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedDiffWithCeilSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedDiffWithCeilSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedDiffWithCeilSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedDiffWithCeilSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedDiffWithCeilWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithCeilWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedDiffWithCeilWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithCeilWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedDiffWithCeilWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithCeilWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedDiffWithCeilWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithCeilWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedDiffWithCeilWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithCeilWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedDiffWithCeilWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithCeilWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedDiffWithFloorSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedDiffWithFloorSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedDiffWithFloorSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedDiffWithFloorSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedDiffWithFloorSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedDiffWithFloorSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedDiffWithFloorWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithFloorWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedDiffWithFloorWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithFloorWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedDiffWithFloorWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithFloorWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedDiffWithFloorWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithFloorWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedDiffWithFloorWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithFloorWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedDiffWithFloorWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithFloorWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedDiffWithRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedDiffWithRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedDiffWithRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedDiffWithRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedDiffWithRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedDiffWithRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedDiffWithRoundWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithRoundWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedDiffWithRoundWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithRoundWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedDiffWithRoundWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithRoundWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedDiffWithRoundWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithRoundWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedDiffWithRoundWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithRoundWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedDiffWithRoundWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithRoundWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedDiffWithTruncSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedDiffWithTruncSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedDiffWithTruncSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedDiffWithTruncSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedDiffWithTruncSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedDiffWithTruncSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedDiffWithTruncWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithTruncWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedDiffWithTruncWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithTruncWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedDiffWithTruncWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithTruncWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedDiffWithTruncWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithTruncWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedDiffWithTruncWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithTruncWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedDiffWithTruncWithPrecision", opLen2Imm8(ssa.OpMaskedDiffWithTruncWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFloorSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedFloorSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFloorSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedFloorSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFloorSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedFloorSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFloorSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedFloorSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFloorSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedFloorSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFloorSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedFloorSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFloorWithPrecision", opLen2Imm8(ssa.OpMaskedFloorWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFloorWithPrecision", opLen2Imm8(ssa.OpMaskedFloorWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFloorWithPrecision", opLen2Imm8(ssa.OpMaskedFloorWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFloorWithPrecision", opLen2Imm8(ssa.OpMaskedFloorWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFloorWithPrecision", opLen2Imm8(ssa.OpMaskedFloorWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFloorWithPrecision", opLen2Imm8(ssa.OpMaskedFloorWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedRoundWithPrecision", opLen2Imm8(ssa.OpMaskedRoundWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedRoundWithPrecision", opLen2Imm8(ssa.OpMaskedRoundWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedRoundWithPrecision", opLen2Imm8(ssa.OpMaskedRoundWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedRoundWithPrecision", opLen2Imm8(ssa.OpMaskedRoundWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedRoundWithPrecision", opLen2Imm8(ssa.OpMaskedRoundWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedRoundWithPrecision", opLen2Imm8(ssa.OpMaskedRoundWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedTruncSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedTruncSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedTruncSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedTruncSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedTruncSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedTruncSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedTruncSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedTruncSuppressExceptionWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedTruncSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedTruncSuppressExceptionWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedTruncSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedTruncSuppressExceptionWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedTruncWithPrecision", opLen2Imm8(ssa.OpMaskedTruncWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedTruncWithPrecision", opLen2Imm8(ssa.OpMaskedTruncWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedTruncWithPrecision", opLen2Imm8(ssa.OpMaskedTruncWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedTruncWithPrecision", opLen2Imm8(ssa.OpMaskedTruncWithPrecisionFloat64x2, types.TypeVec128, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedTruncWithPrecision", opLen2Imm8(ssa.OpMaskedTruncWithPrecisionFloat64x4, types.TypeVec256, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedTruncWithPrecision", opLen2Imm8(ssa.OpMaskedTruncWithPrecisionFloat64x8, types.TypeVec512, 4), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.AsFloat64x8", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.AsInt16x32", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.AsInt32x16", func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { return args[0] }, sys.AMD64)
|
||||
|
|
|
|||
|
|
@ -19,36 +19,84 @@ func (x Float32x4) ApproximateReciprocal() Float32x4
|
|||
// Asm: VRSQRTPS, CPU Feature: AVX
|
||||
func (x Float32x4) ApproximateReciprocalOfSqrt() Float32x4
|
||||
|
||||
// Asm: VROUNDPS, CPU Feature: AVX
|
||||
func (x Float32x4) Ceil() Float32x4
|
||||
|
||||
// Asm: VROUNDPS, CPU Feature: AVX
|
||||
func (x Float32x4) Floor() Float32x4
|
||||
|
||||
// Asm: VROUNDPS, CPU Feature: AVX
|
||||
func (x Float32x4) Round() Float32x4
|
||||
|
||||
// Asm: VSQRTPS, CPU Feature: AVX
|
||||
func (x Float32x4) Sqrt() Float32x4
|
||||
|
||||
// Asm: VROUNDPS, CPU Feature: AVX
|
||||
func (x Float32x4) Trunc() Float32x4
|
||||
|
||||
// Asm: VRCP14PS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) ApproximateReciprocal() Float32x8
|
||||
|
||||
// Asm: VRSQRTPS, CPU Feature: AVX
|
||||
func (x Float32x8) ApproximateReciprocalOfSqrt() Float32x8
|
||||
|
||||
// Asm: VROUNDPS, CPU Feature: AVX
|
||||
func (x Float32x8) Ceil() Float32x8
|
||||
|
||||
// Asm: VROUNDPS, CPU Feature: AVX
|
||||
func (x Float32x8) Floor() Float32x8
|
||||
|
||||
// Asm: VROUNDPS, CPU Feature: AVX
|
||||
func (x Float32x8) Round() Float32x8
|
||||
|
||||
// Asm: VSQRTPS, CPU Feature: AVX
|
||||
func (x Float32x8) Sqrt() Float32x8
|
||||
|
||||
// Asm: VROUNDPS, CPU Feature: AVX
|
||||
func (x Float32x8) Trunc() Float32x8
|
||||
|
||||
// Asm: VRCP14PD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) ApproximateReciprocal() Float64x2
|
||||
|
||||
// Asm: VRSQRT14PD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) ApproximateReciprocalOfSqrt() Float64x2
|
||||
|
||||
// Asm: VROUNDPD, CPU Feature: AVX
|
||||
func (x Float64x2) Ceil() Float64x2
|
||||
|
||||
// Asm: VROUNDPD, CPU Feature: AVX
|
||||
func (x Float64x2) Floor() Float64x2
|
||||
|
||||
// Asm: VROUNDPD, CPU Feature: AVX
|
||||
func (x Float64x2) Round() Float64x2
|
||||
|
||||
// Asm: VSQRTPD, CPU Feature: AVX
|
||||
func (x Float64x2) Sqrt() Float64x2
|
||||
|
||||
// Asm: VROUNDPD, CPU Feature: AVX
|
||||
func (x Float64x2) Trunc() Float64x2
|
||||
|
||||
// Asm: VRCP14PD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) ApproximateReciprocal() Float64x4
|
||||
|
||||
// Asm: VRSQRT14PD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) ApproximateReciprocalOfSqrt() Float64x4
|
||||
|
||||
// Asm: VROUNDPD, CPU Feature: AVX
|
||||
func (x Float64x4) Ceil() Float64x4
|
||||
|
||||
// Asm: VROUNDPD, CPU Feature: AVX
|
||||
func (x Float64x4) Floor() Float64x4
|
||||
|
||||
// Asm: VROUNDPD, CPU Feature: AVX
|
||||
func (x Float64x4) Round() Float64x4
|
||||
|
||||
// Asm: VSQRTPD, CPU Feature: AVX
|
||||
func (x Float64x4) Sqrt() Float64x4
|
||||
|
||||
// Asm: VROUNDPD, CPU Feature: AVX
|
||||
func (x Float64x4) Trunc() Float64x4
|
||||
|
||||
// Asm: VRCP14PD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) ApproximateReciprocal() Float64x8
|
||||
|
||||
|
|
@ -246,6 +294,9 @@ func (x Float32x16) Xor(y Float32x16) Float32x16
|
|||
// Asm: VADDPS, CPU Feature: AVX
|
||||
func (x Float32x4) Add(y Float32x4) Float32x4
|
||||
|
||||
// Asm: VADDSUBPS, CPU Feature: AVX
|
||||
func (x Float32x4) AddSub(y Float32x4) Float32x4
|
||||
|
||||
// Asm: VANDPS, CPU Feature: AVX
|
||||
func (x Float32x4) And(y Float32x4) Float32x4
|
||||
|
||||
|
|
@ -333,6 +384,9 @@ func (x Float32x4) Xor(y Float32x4) Float32x4
|
|||
// Asm: VADDPS, CPU Feature: AVX
|
||||
func (x Float32x8) Add(y Float32x8) Float32x8
|
||||
|
||||
// Asm: VADDSUBPS, CPU Feature: AVX
|
||||
func (x Float32x8) AddSub(y Float32x8) Float32x8
|
||||
|
||||
// Asm: VANDPS, CPU Feature: AVX
|
||||
func (x Float32x8) And(y Float32x8) Float32x8
|
||||
|
||||
|
|
@ -420,6 +474,9 @@ func (x Float32x8) Xor(y Float32x8) Float32x8
|
|||
// Asm: VADDPD, CPU Feature: AVX
|
||||
func (x Float64x2) Add(y Float64x2) Float64x2
|
||||
|
||||
// Asm: VADDSUBPD, CPU Feature: AVX
|
||||
func (x Float64x2) AddSub(y Float64x2) Float64x2
|
||||
|
||||
// Asm: VANDPD, CPU Feature: AVX
|
||||
func (x Float64x2) And(y Float64x2) Float64x2
|
||||
|
||||
|
|
@ -507,6 +564,9 @@ func (x Float64x2) Xor(y Float64x2) Float64x2
|
|||
// Asm: VADDPD, CPU Feature: AVX
|
||||
func (x Float64x4) Add(y Float64x4) Float64x4
|
||||
|
||||
// Asm: VADDSUBPD, CPU Feature: AVX
|
||||
func (x Float64x4) AddSub(y Float64x4) Float64x4
|
||||
|
||||
// Asm: VANDPD, CPU Feature: AVX
|
||||
func (x Float64x4) And(y Float64x4) Float64x4
|
||||
|
||||
|
|
@ -4112,6 +4172,582 @@ func (x Uint8x64) MaskedSaturatedSub(y Uint8x64, z Mask8x64) Uint8x64
|
|||
// Asm: VPSUBB, CPU Feature: AVX512EVEX
|
||||
func (x Uint8x64) MaskedSub(y Uint8x64, z Mask8x64) Uint8x64
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) CeilSuppressExceptionWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) CeilSuppressExceptionWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) CeilSuppressExceptionWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) CeilSuppressExceptionWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) CeilSuppressExceptionWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) CeilSuppressExceptionWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) CeilWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) CeilWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) CeilWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) CeilWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) CeilWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) CeilWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) DiffWithCeilSuppressExceptionWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) DiffWithCeilSuppressExceptionWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) DiffWithCeilSuppressExceptionWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) DiffWithCeilSuppressExceptionWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) DiffWithCeilSuppressExceptionWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) DiffWithCeilSuppressExceptionWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) DiffWithCeilWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) DiffWithCeilWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) DiffWithCeilWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) DiffWithCeilWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) DiffWithCeilWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) DiffWithCeilWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) DiffWithFloorSuppressExceptionWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) DiffWithFloorSuppressExceptionWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) DiffWithFloorSuppressExceptionWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) DiffWithFloorSuppressExceptionWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) DiffWithFloorSuppressExceptionWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) DiffWithFloorSuppressExceptionWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) DiffWithFloorWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) DiffWithFloorWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) DiffWithFloorWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) DiffWithFloorWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) DiffWithFloorWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) DiffWithFloorWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) DiffWithRoundSuppressExceptionWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) DiffWithRoundSuppressExceptionWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) DiffWithRoundSuppressExceptionWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) DiffWithRoundSuppressExceptionWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) DiffWithRoundSuppressExceptionWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) DiffWithRoundSuppressExceptionWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) DiffWithRoundWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) DiffWithRoundWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) DiffWithRoundWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) DiffWithRoundWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) DiffWithRoundWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) DiffWithRoundWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) DiffWithTruncSuppressExceptionWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) DiffWithTruncSuppressExceptionWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) DiffWithTruncSuppressExceptionWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) DiffWithTruncSuppressExceptionWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) DiffWithTruncSuppressExceptionWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) DiffWithTruncSuppressExceptionWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) DiffWithTruncWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) DiffWithTruncWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) DiffWithTruncWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) DiffWithTruncWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) DiffWithTruncWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) DiffWithTruncWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) FloorSuppressExceptionWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) FloorSuppressExceptionWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) FloorSuppressExceptionWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) FloorSuppressExceptionWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) FloorSuppressExceptionWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) FloorSuppressExceptionWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) FloorWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) FloorWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) FloorWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) FloorWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) FloorWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) FloorWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) RoundSuppressExceptionWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) RoundSuppressExceptionWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) RoundSuppressExceptionWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) RoundSuppressExceptionWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) RoundSuppressExceptionWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) RoundSuppressExceptionWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) RoundWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) RoundWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) RoundWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) RoundWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) RoundWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) RoundWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) TruncSuppressExceptionWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) TruncSuppressExceptionWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) TruncSuppressExceptionWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) TruncSuppressExceptionWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) TruncSuppressExceptionWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) TruncSuppressExceptionWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) TruncWithPrecision(imm8 uint8) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) TruncWithPrecision(imm8 uint8) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) TruncWithPrecision(imm8 uint8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) TruncWithPrecision(imm8 uint8) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) TruncWithPrecision(imm8 uint8) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) TruncWithPrecision(imm8 uint8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedCeilSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedCeilSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedCeilSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedCeilSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedCeilSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedCeilSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedCeilWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedCeilWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedCeilWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedCeilWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedCeilWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedCeilWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedDiffWithCeilSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedDiffWithCeilSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedDiffWithCeilSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedDiffWithCeilSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedDiffWithCeilSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedDiffWithCeilSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedDiffWithCeilWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedDiffWithCeilWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedDiffWithCeilWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedDiffWithCeilWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedDiffWithCeilWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedDiffWithCeilWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedDiffWithFloorSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedDiffWithFloorSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedDiffWithFloorSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedDiffWithFloorSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedDiffWithFloorSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedDiffWithFloorSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedDiffWithFloorWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedDiffWithFloorWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedDiffWithFloorWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedDiffWithFloorWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedDiffWithFloorWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedDiffWithFloorWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedDiffWithRoundSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedDiffWithRoundSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedDiffWithRoundSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedDiffWithRoundSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedDiffWithRoundSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedDiffWithRoundSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedDiffWithRoundWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedDiffWithRoundWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedDiffWithRoundWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedDiffWithRoundWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedDiffWithRoundWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedDiffWithRoundWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedDiffWithTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedDiffWithTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedDiffWithTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedDiffWithTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedDiffWithTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedDiffWithTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedDiffWithTruncWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedDiffWithTruncWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VREDUCEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedDiffWithTruncWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedDiffWithTruncWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedDiffWithTruncWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VREDUCEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedDiffWithTruncWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedFloorSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedFloorSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedFloorSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedFloorSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedFloorSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedFloorSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedFloorWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedFloorWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedFloorWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedFloorWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedFloorWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedFloorWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedRoundSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedRoundSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedRoundSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedRoundSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedRoundSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedRoundSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedRoundWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedRoundWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedRoundWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedRoundWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedRoundWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedRoundWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x16) MaskedTruncWithPrecision(imm uint8, y Mask32x16) Float32x16
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x4) MaskedTruncWithPrecision(imm uint8, y Mask32x4) Float32x4
|
||||
|
||||
// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX
|
||||
func (x Float32x8) MaskedTruncWithPrecision(imm uint8, y Mask32x8) Float32x8
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x2) MaskedTruncWithPrecision(imm uint8, y Mask64x2) Float64x2
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x4) MaskedTruncWithPrecision(imm uint8, y Mask64x4) Float64x4
|
||||
|
||||
// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX
|
||||
func (x Float64x8) MaskedTruncWithPrecision(imm uint8, y Mask64x8) Float64x8
|
||||
|
||||
// Float64x8 converts from Float32x16 to Float64x8
|
||||
func (from Float32x16) AsFloat64x8() (to Float64x8)
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue