diff --git a/src/cmd/compile/internal/amd64/simdssa.go b/src/cmd/compile/internal/amd64/simdssa.go index 90e2b135917..462b046d37a 100644 --- a/src/cmd/compile/internal/amd64/simdssa.go +++ b/src/cmd/compile/internal/amd64/simdssa.go @@ -1397,110 +1397,50 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { ssa.OpAMD64VSQRTPDMasked512load: p = simdVkvload(s, v) - case ssa.OpAMD64VADDPS128load, - ssa.OpAMD64VADDPS256load, - ssa.OpAMD64VADDPS512load, - ssa.OpAMD64VADDPD128load, - ssa.OpAMD64VADDPD256load, + case ssa.OpAMD64VADDPS512load, ssa.OpAMD64VADDPD512load, - ssa.OpAMD64VPADDD128load, - ssa.OpAMD64VPADDD256load, ssa.OpAMD64VPADDD512load, - ssa.OpAMD64VPADDQ128load, - ssa.OpAMD64VPADDQ256load, ssa.OpAMD64VPADDQ512load, ssa.OpAMD64VPANDD512load, ssa.OpAMD64VPANDQ512load, ssa.OpAMD64VPANDND512load, ssa.OpAMD64VPANDNQ512load, - ssa.OpAMD64VPACKSSDW128load, - ssa.OpAMD64VPACKSSDW256load, ssa.OpAMD64VPACKSSDW512load, - ssa.OpAMD64VPACKUSDW128load, - ssa.OpAMD64VPACKUSDW256load, ssa.OpAMD64VPACKUSDW512load, - ssa.OpAMD64VDIVPS128load, - ssa.OpAMD64VDIVPS256load, ssa.OpAMD64VDIVPS512load, - ssa.OpAMD64VDIVPD128load, - ssa.OpAMD64VDIVPD256load, ssa.OpAMD64VDIVPD512load, - ssa.OpAMD64VPCMPEQD128load, - ssa.OpAMD64VPCMPEQD256load, - ssa.OpAMD64VPCMPEQQ128load, - ssa.OpAMD64VPCMPEQQ256load, - ssa.OpAMD64VPCMPGTD128load, - ssa.OpAMD64VPCMPGTD256load, - ssa.OpAMD64VPCMPGTQ128load, - ssa.OpAMD64VPCMPGTQ256load, - ssa.OpAMD64VPUNPCKHDQ128load, - ssa.OpAMD64VPUNPCKHQDQ128load, - ssa.OpAMD64VPUNPCKHDQ256load, ssa.OpAMD64VPUNPCKHDQ512load, - ssa.OpAMD64VPUNPCKHQDQ256load, ssa.OpAMD64VPUNPCKHQDQ512load, - ssa.OpAMD64VPUNPCKLDQ128load, - ssa.OpAMD64VPUNPCKLQDQ128load, - ssa.OpAMD64VPUNPCKLDQ256load, ssa.OpAMD64VPUNPCKLDQ512load, - ssa.OpAMD64VPUNPCKLQDQ256load, ssa.OpAMD64VPUNPCKLQDQ512load, - ssa.OpAMD64VMAXPS128load, - ssa.OpAMD64VMAXPS256load, ssa.OpAMD64VMAXPS512load, - ssa.OpAMD64VMAXPD128load, - ssa.OpAMD64VMAXPD256load, ssa.OpAMD64VMAXPD512load, - ssa.OpAMD64VPMAXSD128load, - ssa.OpAMD64VPMAXSD256load, ssa.OpAMD64VPMAXSD512load, ssa.OpAMD64VPMAXSQ128load, ssa.OpAMD64VPMAXSQ256load, ssa.OpAMD64VPMAXSQ512load, - ssa.OpAMD64VPMAXUD128load, - ssa.OpAMD64VPMAXUD256load, ssa.OpAMD64VPMAXUD512load, ssa.OpAMD64VPMAXUQ128load, ssa.OpAMD64VPMAXUQ256load, ssa.OpAMD64VPMAXUQ512load, - ssa.OpAMD64VMINPS128load, - ssa.OpAMD64VMINPS256load, ssa.OpAMD64VMINPS512load, - ssa.OpAMD64VMINPD128load, - ssa.OpAMD64VMINPD256load, ssa.OpAMD64VMINPD512load, - ssa.OpAMD64VPMINSD128load, - ssa.OpAMD64VPMINSD256load, ssa.OpAMD64VPMINSD512load, ssa.OpAMD64VPMINSQ128load, ssa.OpAMD64VPMINSQ256load, ssa.OpAMD64VPMINSQ512load, - ssa.OpAMD64VPMINUD128load, - ssa.OpAMD64VPMINUD256load, ssa.OpAMD64VPMINUD512load, ssa.OpAMD64VPMINUQ128load, ssa.OpAMD64VPMINUQ256load, ssa.OpAMD64VPMINUQ512load, - ssa.OpAMD64VMULPS128load, - ssa.OpAMD64VMULPS256load, ssa.OpAMD64VMULPS512load, - ssa.OpAMD64VMULPD128load, - ssa.OpAMD64VMULPD256load, ssa.OpAMD64VMULPD512load, - ssa.OpAMD64VPMULLD128load, - ssa.OpAMD64VPMULLD256load, ssa.OpAMD64VPMULLD512load, ssa.OpAMD64VPMULLQ128load, ssa.OpAMD64VPMULLQ256load, ssa.OpAMD64VPMULLQ512load, - ssa.OpAMD64VPMULDQ128load, - ssa.OpAMD64VPMULDQ256load, - ssa.OpAMD64VPMULUDQ128load, - ssa.OpAMD64VPMULUDQ256load, ssa.OpAMD64VPORD512load, ssa.OpAMD64VPORQ512load, - ssa.OpAMD64VPERMPS256load, - ssa.OpAMD64VPERMD256load, ssa.OpAMD64VPERMPS512load, ssa.OpAMD64VPERMD512load, ssa.OpAMD64VPERMPD256load, @@ -1525,51 +1465,25 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { ssa.OpAMD64VSCALEFPD128load, ssa.OpAMD64VSCALEFPD256load, ssa.OpAMD64VSCALEFPD512load, - ssa.OpAMD64VPSLLVD128load, - ssa.OpAMD64VPSLLVD256load, ssa.OpAMD64VPSLLVD512load, - ssa.OpAMD64VPSLLVQ128load, - ssa.OpAMD64VPSLLVQ256load, ssa.OpAMD64VPSLLVQ512load, - ssa.OpAMD64VPSRAVD128load, - ssa.OpAMD64VPSRAVD256load, ssa.OpAMD64VPSRAVD512load, ssa.OpAMD64VPSRAVQ128load, ssa.OpAMD64VPSRAVQ256load, ssa.OpAMD64VPSRAVQ512load, - ssa.OpAMD64VPSRLVD128load, - ssa.OpAMD64VPSRLVD256load, ssa.OpAMD64VPSRLVD512load, - ssa.OpAMD64VPSRLVQ128load, - ssa.OpAMD64VPSRLVQ256load, ssa.OpAMD64VPSRLVQ512load, - ssa.OpAMD64VSUBPS128load, - ssa.OpAMD64VSUBPS256load, ssa.OpAMD64VSUBPS512load, - ssa.OpAMD64VSUBPD128load, - ssa.OpAMD64VSUBPD256load, ssa.OpAMD64VSUBPD512load, - ssa.OpAMD64VPSUBD128load, - ssa.OpAMD64VPSUBD256load, ssa.OpAMD64VPSUBD512load, - ssa.OpAMD64VPSUBQ128load, - ssa.OpAMD64VPSUBQ256load, ssa.OpAMD64VPSUBQ512load, ssa.OpAMD64VPXORD512load, ssa.OpAMD64VPXORQ512load: p = simdV21load(s, v) - case ssa.OpAMD64VPDPWSSD128load, - ssa.OpAMD64VPDPWSSD256load, - ssa.OpAMD64VPDPWSSD512load, - ssa.OpAMD64VPDPWSSDS128load, - ssa.OpAMD64VPDPWSSDS256load, + case ssa.OpAMD64VPDPWSSD512load, ssa.OpAMD64VPDPWSSDS512load, - ssa.OpAMD64VPDPBUSD128load, - ssa.OpAMD64VPDPBUSD256load, ssa.OpAMD64VPDPBUSD512load, - ssa.OpAMD64VPDPBUSDS128load, - ssa.OpAMD64VPDPBUSDS256load, ssa.OpAMD64VPDPBUSDS512load, ssa.OpAMD64VFMADD213PS128load, ssa.OpAMD64VFMADD213PS256load, @@ -1833,14 +1747,10 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { ssa.OpAMD64VPCMPGTQ512load: p = simdV2kload(s, v) - case ssa.OpAMD64VPABSD128load, - ssa.OpAMD64VPABSD256load, - ssa.OpAMD64VPABSD512load, + case ssa.OpAMD64VPABSD512load, ssa.OpAMD64VPABSQ128load, ssa.OpAMD64VPABSQ256load, ssa.OpAMD64VPABSQ512load, - ssa.OpAMD64VCVTTPS2DQ128load, - ssa.OpAMD64VCVTTPS2DQ256load, ssa.OpAMD64VCVTTPS2DQ512load, ssa.OpAMD64VCVTPS2UDQ128load, ssa.OpAMD64VCVTPS2UDQ256load, @@ -1865,11 +1775,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { ssa.OpAMD64VRSQRT14PD128load, ssa.OpAMD64VRSQRT14PD256load, ssa.OpAMD64VRSQRT14PD512load, - ssa.OpAMD64VSQRTPS128load, - ssa.OpAMD64VSQRTPS256load, ssa.OpAMD64VSQRTPS512load, - ssa.OpAMD64VSQRTPD128load, - ssa.OpAMD64VSQRTPD256load, ssa.OpAMD64VSQRTPD512load: p = simdV11load(s, v) @@ -1885,8 +1791,6 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { ssa.OpAMD64VREDUCEPD128load, ssa.OpAMD64VREDUCEPD256load, ssa.OpAMD64VREDUCEPD512load, - ssa.OpAMD64VPSHUFD128load, - ssa.OpAMD64VPSHUFD256load, ssa.OpAMD64VPSHUFD512load, ssa.OpAMD64VPROLD128load, ssa.OpAMD64VPROLD256load, @@ -1900,20 +1804,10 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { ssa.OpAMD64VPRORQ128load, ssa.OpAMD64VPRORQ256load, ssa.OpAMD64VPRORQ512load, - ssa.OpAMD64VPSLLD128constload, - ssa.OpAMD64VPSLLD256constload, ssa.OpAMD64VPSLLD512constload, - ssa.OpAMD64VPSLLQ128constload, - ssa.OpAMD64VPSLLQ256constload, ssa.OpAMD64VPSLLQ512constload, - ssa.OpAMD64VPSRLD128constload, - ssa.OpAMD64VPSRLD256constload, ssa.OpAMD64VPSRLD512constload, - ssa.OpAMD64VPSRLQ128constload, - ssa.OpAMD64VPSRLQ256constload, ssa.OpAMD64VPSRLQ512constload, - ssa.OpAMD64VPSRAD128constload, - ssa.OpAMD64VPSRAD256constload, ssa.OpAMD64VPSRAD512constload, ssa.OpAMD64VPSRAQ128constload, ssa.OpAMD64VPSRAQ256constload, @@ -1967,11 +1861,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { ssa.OpAMD64VPSRAQMasked512constload: p = simdVkvloadImm8(s, v) - case ssa.OpAMD64VCMPPS128load, - ssa.OpAMD64VCMPPS256load, - ssa.OpAMD64VCMPPD128load, - ssa.OpAMD64VCMPPD256load, - ssa.OpAMD64VGF2P8AFFINEQB128load, + case ssa.OpAMD64VGF2P8AFFINEQB128load, ssa.OpAMD64VGF2P8AFFINEQB256load, ssa.OpAMD64VGF2P8AFFINEQB512load, ssa.OpAMD64VGF2P8AFFINEINVQB128load, diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules index db5dc823c2f..65f47eb369b 100644 --- a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules +++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules @@ -1469,8 +1469,6 @@ (VMOVDQU16Masked512 (VPSRAW512const [a] x) mask) => (VPSRAWMasked512const [a] x mask) (VMOVDQU32Masked512 (VPSRAD512const [a] x) mask) => (VPSRADMasked512const [a] x mask) (VMOVDQU64Masked512 (VPSRAQ512const [a] x) mask) => (VPSRAQMasked512const [a] x mask) -(VPABSD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSD128load {sym} [off] ptr mem) -(VPABSD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSD256load {sym} [off] ptr mem) (VPABSD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSD512load {sym} [off] ptr mem) (VPABSQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSQ128load {sym} [off] ptr mem) (VPABSQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPABSQ256load {sym} [off] ptr mem) @@ -1481,38 +1479,22 @@ (VPABSQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSQMasked128load {sym} [off] ptr mask mem) (VPABSQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSQMasked256load {sym} [off] ptr mask mem) (VPABSQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPABSQMasked512load {sym} [off] ptr mask mem) -(VADDPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPS128load {sym} [off] x ptr mem) -(VADDPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPS256load {sym} [off] x ptr mem) (VADDPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPS512load {sym} [off] x ptr mem) -(VADDPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPD128load {sym} [off] x ptr mem) -(VADDPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPD256load {sym} [off] x ptr mem) (VADDPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VADDPD512load {sym} [off] x ptr mem) -(VPADDD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDD128load {sym} [off] x ptr mem) -(VPADDD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDD256load {sym} [off] x ptr mem) (VPADDD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDD512load {sym} [off] x ptr mem) -(VPADDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDQ128load {sym} [off] x ptr mem) -(VPADDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDQ256load {sym} [off] x ptr mem) (VPADDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPADDQ512load {sym} [off] x ptr mem) -(VPDPWSSD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSD128load {sym} [off] x y ptr mem) -(VPDPWSSD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSD256load {sym} [off] x y ptr mem) (VPDPWSSD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSD512load {sym} [off] x y ptr mem) (VPDPWSSDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDMasked128load {sym} [off] x y ptr mask mem) (VPDPWSSDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDMasked256load {sym} [off] x y ptr mask mem) (VPDPWSSDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDMasked512load {sym} [off] x y ptr mask mem) -(VPDPWSSDS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDS128load {sym} [off] x y ptr mem) -(VPDPWSSDS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDS256load {sym} [off] x y ptr mem) (VPDPWSSDS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDS512load {sym} [off] x y ptr mem) (VPDPWSSDSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDSMasked128load {sym} [off] x y ptr mask mem) (VPDPWSSDSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDSMasked256load {sym} [off] x y ptr mask mem) (VPDPWSSDSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPWSSDSMasked512load {sym} [off] x y ptr mask mem) -(VPDPBUSD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSD128load {sym} [off] x y ptr mem) -(VPDPBUSD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSD256load {sym} [off] x y ptr mem) (VPDPBUSD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSD512load {sym} [off] x y ptr mem) (VPDPBUSDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDMasked128load {sym} [off] x y ptr mask mem) (VPDPBUSDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDMasked256load {sym} [off] x y ptr mask mem) (VPDPBUSDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDMasked512load {sym} [off] x y ptr mask mem) -(VPDPBUSDS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDS128load {sym} [off] x y ptr mem) -(VPDPBUSDS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDS256load {sym} [off] x y ptr mem) (VPDPBUSDS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDS512load {sym} [off] x y ptr mem) (VPDPBUSDSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDSMasked128load {sym} [off] x y ptr mask mem) (VPDPBUSDSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPDPBUSDSMasked256load {sym} [off] x y ptr mask mem) @@ -1545,20 +1527,14 @@ (VPANDNQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNQMasked128load {sym} [off] x ptr mask mem) (VPANDNQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNQMasked256load {sym} [off] x ptr mask mem) (VPANDNQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPANDNQMasked512load {sym} [off] x ptr mask mem) -(VPACKSSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW128load {sym} [off] x ptr mem) -(VPACKSSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW256load {sym} [off] x ptr mem) (VPACKSSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDW512load {sym} [off] x ptr mem) (VPACKSSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked128load {sym} [off] x ptr mask mem) (VPACKSSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked256load {sym} [off] x ptr mask mem) (VPACKSSDWMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKSSDWMasked512load {sym} [off] x ptr mask mem) -(VCVTTPS2DQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ128load {sym} [off] ptr mem) -(VCVTTPS2DQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ256load {sym} [off] ptr mem) (VCVTTPS2DQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ512load {sym} [off] ptr mem) (VCVTTPS2DQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked128load {sym} [off] ptr mask mem) (VCVTTPS2DQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked256load {sym} [off] ptr mask mem) (VCVTTPS2DQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked512load {sym} [off] ptr mask mem) -(VPACKUSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW128load {sym} [off] x ptr mem) -(VPACKUSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW256load {sym} [off] x ptr mem) (VPACKUSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDW512load {sym} [off] x ptr mem) (VPACKUSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked128load {sym} [off] x ptr mask mem) (VPACKUSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPACKUSDWMasked256load {sym} [off] x ptr mask mem) @@ -1569,11 +1545,7 @@ (VCVTPS2UDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked128load {sym} [off] ptr mask mem) (VCVTPS2UDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked256load {sym} [off] ptr mask mem) (VCVTPS2UDQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked512load {sym} [off] ptr mask mem) -(VDIVPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPS128load {sym} [off] x ptr mem) -(VDIVPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPS256load {sym} [off] x ptr mem) (VDIVPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPS512load {sym} [off] x ptr mem) -(VDIVPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPD128load {sym} [off] x ptr mem) -(VDIVPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPD256load {sym} [off] x ptr mem) (VDIVPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPD512load {sym} [off] x ptr mem) (VDIVPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPSMasked128load {sym} [off] x ptr mask mem) (VDIVPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPSMasked256load {sym} [off] x ptr mask mem) @@ -1581,29 +1553,13 @@ (VDIVPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPDMasked128load {sym} [off] x ptr mask mem) (VDIVPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPDMasked256load {sym} [off] x ptr mask mem) (VDIVPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPDMasked512load {sym} [off] x ptr mask mem) -(VPCMPEQD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQD128load {sym} [off] x ptr mem) -(VPCMPEQD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQD256load {sym} [off] x ptr mem) (VPCMPEQD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQD512load {sym} [off] x ptr mem) -(VPCMPEQQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQQ128load {sym} [off] x ptr mem) -(VPCMPEQQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQQ256load {sym} [off] x ptr mem) (VPCMPEQQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPEQQ512load {sym} [off] x ptr mem) -(VPCMPGTD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTD128load {sym} [off] x ptr mem) -(VPCMPGTD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTD256load {sym} [off] x ptr mem) (VPCMPGTD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTD512load {sym} [off] x ptr mem) -(VPCMPGTQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTQ128load {sym} [off] x ptr mem) -(VPCMPGTQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTQ256load {sym} [off] x ptr mem) (VPCMPGTQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPCMPGTQ512load {sym} [off] x ptr mem) -(VPUNPCKHDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHDQ128load {sym} [off] x ptr mem) -(VPUNPCKHQDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHQDQ128load {sym} [off] x ptr mem) -(VPUNPCKHDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHDQ256load {sym} [off] x ptr mem) (VPUNPCKHDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHDQ512load {sym} [off] x ptr mem) -(VPUNPCKHQDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHQDQ256load {sym} [off] x ptr mem) (VPUNPCKHQDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKHQDQ512load {sym} [off] x ptr mem) -(VPUNPCKLDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLDQ128load {sym} [off] x ptr mem) -(VPUNPCKLQDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLQDQ128load {sym} [off] x ptr mem) -(VPUNPCKLDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLDQ256load {sym} [off] x ptr mem) (VPUNPCKLDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLDQ512load {sym} [off] x ptr mem) -(VPUNPCKLQDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLQDQ256load {sym} [off] x ptr mem) (VPUNPCKLQDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPUNPCKLQDQ512load {sym} [off] x ptr mem) (VPLZCNTD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTD128load {sym} [off] ptr mem) (VPLZCNTD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTD256load {sym} [off] ptr mem) @@ -1617,20 +1573,12 @@ (VPLZCNTQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTQMasked128load {sym} [off] ptr mask mem) (VPLZCNTQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTQMasked256load {sym} [off] ptr mask mem) (VPLZCNTQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPLZCNTQMasked512load {sym} [off] ptr mask mem) -(VMAXPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPS128load {sym} [off] x ptr mem) -(VMAXPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPS256load {sym} [off] x ptr mem) (VMAXPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPS512load {sym} [off] x ptr mem) -(VMAXPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPD128load {sym} [off] x ptr mem) -(VMAXPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPD256load {sym} [off] x ptr mem) (VMAXPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMAXPD512load {sym} [off] x ptr mem) -(VPMAXSD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSD128load {sym} [off] x ptr mem) -(VPMAXSD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSD256load {sym} [off] x ptr mem) (VPMAXSD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSD512load {sym} [off] x ptr mem) (VPMAXSQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQ128load {sym} [off] x ptr mem) (VPMAXSQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQ256load {sym} [off] x ptr mem) (VPMAXSQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXSQ512load {sym} [off] x ptr mem) -(VPMAXUD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUD128load {sym} [off] x ptr mem) -(VPMAXUD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUD256load {sym} [off] x ptr mem) (VPMAXUD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUD512load {sym} [off] x ptr mem) (VPMAXUQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQ128load {sym} [off] x ptr mem) (VPMAXUQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQ256load {sym} [off] x ptr mem) @@ -1653,20 +1601,12 @@ (VPMAXUQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQMasked128load {sym} [off] x ptr mask mem) (VPMAXUQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQMasked256load {sym} [off] x ptr mask mem) (VPMAXUQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMAXUQMasked512load {sym} [off] x ptr mask mem) -(VMINPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPS128load {sym} [off] x ptr mem) -(VMINPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPS256load {sym} [off] x ptr mem) (VMINPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPS512load {sym} [off] x ptr mem) -(VMINPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPD128load {sym} [off] x ptr mem) -(VMINPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPD256load {sym} [off] x ptr mem) (VMINPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMINPD512load {sym} [off] x ptr mem) -(VPMINSD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSD128load {sym} [off] x ptr mem) -(VPMINSD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSD256load {sym} [off] x ptr mem) (VPMINSD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSD512load {sym} [off] x ptr mem) (VPMINSQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSQ128load {sym} [off] x ptr mem) (VPMINSQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSQ256load {sym} [off] x ptr mem) (VPMINSQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINSQ512load {sym} [off] x ptr mem) -(VPMINUD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUD128load {sym} [off] x ptr mem) -(VPMINUD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUD256load {sym} [off] x ptr mem) (VPMINUD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUD512load {sym} [off] x ptr mem) (VPMINUQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUQ128load {sym} [off] x ptr mem) (VPMINUQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMINUQ256load {sym} [off] x ptr mem) @@ -1689,14 +1629,8 @@ (VPMINUQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUQMasked128load {sym} [off] x ptr mask mem) (VPMINUQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUQMasked256load {sym} [off] x ptr mask mem) (VPMINUQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPMINUQMasked512load {sym} [off] x ptr mask mem) -(VMULPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPS128load {sym} [off] x ptr mem) -(VMULPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPS256load {sym} [off] x ptr mem) (VMULPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPS512load {sym} [off] x ptr mem) -(VMULPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPD128load {sym} [off] x ptr mem) -(VMULPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPD256load {sym} [off] x ptr mem) (VMULPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VMULPD512load {sym} [off] x ptr mem) -(VPMULLD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLD128load {sym} [off] x ptr mem) -(VPMULLD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLD256load {sym} [off] x ptr mem) (VPMULLD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLD512load {sym} [off] x ptr mem) (VPMULLQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLQ128load {sym} [off] x ptr mem) (VPMULLQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULLQ256load {sym} [off] x ptr mem) @@ -1725,10 +1659,6 @@ (VFMADDSUB213PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PDMasked128load {sym} [off] x y ptr mask mem) (VFMADDSUB213PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PDMasked256load {sym} [off] x y ptr mask mem) (VFMADDSUB213PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VFMADDSUB213PDMasked512load {sym} [off] x y ptr mask mem) -(VPMULDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULDQ128load {sym} [off] x ptr mem) -(VPMULDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULDQ256load {sym} [off] x ptr mem) -(VPMULUDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULUDQ128load {sym} [off] x ptr mem) -(VPMULUDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPMULUDQ256load {sym} [off] x ptr mem) (VMULPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPSMasked128load {sym} [off] x ptr mask mem) (VMULPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPSMasked256load {sym} [off] x ptr mask mem) (VMULPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VMULPSMasked512load {sym} [off] x ptr mask mem) @@ -1773,8 +1703,6 @@ (VPORQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORQMasked128load {sym} [off] x ptr mask mem) (VPORQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORQMasked256load {sym} [off] x ptr mask mem) (VPORQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPORQMasked512load {sym} [off] x ptr mask mem) -(VPERMPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMPS256load {sym} [off] x ptr mem) -(VPERMD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMD256load {sym} [off] x ptr mem) (VPERMPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMPS512load {sym} [off] x ptr mem) (VPERMD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMD512load {sym} [off] x ptr mem) (VPERMPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPERMPD256load {sym} [off] x ptr mem) @@ -1869,11 +1797,7 @@ (VSCALEFPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPDMasked128load {sym} [off] x ptr mask mem) (VSCALEFPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPDMasked256load {sym} [off] x ptr mask mem) (VSCALEFPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSCALEFPDMasked512load {sym} [off] x ptr mask mem) -(VPSLLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVD128load {sym} [off] x ptr mem) -(VPSLLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVD256load {sym} [off] x ptr mem) (VPSLLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVD512load {sym} [off] x ptr mem) -(VPSLLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQ128load {sym} [off] x ptr mem) -(VPSLLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQ256load {sym} [off] x ptr mem) (VPSLLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQ512load {sym} [off] x ptr mem) (VPSHLDVD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVD128load {sym} [off] x y ptr mem) (VPSHLDVD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHLDVD256load {sym} [off] x y ptr mem) @@ -1893,17 +1817,11 @@ (VPSLLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQMasked128load {sym} [off] x ptr mask mem) (VPSLLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQMasked256load {sym} [off] x ptr mask mem) (VPSLLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSLLVQMasked512load {sym} [off] x ptr mask mem) -(VPSRAVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVD128load {sym} [off] x ptr mem) -(VPSRAVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVD256load {sym} [off] x ptr mem) (VPSRAVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVD512load {sym} [off] x ptr mem) (VPSRAVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQ128load {sym} [off] x ptr mem) (VPSRAVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQ256load {sym} [off] x ptr mem) (VPSRAVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRAVQ512load {sym} [off] x ptr mem) -(VPSRLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVD128load {sym} [off] x ptr mem) -(VPSRLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVD256load {sym} [off] x ptr mem) (VPSRLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVD512load {sym} [off] x ptr mem) -(VPSRLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQ128load {sym} [off] x ptr mem) -(VPSRLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQ256load {sym} [off] x ptr mem) (VPSRLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQ512load {sym} [off] x ptr mem) (VPSHRDVD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVD128load {sym} [off] x y ptr mem) (VPSHRDVD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSHRDVD256load {sym} [off] x y ptr mem) @@ -1929,11 +1847,7 @@ (VPSRLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQMasked128load {sym} [off] x ptr mask mem) (VPSRLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQMasked256load {sym} [off] x ptr mask mem) (VPSRLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPSRLVQMasked512load {sym} [off] x ptr mask mem) -(VSQRTPS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPS128load {sym} [off] ptr mem) -(VSQRTPS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPS256load {sym} [off] ptr mem) (VSQRTPS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPS512load {sym} [off] ptr mem) -(VSQRTPD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPD128load {sym} [off] ptr mem) -(VSQRTPD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPD256load {sym} [off] ptr mem) (VSQRTPD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSQRTPD512load {sym} [off] ptr mem) (VSQRTPSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPSMasked128load {sym} [off] ptr mask mem) (VSQRTPSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPSMasked256load {sym} [off] ptr mask mem) @@ -1941,17 +1855,9 @@ (VSQRTPDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPDMasked128load {sym} [off] ptr mask mem) (VSQRTPDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPDMasked256load {sym} [off] ptr mask mem) (VSQRTPDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSQRTPDMasked512load {sym} [off] ptr mask mem) -(VSUBPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPS128load {sym} [off] x ptr mem) -(VSUBPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPS256load {sym} [off] x ptr mem) (VSUBPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPS512load {sym} [off] x ptr mem) -(VSUBPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPD128load {sym} [off] x ptr mem) -(VSUBPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPD256load {sym} [off] x ptr mem) (VSUBPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VSUBPD512load {sym} [off] x ptr mem) -(VPSUBD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBD128load {sym} [off] x ptr mem) -(VPSUBD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBD256load {sym} [off] x ptr mem) (VPSUBD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBD512load {sym} [off] x ptr mem) -(VPSUBQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBQ128load {sym} [off] x ptr mem) -(VPSUBQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBQ256load {sym} [off] x ptr mem) (VPSUBQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VPSUBQ512load {sym} [off] x ptr mem) (VSUBPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPSMasked128load {sym} [off] x ptr mask mem) (VSUBPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VSUBPSMasked256load {sym} [off] x ptr mask mem) diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go index 11f485c4e03..b9f0b866a02 100644 --- a/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go +++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go @@ -1310,8 +1310,6 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VPSRAQMasked128const", argLength: 2, reg: wkw, asm: "VPSRAQ", aux: "UInt8", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPSRAQMasked256const", argLength: 2, reg: wkw, asm: "VPSRAQ", aux: "UInt8", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPSRAQMasked512const", argLength: 2, reg: wkw, asm: "VPSRAQ", aux: "UInt8", commutative: false, typ: "Vec512", resultInArg0: false}, - {name: "VPABSD128load", argLength: 2, reg: v11load, asm: "VPABSD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPABSD256load", argLength: 2, reg: v11load, asm: "VPABSD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPABSD512load", argLength: 2, reg: w11load, asm: "VPABSD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPABSQ128load", argLength: 2, reg: w11load, asm: "VPABSQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPABSQ256load", argLength: 2, reg: w11load, asm: "VPABSQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, @@ -1322,38 +1320,22 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VPABSQMasked128load", argLength: 3, reg: wkwload, asm: "VPABSQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPABSQMasked256load", argLength: 3, reg: wkwload, asm: "VPABSQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPABSQMasked512load", argLength: 3, reg: wkwload, asm: "VPABSQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VADDPS128load", argLength: 3, reg: v21load, asm: "VADDPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VADDPS256load", argLength: 3, reg: v21load, asm: "VADDPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VADDPS512load", argLength: 3, reg: w21load, asm: "VADDPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VADDPD128load", argLength: 3, reg: v21load, asm: "VADDPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VADDPD256load", argLength: 3, reg: v21load, asm: "VADDPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VADDPD512load", argLength: 3, reg: w21load, asm: "VADDPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPADDD128load", argLength: 3, reg: v21load, asm: "VPADDD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPADDD256load", argLength: 3, reg: v21load, asm: "VPADDD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPADDD512load", argLength: 3, reg: w21load, asm: "VPADDD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPADDQ128load", argLength: 3, reg: v21load, asm: "VPADDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPADDQ256load", argLength: 3, reg: v21load, asm: "VPADDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPADDQ512load", argLength: 3, reg: w21load, asm: "VPADDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPDPWSSD128load", argLength: 4, reg: v31load, asm: "VPDPWSSD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, - {name: "VPDPWSSD256load", argLength: 4, reg: v31load, asm: "VPDPWSSD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPWSSD512load", argLength: 4, reg: w31load, asm: "VPDPWSSD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPWSSDMasked128load", argLength: 5, reg: w3kwload, asm: "VPDPWSSD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPWSSDMasked256load", argLength: 5, reg: w3kwload, asm: "VPDPWSSD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPWSSDMasked512load", argLength: 5, reg: w3kwload, asm: "VPDPWSSD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, - {name: "VPDPWSSDS128load", argLength: 4, reg: v31load, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, - {name: "VPDPWSSDS256load", argLength: 4, reg: v31load, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPWSSDS512load", argLength: 4, reg: w31load, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPWSSDSMasked128load", argLength: 5, reg: w3kwload, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPWSSDSMasked256load", argLength: 5, reg: w3kwload, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPWSSDSMasked512load", argLength: 5, reg: w3kwload, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, - {name: "VPDPBUSD128load", argLength: 4, reg: v31load, asm: "VPDPBUSD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, - {name: "VPDPBUSD256load", argLength: 4, reg: v31load, asm: "VPDPBUSD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPBUSD512load", argLength: 4, reg: w31load, asm: "VPDPBUSD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPBUSDMasked128load", argLength: 5, reg: w3kwload, asm: "VPDPBUSD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPBUSDMasked256load", argLength: 5, reg: w3kwload, asm: "VPDPBUSD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPBUSDMasked512load", argLength: 5, reg: w3kwload, asm: "VPDPBUSD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, - {name: "VPDPBUSDS128load", argLength: 4, reg: v31load, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, - {name: "VPDPBUSDS256load", argLength: 4, reg: v31load, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPBUSDS512load", argLength: 4, reg: w31load, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPBUSDSMasked128load", argLength: 5, reg: w3kwload, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPDPBUSDSMasked256load", argLength: 5, reg: w3kwload, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, @@ -1386,20 +1368,14 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VPANDNQMasked128load", argLength: 4, reg: w2kwload, asm: "VPANDNQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPANDNQMasked256load", argLength: 4, reg: w2kwload, asm: "VPANDNQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPANDNQMasked512load", argLength: 4, reg: w2kwload, asm: "VPANDNQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPACKSSDW128load", argLength: 3, reg: v21load, asm: "VPACKSSDW", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPACKSSDW256load", argLength: 3, reg: v21load, asm: "VPACKSSDW", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPACKSSDW512load", argLength: 3, reg: w21load, asm: "VPACKSSDW", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPACKSSDWMasked128load", argLength: 4, reg: w2kwload, asm: "VPACKSSDW", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPACKSSDWMasked256load", argLength: 4, reg: w2kwload, asm: "VPACKSSDW", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPACKSSDWMasked512load", argLength: 4, reg: w2kwload, asm: "VPACKSSDW", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VCVTTPS2DQ128load", argLength: 2, reg: v11load, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VCVTTPS2DQ256load", argLength: 2, reg: v11load, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VCVTTPS2DQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VCVTTPS2DQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VCVTTPS2DQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VCVTTPS2DQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPACKUSDW128load", argLength: 3, reg: v21load, asm: "VPACKUSDW", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPACKUSDW256load", argLength: 3, reg: v21load, asm: "VPACKUSDW", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPACKUSDW512load", argLength: 3, reg: w21load, asm: "VPACKUSDW", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPACKUSDWMasked128load", argLength: 4, reg: w2kwload, asm: "VPACKUSDW", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPACKUSDWMasked256load", argLength: 4, reg: w2kwload, asm: "VPACKUSDW", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, @@ -1410,11 +1386,7 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VCVTPS2UDQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VCVTPS2UDQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VCVTPS2UDQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VDIVPS128load", argLength: 3, reg: v21load, asm: "VDIVPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VDIVPS256load", argLength: 3, reg: v21load, asm: "VDIVPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VDIVPS512load", argLength: 3, reg: w21load, asm: "VDIVPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VDIVPD128load", argLength: 3, reg: v21load, asm: "VDIVPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VDIVPD256load", argLength: 3, reg: v21load, asm: "VDIVPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VDIVPD512load", argLength: 3, reg: w21load, asm: "VDIVPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VDIVPSMasked128load", argLength: 4, reg: w2kwload, asm: "VDIVPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VDIVPSMasked256load", argLength: 4, reg: w2kwload, asm: "VDIVPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, @@ -1422,29 +1394,13 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VDIVPDMasked128load", argLength: 4, reg: w2kwload, asm: "VDIVPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VDIVPDMasked256load", argLength: 4, reg: w2kwload, asm: "VDIVPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VDIVPDMasked512load", argLength: 4, reg: w2kwload, asm: "VDIVPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPCMPEQD128load", argLength: 3, reg: v21load, asm: "VPCMPEQD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPCMPEQD256load", argLength: 3, reg: v21load, asm: "VPCMPEQD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPCMPEQD512load", argLength: 3, reg: w2kload, asm: "VPCMPEQD", commutative: false, typ: "Mask", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPCMPEQQ128load", argLength: 3, reg: v21load, asm: "VPCMPEQQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPCMPEQQ256load", argLength: 3, reg: v21load, asm: "VPCMPEQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPCMPEQQ512load", argLength: 3, reg: w2kload, asm: "VPCMPEQQ", commutative: false, typ: "Mask", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPCMPGTD128load", argLength: 3, reg: v21load, asm: "VPCMPGTD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPCMPGTD256load", argLength: 3, reg: v21load, asm: "VPCMPGTD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPCMPGTD512load", argLength: 3, reg: w2kload, asm: "VPCMPGTD", commutative: false, typ: "Mask", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPCMPGTQ128load", argLength: 3, reg: v21load, asm: "VPCMPGTQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPCMPGTQ256load", argLength: 3, reg: v21load, asm: "VPCMPGTQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPCMPGTQ512load", argLength: 3, reg: w2kload, asm: "VPCMPGTQ", commutative: false, typ: "Mask", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPUNPCKHDQ128load", argLength: 3, reg: v21load, asm: "VPUNPCKHDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPUNPCKHQDQ128load", argLength: 3, reg: v21load, asm: "VPUNPCKHQDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPUNPCKHDQ256load", argLength: 3, reg: v21load, asm: "VPUNPCKHDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPUNPCKHDQ512load", argLength: 3, reg: w21load, asm: "VPUNPCKHDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPUNPCKHQDQ256load", argLength: 3, reg: v21load, asm: "VPUNPCKHQDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPUNPCKHQDQ512load", argLength: 3, reg: w21load, asm: "VPUNPCKHQDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPUNPCKLDQ128load", argLength: 3, reg: v21load, asm: "VPUNPCKLDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPUNPCKLQDQ128load", argLength: 3, reg: v21load, asm: "VPUNPCKLQDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPUNPCKLDQ256load", argLength: 3, reg: v21load, asm: "VPUNPCKLDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPUNPCKLDQ512load", argLength: 3, reg: w21load, asm: "VPUNPCKLDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPUNPCKLQDQ256load", argLength: 3, reg: v21load, asm: "VPUNPCKLQDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPUNPCKLQDQ512load", argLength: 3, reg: w21load, asm: "VPUNPCKLQDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPLZCNTD128load", argLength: 2, reg: w11load, asm: "VPLZCNTD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPLZCNTD256load", argLength: 2, reg: w11load, asm: "VPLZCNTD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, @@ -1458,20 +1414,12 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VPLZCNTQMasked128load", argLength: 3, reg: wkwload, asm: "VPLZCNTQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPLZCNTQMasked256load", argLength: 3, reg: wkwload, asm: "VPLZCNTQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPLZCNTQMasked512load", argLength: 3, reg: wkwload, asm: "VPLZCNTQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VMAXPS128load", argLength: 3, reg: v21load, asm: "VMAXPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VMAXPS256load", argLength: 3, reg: v21load, asm: "VMAXPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VMAXPS512load", argLength: 3, reg: w21load, asm: "VMAXPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VMAXPD128load", argLength: 3, reg: v21load, asm: "VMAXPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VMAXPD256load", argLength: 3, reg: v21load, asm: "VMAXPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VMAXPD512load", argLength: 3, reg: w21load, asm: "VMAXPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPMAXSD128load", argLength: 3, reg: v21load, asm: "VPMAXSD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPMAXSD256load", argLength: 3, reg: v21load, asm: "VPMAXSD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMAXSD512load", argLength: 3, reg: w21load, asm: "VPMAXSD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMAXSQ128load", argLength: 3, reg: w21load, asm: "VPMAXSQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMAXSQ256load", argLength: 3, reg: w21load, asm: "VPMAXSQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMAXSQ512load", argLength: 3, reg: w21load, asm: "VPMAXSQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPMAXUD128load", argLength: 3, reg: v21load, asm: "VPMAXUD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPMAXUD256load", argLength: 3, reg: v21load, asm: "VPMAXUD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMAXUD512load", argLength: 3, reg: w21load, asm: "VPMAXUD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMAXUQ128load", argLength: 3, reg: w21load, asm: "VPMAXUQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMAXUQ256load", argLength: 3, reg: w21load, asm: "VPMAXUQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, @@ -1494,20 +1442,12 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VPMAXUQMasked128load", argLength: 4, reg: w2kwload, asm: "VPMAXUQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMAXUQMasked256load", argLength: 4, reg: w2kwload, asm: "VPMAXUQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMAXUQMasked512load", argLength: 4, reg: w2kwload, asm: "VPMAXUQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VMINPS128load", argLength: 3, reg: v21load, asm: "VMINPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VMINPS256load", argLength: 3, reg: v21load, asm: "VMINPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VMINPS512load", argLength: 3, reg: w21load, asm: "VMINPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VMINPD128load", argLength: 3, reg: v21load, asm: "VMINPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VMINPD256load", argLength: 3, reg: v21load, asm: "VMINPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VMINPD512load", argLength: 3, reg: w21load, asm: "VMINPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPMINSD128load", argLength: 3, reg: v21load, asm: "VPMINSD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPMINSD256load", argLength: 3, reg: v21load, asm: "VPMINSD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMINSD512load", argLength: 3, reg: w21load, asm: "VPMINSD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMINSQ128load", argLength: 3, reg: w21load, asm: "VPMINSQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMINSQ256load", argLength: 3, reg: w21load, asm: "VPMINSQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMINSQ512load", argLength: 3, reg: w21load, asm: "VPMINSQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPMINUD128load", argLength: 3, reg: v21load, asm: "VPMINUD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPMINUD256load", argLength: 3, reg: v21load, asm: "VPMINUD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMINUD512load", argLength: 3, reg: w21load, asm: "VPMINUD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMINUQ128load", argLength: 3, reg: w21load, asm: "VPMINUQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMINUQ256load", argLength: 3, reg: w21load, asm: "VPMINUQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, @@ -1530,14 +1470,8 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VPMINUQMasked128load", argLength: 4, reg: w2kwload, asm: "VPMINUQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMINUQMasked256load", argLength: 4, reg: w2kwload, asm: "VPMINUQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMINUQMasked512load", argLength: 4, reg: w2kwload, asm: "VPMINUQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VMULPS128load", argLength: 3, reg: v21load, asm: "VMULPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VMULPS256load", argLength: 3, reg: v21load, asm: "VMULPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VMULPS512load", argLength: 3, reg: w21load, asm: "VMULPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VMULPD128load", argLength: 3, reg: v21load, asm: "VMULPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VMULPD256load", argLength: 3, reg: v21load, asm: "VMULPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VMULPD512load", argLength: 3, reg: w21load, asm: "VMULPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPMULLD128load", argLength: 3, reg: v21load, asm: "VPMULLD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPMULLD256load", argLength: 3, reg: v21load, asm: "VPMULLD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMULLD512load", argLength: 3, reg: w21load, asm: "VPMULLD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMULLQ128load", argLength: 3, reg: w21load, asm: "VPMULLQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPMULLQ256load", argLength: 3, reg: w21load, asm: "VPMULLQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, @@ -1566,10 +1500,6 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VFMADDSUB213PDMasked128load", argLength: 5, reg: w3kwload, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VFMADDSUB213PDMasked256load", argLength: 5, reg: w3kwload, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VFMADDSUB213PDMasked512load", argLength: 5, reg: w3kwload, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: true}, - {name: "VPMULDQ128load", argLength: 3, reg: v21load, asm: "VPMULDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPMULDQ256load", argLength: 3, reg: v21load, asm: "VPMULDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPMULUDQ128load", argLength: 3, reg: v21load, asm: "VPMULUDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPMULUDQ256load", argLength: 3, reg: v21load, asm: "VPMULUDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VMULPSMasked128load", argLength: 4, reg: w2kwload, asm: "VMULPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VMULPSMasked256load", argLength: 4, reg: w2kwload, asm: "VMULPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VMULPSMasked512load", argLength: 4, reg: w2kwload, asm: "VMULPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, @@ -1614,8 +1544,6 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VPORQMasked128load", argLength: 4, reg: w2kwload, asm: "VPORQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPORQMasked256load", argLength: 4, reg: w2kwload, asm: "VPORQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPORQMasked512load", argLength: 4, reg: w2kwload, asm: "VPORQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPERMPS256load", argLength: 3, reg: v21load, asm: "VPERMPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPERMD256load", argLength: 3, reg: v21load, asm: "VPERMD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPERMPS512load", argLength: 3, reg: w21load, asm: "VPERMPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPERMD512load", argLength: 3, reg: w21load, asm: "VPERMD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPERMPD256load", argLength: 3, reg: w21load, asm: "VPERMPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, @@ -1710,11 +1638,7 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VSCALEFPDMasked128load", argLength: 4, reg: w2kwload, asm: "VSCALEFPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VSCALEFPDMasked256load", argLength: 4, reg: w2kwload, asm: "VSCALEFPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VSCALEFPDMasked512load", argLength: 4, reg: w2kwload, asm: "VSCALEFPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSLLVD128load", argLength: 3, reg: v21load, asm: "VPSLLVD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSLLVD256load", argLength: 3, reg: v21load, asm: "VPSLLVD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSLLVD512load", argLength: 3, reg: w21load, asm: "VPSLLVD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSLLVQ128load", argLength: 3, reg: v21load, asm: "VPSLLVQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSLLVQ256load", argLength: 3, reg: v21load, asm: "VPSLLVQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSLLVQ512load", argLength: 3, reg: w21load, asm: "VPSLLVQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSHLDVD128load", argLength: 4, reg: w31load, asm: "VPSHLDVD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPSHLDVD256load", argLength: 4, reg: w31load, asm: "VPSHLDVD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, @@ -1734,17 +1658,11 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VPSLLVQMasked128load", argLength: 4, reg: w2kwload, asm: "VPSLLVQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSLLVQMasked256load", argLength: 4, reg: w2kwload, asm: "VPSLLVQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSLLVQMasked512load", argLength: 4, reg: w2kwload, asm: "VPSLLVQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSRAVD128load", argLength: 3, reg: v21load, asm: "VPSRAVD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSRAVD256load", argLength: 3, reg: v21load, asm: "VPSRAVD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSRAVD512load", argLength: 3, reg: w21load, asm: "VPSRAVD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSRAVQ128load", argLength: 3, reg: w21load, asm: "VPSRAVQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSRAVQ256load", argLength: 3, reg: w21load, asm: "VPSRAVQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSRAVQ512load", argLength: 3, reg: w21load, asm: "VPSRAVQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSRLVD128load", argLength: 3, reg: v21load, asm: "VPSRLVD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSRLVD256load", argLength: 3, reg: v21load, asm: "VPSRLVD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSRLVD512load", argLength: 3, reg: w21load, asm: "VPSRLVD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSRLVQ128load", argLength: 3, reg: v21load, asm: "VPSRLVQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSRLVQ256load", argLength: 3, reg: v21load, asm: "VPSRLVQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSRLVQ512load", argLength: 3, reg: w21load, asm: "VPSRLVQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSHRDVD128load", argLength: 4, reg: w31load, asm: "VPSHRDVD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: true}, {name: "VPSHRDVD256load", argLength: 4, reg: w31load, asm: "VPSHRDVD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: true}, @@ -1770,11 +1688,7 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VPSRLVQMasked128load", argLength: 4, reg: w2kwload, asm: "VPSRLVQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSRLVQMasked256load", argLength: 4, reg: w2kwload, asm: "VPSRLVQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSRLVQMasked512load", argLength: 4, reg: w2kwload, asm: "VPSRLVQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VSQRTPS128load", argLength: 2, reg: v11load, asm: "VSQRTPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VSQRTPS256load", argLength: 2, reg: v11load, asm: "VSQRTPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VSQRTPS512load", argLength: 2, reg: w11load, asm: "VSQRTPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VSQRTPD128load", argLength: 2, reg: v11load, asm: "VSQRTPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VSQRTPD256load", argLength: 2, reg: v11load, asm: "VSQRTPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VSQRTPD512load", argLength: 2, reg: w11load, asm: "VSQRTPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VSQRTPSMasked128load", argLength: 3, reg: wkwload, asm: "VSQRTPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VSQRTPSMasked256load", argLength: 3, reg: wkwload, asm: "VSQRTPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, @@ -1782,17 +1696,9 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VSQRTPDMasked128load", argLength: 3, reg: wkwload, asm: "VSQRTPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VSQRTPDMasked256load", argLength: 3, reg: wkwload, asm: "VSQRTPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VSQRTPDMasked512load", argLength: 3, reg: wkwload, asm: "VSQRTPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VSUBPS128load", argLength: 3, reg: v21load, asm: "VSUBPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VSUBPS256load", argLength: 3, reg: v21load, asm: "VSUBPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VSUBPS512load", argLength: 3, reg: w21load, asm: "VSUBPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VSUBPD128load", argLength: 3, reg: v21load, asm: "VSUBPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VSUBPD256load", argLength: 3, reg: v21load, asm: "VSUBPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VSUBPD512load", argLength: 3, reg: w21load, asm: "VSUBPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSUBD128load", argLength: 3, reg: v21load, asm: "VPSUBD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSUBD256load", argLength: 3, reg: v21load, asm: "VPSUBD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSUBD512load", argLength: 3, reg: w21load, asm: "VPSUBD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSUBQ128load", argLength: 3, reg: v21load, asm: "VPSUBQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSUBQ256load", argLength: 3, reg: v21load, asm: "VPSUBQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VPSUBQ512load", argLength: 3, reg: w21load, asm: "VPSUBQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VSUBPSMasked128load", argLength: 4, reg: w2kwload, asm: "VSUBPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false}, {name: "VSUBPSMasked256load", argLength: 4, reg: w2kwload, asm: "VSUBPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false}, @@ -1840,11 +1746,7 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VREDUCEPDMasked128load", argLength: 3, reg: wkwload, asm: "VREDUCEPD", commutative: false, typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VREDUCEPDMasked256load", argLength: 3, reg: wkwload, asm: "VREDUCEPD", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VREDUCEPDMasked512load", argLength: 3, reg: wkwload, asm: "VREDUCEPD", commutative: false, typ: "Vec512", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VCMPPS128load", argLength: 3, reg: v21load, asm: "VCMPPS", commutative: false, typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VCMPPS256load", argLength: 3, reg: v21load, asm: "VCMPPS", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VCMPPS512load", argLength: 3, reg: w2kload, asm: "VCMPPS", commutative: false, typ: "Mask", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VCMPPD128load", argLength: 3, reg: v21load, asm: "VCMPPD", commutative: false, typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VCMPPD256load", argLength: 3, reg: v21load, asm: "VCMPPD", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VCMPPD512load", argLength: 3, reg: w2kload, asm: "VCMPPD", commutative: false, typ: "Mask", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VCMPPSMasked128load", argLength: 4, reg: w2kkload, asm: "VCMPPS", commutative: false, typ: "Mask", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VCMPPSMasked256load", argLength: 4, reg: w2kkload, asm: "VCMPPS", commutative: false, typ: "Mask", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, @@ -1880,8 +1782,6 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VPCMPUQ512load", argLength: 3, reg: w2kload, asm: "VPCMPUQ", commutative: false, typ: "Mask", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPCMPD512load", argLength: 3, reg: w2kload, asm: "VPCMPD", commutative: false, typ: "Mask", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPCMPQ512load", argLength: 3, reg: w2kload, asm: "VPCMPQ", commutative: false, typ: "Mask", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSHUFD128load", argLength: 2, reg: v11load, asm: "VPSHUFD", commutative: false, typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSHUFD256load", argLength: 2, reg: v11load, asm: "VPSHUFD", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSHUFD512load", argLength: 2, reg: w11load, asm: "VPSHUFD", commutative: false, typ: "Vec512", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSHUFDMasked256load", argLength: 3, reg: wkwload, asm: "VPSHUFD", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSHUFDMasked512load", argLength: 3, reg: wkwload, asm: "VPSHUFD", commutative: false, typ: "Vec512", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, @@ -1934,11 +1834,7 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VPSHRDQMasked128load", argLength: 4, reg: w2kwload, asm: "VPSHRDQ", commutative: false, typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSHRDQMasked256load", argLength: 4, reg: w2kwload, asm: "VPSHRDQ", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSHRDQMasked512load", argLength: 4, reg: w2kwload, asm: "VPSHRDQ", commutative: false, typ: "Vec512", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSLLD128constload", argLength: 2, reg: v11load, asm: "VPSLLD", commutative: false, typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSLLD256constload", argLength: 2, reg: v11load, asm: "VPSLLD", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSLLD512constload", argLength: 2, reg: w11load, asm: "VPSLLD", commutative: false, typ: "Vec512", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSLLQ128constload", argLength: 2, reg: v11load, asm: "VPSLLQ", commutative: false, typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSLLQ256constload", argLength: 2, reg: v11load, asm: "VPSLLQ", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSLLQ512constload", argLength: 2, reg: w11load, asm: "VPSLLQ", commutative: false, typ: "Vec512", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSLLDMasked128constload", argLength: 3, reg: wkwload, asm: "VPSLLD", commutative: false, typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSLLDMasked256constload", argLength: 3, reg: wkwload, asm: "VPSLLD", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, @@ -1946,14 +1842,8 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf {name: "VPSLLQMasked128constload", argLength: 3, reg: wkwload, asm: "VPSLLQ", commutative: false, typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSLLQMasked256constload", argLength: 3, reg: wkwload, asm: "VPSLLQ", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSLLQMasked512constload", argLength: 3, reg: wkwload, asm: "VPSLLQ", commutative: false, typ: "Vec512", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSRLD128constload", argLength: 2, reg: v11load, asm: "VPSRLD", commutative: false, typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSRLD256constload", argLength: 2, reg: v11load, asm: "VPSRLD", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSRLD512constload", argLength: 2, reg: w11load, asm: "VPSRLD", commutative: false, typ: "Vec512", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSRLQ128constload", argLength: 2, reg: v11load, asm: "VPSRLQ", commutative: false, typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSRLQ256constload", argLength: 2, reg: v11load, asm: "VPSRLQ", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSRLQ512constload", argLength: 2, reg: w11load, asm: "VPSRLQ", commutative: false, typ: "Vec512", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSRAD128constload", argLength: 2, reg: v11load, asm: "VPSRAD", commutative: false, typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, - {name: "VPSRAD256constload", argLength: 2, reg: v11load, asm: "VPSRAD", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSRAD512constload", argLength: 2, reg: w11load, asm: "VPSRAD", commutative: false, typ: "Vec512", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSRAQ128constload", argLength: 2, reg: w11load, asm: "VPSRAQ", commutative: false, typ: "Vec128", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, {name: "VPSRAQ256constload", argLength: 2, reg: w11load, asm: "VPSRAQ", commutative: false, typ: "Vec256", aux: "SymValAndOff", symEffect: "Read", resultInArg0: false}, diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go index 77bac7734ae..1d2dc46895f 100644 --- a/src/cmd/compile/internal/ssa/opGen.go +++ b/src/cmd/compile/internal/ssa/opGen.go @@ -2541,8 +2541,6 @@ const ( OpAMD64VPSRAQMasked128const OpAMD64VPSRAQMasked256const OpAMD64VPSRAQMasked512const - OpAMD64VPABSD128load - OpAMD64VPABSD256load OpAMD64VPABSD512load OpAMD64VPABSQ128load OpAMD64VPABSQ256load @@ -2553,38 +2551,22 @@ const ( OpAMD64VPABSQMasked128load OpAMD64VPABSQMasked256load OpAMD64VPABSQMasked512load - OpAMD64VADDPS128load - OpAMD64VADDPS256load OpAMD64VADDPS512load - OpAMD64VADDPD128load - OpAMD64VADDPD256load OpAMD64VADDPD512load - OpAMD64VPADDD128load - OpAMD64VPADDD256load OpAMD64VPADDD512load - OpAMD64VPADDQ128load - OpAMD64VPADDQ256load OpAMD64VPADDQ512load - OpAMD64VPDPWSSD128load - OpAMD64VPDPWSSD256load OpAMD64VPDPWSSD512load OpAMD64VPDPWSSDMasked128load OpAMD64VPDPWSSDMasked256load OpAMD64VPDPWSSDMasked512load - OpAMD64VPDPWSSDS128load - OpAMD64VPDPWSSDS256load OpAMD64VPDPWSSDS512load OpAMD64VPDPWSSDSMasked128load OpAMD64VPDPWSSDSMasked256load OpAMD64VPDPWSSDSMasked512load - OpAMD64VPDPBUSD128load - OpAMD64VPDPBUSD256load OpAMD64VPDPBUSD512load OpAMD64VPDPBUSDMasked128load OpAMD64VPDPBUSDMasked256load OpAMD64VPDPBUSDMasked512load - OpAMD64VPDPBUSDS128load - OpAMD64VPDPBUSDS256load OpAMD64VPDPBUSDS512load OpAMD64VPDPBUSDSMasked128load OpAMD64VPDPBUSDSMasked256load @@ -2617,20 +2599,14 @@ const ( OpAMD64VPANDNQMasked128load OpAMD64VPANDNQMasked256load OpAMD64VPANDNQMasked512load - OpAMD64VPACKSSDW128load - OpAMD64VPACKSSDW256load OpAMD64VPACKSSDW512load OpAMD64VPACKSSDWMasked128load OpAMD64VPACKSSDWMasked256load OpAMD64VPACKSSDWMasked512load - OpAMD64VCVTTPS2DQ128load - OpAMD64VCVTTPS2DQ256load OpAMD64VCVTTPS2DQ512load OpAMD64VCVTTPS2DQMasked128load OpAMD64VCVTTPS2DQMasked256load OpAMD64VCVTTPS2DQMasked512load - OpAMD64VPACKUSDW128load - OpAMD64VPACKUSDW256load OpAMD64VPACKUSDW512load OpAMD64VPACKUSDWMasked128load OpAMD64VPACKUSDWMasked256load @@ -2641,11 +2617,7 @@ const ( OpAMD64VCVTPS2UDQMasked128load OpAMD64VCVTPS2UDQMasked256load OpAMD64VCVTPS2UDQMasked512load - OpAMD64VDIVPS128load - OpAMD64VDIVPS256load OpAMD64VDIVPS512load - OpAMD64VDIVPD128load - OpAMD64VDIVPD256load OpAMD64VDIVPD512load OpAMD64VDIVPSMasked128load OpAMD64VDIVPSMasked256load @@ -2653,29 +2625,13 @@ const ( OpAMD64VDIVPDMasked128load OpAMD64VDIVPDMasked256load OpAMD64VDIVPDMasked512load - OpAMD64VPCMPEQD128load - OpAMD64VPCMPEQD256load OpAMD64VPCMPEQD512load - OpAMD64VPCMPEQQ128load - OpAMD64VPCMPEQQ256load OpAMD64VPCMPEQQ512load - OpAMD64VPCMPGTD128load - OpAMD64VPCMPGTD256load OpAMD64VPCMPGTD512load - OpAMD64VPCMPGTQ128load - OpAMD64VPCMPGTQ256load OpAMD64VPCMPGTQ512load - OpAMD64VPUNPCKHDQ128load - OpAMD64VPUNPCKHQDQ128load - OpAMD64VPUNPCKHDQ256load OpAMD64VPUNPCKHDQ512load - OpAMD64VPUNPCKHQDQ256load OpAMD64VPUNPCKHQDQ512load - OpAMD64VPUNPCKLDQ128load - OpAMD64VPUNPCKLQDQ128load - OpAMD64VPUNPCKLDQ256load OpAMD64VPUNPCKLDQ512load - OpAMD64VPUNPCKLQDQ256load OpAMD64VPUNPCKLQDQ512load OpAMD64VPLZCNTD128load OpAMD64VPLZCNTD256load @@ -2689,20 +2645,12 @@ const ( OpAMD64VPLZCNTQMasked128load OpAMD64VPLZCNTQMasked256load OpAMD64VPLZCNTQMasked512load - OpAMD64VMAXPS128load - OpAMD64VMAXPS256load OpAMD64VMAXPS512load - OpAMD64VMAXPD128load - OpAMD64VMAXPD256load OpAMD64VMAXPD512load - OpAMD64VPMAXSD128load - OpAMD64VPMAXSD256load OpAMD64VPMAXSD512load OpAMD64VPMAXSQ128load OpAMD64VPMAXSQ256load OpAMD64VPMAXSQ512load - OpAMD64VPMAXUD128load - OpAMD64VPMAXUD256load OpAMD64VPMAXUD512load OpAMD64VPMAXUQ128load OpAMD64VPMAXUQ256load @@ -2725,20 +2673,12 @@ const ( OpAMD64VPMAXUQMasked128load OpAMD64VPMAXUQMasked256load OpAMD64VPMAXUQMasked512load - OpAMD64VMINPS128load - OpAMD64VMINPS256load OpAMD64VMINPS512load - OpAMD64VMINPD128load - OpAMD64VMINPD256load OpAMD64VMINPD512load - OpAMD64VPMINSD128load - OpAMD64VPMINSD256load OpAMD64VPMINSD512load OpAMD64VPMINSQ128load OpAMD64VPMINSQ256load OpAMD64VPMINSQ512load - OpAMD64VPMINUD128load - OpAMD64VPMINUD256load OpAMD64VPMINUD512load OpAMD64VPMINUQ128load OpAMD64VPMINUQ256load @@ -2761,14 +2701,8 @@ const ( OpAMD64VPMINUQMasked128load OpAMD64VPMINUQMasked256load OpAMD64VPMINUQMasked512load - OpAMD64VMULPS128load - OpAMD64VMULPS256load OpAMD64VMULPS512load - OpAMD64VMULPD128load - OpAMD64VMULPD256load OpAMD64VMULPD512load - OpAMD64VPMULLD128load - OpAMD64VPMULLD256load OpAMD64VPMULLD512load OpAMD64VPMULLQ128load OpAMD64VPMULLQ256load @@ -2797,10 +2731,6 @@ const ( OpAMD64VFMADDSUB213PDMasked128load OpAMD64VFMADDSUB213PDMasked256load OpAMD64VFMADDSUB213PDMasked512load - OpAMD64VPMULDQ128load - OpAMD64VPMULDQ256load - OpAMD64VPMULUDQ128load - OpAMD64VPMULUDQ256load OpAMD64VMULPSMasked128load OpAMD64VMULPSMasked256load OpAMD64VMULPSMasked512load @@ -2845,8 +2775,6 @@ const ( OpAMD64VPORQMasked128load OpAMD64VPORQMasked256load OpAMD64VPORQMasked512load - OpAMD64VPERMPS256load - OpAMD64VPERMD256load OpAMD64VPERMPS512load OpAMD64VPERMD512load OpAMD64VPERMPD256load @@ -2941,11 +2869,7 @@ const ( OpAMD64VSCALEFPDMasked128load OpAMD64VSCALEFPDMasked256load OpAMD64VSCALEFPDMasked512load - OpAMD64VPSLLVD128load - OpAMD64VPSLLVD256load OpAMD64VPSLLVD512load - OpAMD64VPSLLVQ128load - OpAMD64VPSLLVQ256load OpAMD64VPSLLVQ512load OpAMD64VPSHLDVD128load OpAMD64VPSHLDVD256load @@ -2965,17 +2889,11 @@ const ( OpAMD64VPSLLVQMasked128load OpAMD64VPSLLVQMasked256load OpAMD64VPSLLVQMasked512load - OpAMD64VPSRAVD128load - OpAMD64VPSRAVD256load OpAMD64VPSRAVD512load OpAMD64VPSRAVQ128load OpAMD64VPSRAVQ256load OpAMD64VPSRAVQ512load - OpAMD64VPSRLVD128load - OpAMD64VPSRLVD256load OpAMD64VPSRLVD512load - OpAMD64VPSRLVQ128load - OpAMD64VPSRLVQ256load OpAMD64VPSRLVQ512load OpAMD64VPSHRDVD128load OpAMD64VPSHRDVD256load @@ -3001,11 +2919,7 @@ const ( OpAMD64VPSRLVQMasked128load OpAMD64VPSRLVQMasked256load OpAMD64VPSRLVQMasked512load - OpAMD64VSQRTPS128load - OpAMD64VSQRTPS256load OpAMD64VSQRTPS512load - OpAMD64VSQRTPD128load - OpAMD64VSQRTPD256load OpAMD64VSQRTPD512load OpAMD64VSQRTPSMasked128load OpAMD64VSQRTPSMasked256load @@ -3013,17 +2927,9 @@ const ( OpAMD64VSQRTPDMasked128load OpAMD64VSQRTPDMasked256load OpAMD64VSQRTPDMasked512load - OpAMD64VSUBPS128load - OpAMD64VSUBPS256load OpAMD64VSUBPS512load - OpAMD64VSUBPD128load - OpAMD64VSUBPD256load OpAMD64VSUBPD512load - OpAMD64VPSUBD128load - OpAMD64VPSUBD256load OpAMD64VPSUBD512load - OpAMD64VPSUBQ128load - OpAMD64VPSUBQ256load OpAMD64VPSUBQ512load OpAMD64VSUBPSMasked128load OpAMD64VSUBPSMasked256load @@ -3071,11 +2977,7 @@ const ( OpAMD64VREDUCEPDMasked128load OpAMD64VREDUCEPDMasked256load OpAMD64VREDUCEPDMasked512load - OpAMD64VCMPPS128load - OpAMD64VCMPPS256load OpAMD64VCMPPS512load - OpAMD64VCMPPD128load - OpAMD64VCMPPD256load OpAMD64VCMPPD512load OpAMD64VCMPPSMasked128load OpAMD64VCMPPSMasked256load @@ -3111,8 +3013,6 @@ const ( OpAMD64VPCMPUQ512load OpAMD64VPCMPD512load OpAMD64VPCMPQ512load - OpAMD64VPSHUFD128load - OpAMD64VPSHUFD256load OpAMD64VPSHUFD512load OpAMD64VPSHUFDMasked256load OpAMD64VPSHUFDMasked512load @@ -3165,11 +3065,7 @@ const ( OpAMD64VPSHRDQMasked128load OpAMD64VPSHRDQMasked256load OpAMD64VPSHRDQMasked512load - OpAMD64VPSLLD128constload - OpAMD64VPSLLD256constload OpAMD64VPSLLD512constload - OpAMD64VPSLLQ128constload - OpAMD64VPSLLQ256constload OpAMD64VPSLLQ512constload OpAMD64VPSLLDMasked128constload OpAMD64VPSLLDMasked256constload @@ -3177,14 +3073,8 @@ const ( OpAMD64VPSLLQMasked128constload OpAMD64VPSLLQMasked256constload OpAMD64VPSLLQMasked512constload - OpAMD64VPSRLD128constload - OpAMD64VPSRLD256constload OpAMD64VPSRLD512constload - OpAMD64VPSRLQ128constload - OpAMD64VPSRLQ256constload OpAMD64VPSRLQ512constload - OpAMD64VPSRAD128constload - OpAMD64VPSRAD256constload OpAMD64VPSRAD512constload OpAMD64VPSRAQ128constload OpAMD64VPSRAQ256constload @@ -39188,36 +39078,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPABSD128load", - auxType: auxSymOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPABSD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPABSD256load", - auxType: auxSymOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPABSD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPABSD512load", auxType: auxSymOff, @@ -39374,38 +39234,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VADDPS128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVADDPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VADDPS256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVADDPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VADDPS512load", auxType: auxSymOff, @@ -39422,38 +39250,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VADDPD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVADDPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VADDPD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVADDPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VADDPD512load", auxType: auxSymOff, @@ -39470,38 +39266,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPADDD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPADDD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPADDD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPADDD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPADDD512load", auxType: auxSymOff, @@ -39518,38 +39282,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPADDQ128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPADDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPADDQ256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPADDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPADDQ512load", auxType: auxSymOff, @@ -39566,42 +39298,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPDPWSSD128load", - auxType: auxSymOff, - argLen: 4, - resultInArg0: true, - symEffect: SymRead, - asm: x86.AVPDPWSSD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPDPWSSD256load", - auxType: auxSymOff, - argLen: 4, - resultInArg0: true, - symEffect: SymRead, - asm: x86.AVPDPWSSD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPDPWSSD512load", auxType: auxSymOff, @@ -39677,42 +39373,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPDPWSSDS128load", - auxType: auxSymOff, - argLen: 4, - resultInArg0: true, - symEffect: SymRead, - asm: x86.AVPDPWSSDS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPDPWSSDS256load", - auxType: auxSymOff, - argLen: 4, - resultInArg0: true, - symEffect: SymRead, - asm: x86.AVPDPWSSDS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPDPWSSDS512load", auxType: auxSymOff, @@ -39788,42 +39448,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPDPBUSD128load", - auxType: auxSymOff, - argLen: 4, - resultInArg0: true, - symEffect: SymRead, - asm: x86.AVPDPBUSD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPDPBUSD256load", - auxType: auxSymOff, - argLen: 4, - resultInArg0: true, - symEffect: SymRead, - asm: x86.AVPDPBUSD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPDPBUSD512load", auxType: auxSymOff, @@ -39899,42 +39523,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPDPBUSDS128load", - auxType: auxSymOff, - argLen: 4, - resultInArg0: true, - symEffect: SymRead, - asm: x86.AVPDPBUSDS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPDPBUSDS256load", - auxType: auxSymOff, - argLen: 4, - resultInArg0: true, - symEffect: SymRead, - asm: x86.AVPDPBUSDS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {2, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPDPBUSDS512load", auxType: auxSymOff, @@ -40482,38 +40070,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPACKSSDW128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPACKSSDW, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPACKSSDW256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPACKSSDW, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPACKSSDW512load", auxType: auxSymOff, @@ -40581,36 +40137,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VCVTTPS2DQ128load", - auxType: auxSymOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVCVTTPS2DQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VCVTTPS2DQ256load", - auxType: auxSymOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVCVTTPS2DQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VCVTTPS2DQ512load", auxType: auxSymOff, @@ -40674,38 +40200,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPACKUSDW128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPACKUSDW, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPACKUSDW256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPACKUSDW, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPACKUSDW512load", auxType: auxSymOff, @@ -40866,38 +40360,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VDIVPS128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVDIVPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VDIVPS256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVDIVPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VDIVPS512load", auxType: auxSymOff, @@ -40914,38 +40376,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VDIVPD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVDIVPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VDIVPD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVDIVPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VDIVPD512load", auxType: auxSymOff, @@ -41064,38 +40494,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPCMPEQD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPCMPEQD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPCMPEQD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPCMPEQD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPCMPEQD512load", auxType: auxSymOff, @@ -41112,38 +40510,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPCMPEQQ128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPCMPEQQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPCMPEQQ256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPCMPEQQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPCMPEQQ512load", auxType: auxSymOff, @@ -41160,38 +40526,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPCMPGTD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPCMPGTD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPCMPGTD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPCMPGTD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPCMPGTD512load", auxType: auxSymOff, @@ -41208,38 +40542,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPCMPGTQ128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPCMPGTQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPCMPGTQ256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPCMPGTQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPCMPGTQ512load", auxType: auxSymOff, @@ -41256,54 +40558,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPUNPCKHDQ128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPUNPCKHDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPUNPCKHQDQ128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPUNPCKHQDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPUNPCKHDQ256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPUNPCKHDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPUNPCKHDQ512load", auxType: auxSymOff, @@ -41320,22 +40574,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPUNPCKHQDQ256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPUNPCKHQDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPUNPCKHQDQ512load", auxType: auxSymOff, @@ -41352,54 +40590,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPUNPCKLDQ128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPUNPCKLDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPUNPCKLQDQ128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPUNPCKLQDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPUNPCKLDQ256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPUNPCKLDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPUNPCKLDQ512load", auxType: auxSymOff, @@ -41416,22 +40606,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPUNPCKLQDQ256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPUNPCKLQDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPUNPCKLQDQ512load", auxType: auxSymOff, @@ -41634,38 +40808,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VMAXPS128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVMAXPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VMAXPS256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVMAXPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VMAXPS512load", auxType: auxSymOff, @@ -41682,38 +40824,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VMAXPD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVMAXPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VMAXPD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVMAXPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VMAXPD512load", auxType: auxSymOff, @@ -41730,38 +40840,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPMAXSD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMAXSD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPMAXSD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMAXSD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPMAXSD512load", auxType: auxSymOff, @@ -41826,38 +40904,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPMAXUD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMAXUD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPMAXUD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMAXUD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPMAXUD512load", auxType: auxSymOff, @@ -42228,38 +41274,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VMINPS128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVMINPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VMINPS256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVMINPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VMINPS512load", auxType: auxSymOff, @@ -42276,38 +41290,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VMINPD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVMINPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VMINPD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVMINPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VMINPD512load", auxType: auxSymOff, @@ -42324,38 +41306,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPMINSD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMINSD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPMINSD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMINSD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPMINSD512load", auxType: auxSymOff, @@ -42420,38 +41370,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPMINUD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMINUD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPMINUD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMINUD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPMINUD512load", auxType: auxSymOff, @@ -42822,38 +41740,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VMULPS128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVMULPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VMULPS256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVMULPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VMULPS512load", auxType: auxSymOff, @@ -42870,38 +41756,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VMULPD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVMULPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VMULPD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVMULPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VMULPD512load", auxType: auxSymOff, @@ -42918,38 +41772,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPMULLD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMULLD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPMULLD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMULLD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPMULLD512load", auxType: auxSymOff, @@ -43458,70 +42280,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPMULDQ128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMULDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPMULDQ256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMULDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPMULUDQ128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMULUDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPMULUDQ256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPMULUDQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VMULPSMasked128load", auxType: auxSymOff, @@ -44268,38 +43026,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPERMPS256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPERMPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPERMD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPERMD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPERMPS512load", auxType: auxSymOff, @@ -45882,38 +44608,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPSLLVD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSLLVD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPSLLVD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSLLVD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPSLLVD512load", auxType: auxSymOff, @@ -45930,38 +44624,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPSLLVQ128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSLLVQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPSLLVQ256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSLLVQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPSLLVQ512load", auxType: auxSymOff, @@ -46302,38 +44964,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPSRAVD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSRAVD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPSRAVD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSRAVD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPSRAVD512load", auxType: auxSymOff, @@ -46398,38 +45028,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPSRLVD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSRLVD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPSRLVD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSRLVD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPSRLVD512load", auxType: auxSymOff, @@ -46446,38 +45044,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPSRLVQ128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSRLVQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPSRLVQ256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSRLVQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPSRLVQ512load", auxType: auxSymOff, @@ -46920,36 +45486,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VSQRTPS128load", - auxType: auxSymOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVSQRTPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VSQRTPS256load", - auxType: auxSymOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVSQRTPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VSQRTPS512load", auxType: auxSymOff, @@ -46965,36 +45501,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VSQRTPD128load", - auxType: auxSymOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVSQRTPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VSQRTPD256load", - auxType: auxSymOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVSQRTPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VSQRTPD512load", auxType: auxSymOff, @@ -47106,38 +45612,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VSUBPS128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVSUBPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VSUBPS256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVSUBPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VSUBPS512load", auxType: auxSymOff, @@ -47154,38 +45628,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VSUBPD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVSUBPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VSUBPD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVSUBPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VSUBPD512load", auxType: auxSymOff, @@ -47202,38 +45644,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPSUBD128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSUBD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPSUBD256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSUBD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPSUBD512load", auxType: auxSymOff, @@ -47250,38 +45660,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPSUBQ128load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSUBQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPSUBQ256load", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVPSUBQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPSUBQ512load", auxType: auxSymOff, @@ -48042,38 +46420,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VCMPPS128load", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVCMPPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VCMPPS256load", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVCMPPS, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VCMPPS512load", auxType: auxSymValAndOff, @@ -48090,38 +46436,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VCMPPD128load", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVCMPPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VCMPPD256load", - auxType: auxSymValAndOff, - argLen: 3, - symEffect: SymRead, - asm: x86.AVCMPPD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 - {1, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VCMPPD512load", auxType: auxSymValAndOff, @@ -48706,36 +47020,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPSHUFD128load", - auxType: auxSymValAndOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPSHUFD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPSHUFD256load", - auxType: auxSymValAndOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPSHUFD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPSHUFD512load", auxType: auxSymValAndOff, @@ -49567,36 +47851,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPSLLD128constload", - auxType: auxSymValAndOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPSLLD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPSLLD256constload", - auxType: auxSymValAndOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPSLLD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPSLLD512constload", auxType: auxSymValAndOff, @@ -49612,36 +47866,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPSLLQ128constload", - auxType: auxSymValAndOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPSLLQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPSLLQ256constload", - auxType: auxSymValAndOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPSLLQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPSLLQ512constload", auxType: auxSymValAndOff, @@ -49753,36 +47977,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPSRLD128constload", - auxType: auxSymValAndOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPSRLD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPSRLD256constload", - auxType: auxSymValAndOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPSRLD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPSRLD512constload", auxType: auxSymValAndOff, @@ -49798,36 +47992,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPSRLQ128constload", - auxType: auxSymValAndOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPSRLQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPSRLQ256constload", - auxType: auxSymValAndOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPSRLQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPSRLQ512constload", auxType: auxSymValAndOff, @@ -49843,36 +48007,6 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "VPSRAD128constload", - auxType: auxSymValAndOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPSRAD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, - { - name: "VPSRAD256constload", - auxType: auxSymValAndOff, - argLen: 2, - symEffect: SymRead, - asm: x86.AVPSRAD, - reg: regInfo{ - inputs: []inputInfo{ - {0, 72057594037977087}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - }, - outputs: []outputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - }, - }, - }, { name: "VPSRAD512constload", auxType: auxSymValAndOff, diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go index 187b3ed9d64..471fa0c201e 100644 --- a/src/cmd/compile/internal/ssa/rewriteAMD64.go +++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go @@ -507,10 +507,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64TESTW(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst(v) - case OpAMD64VADDPD128: - return rewriteValueAMD64_OpAMD64VADDPD128(v) - case OpAMD64VADDPD256: - return rewriteValueAMD64_OpAMD64VADDPD256(v) case OpAMD64VADDPD512: return rewriteValueAMD64_OpAMD64VADDPD512(v) case OpAMD64VADDPDMasked128: @@ -519,10 +515,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VADDPDMasked256(v) case OpAMD64VADDPDMasked512: return rewriteValueAMD64_OpAMD64VADDPDMasked512(v) - case OpAMD64VADDPS128: - return rewriteValueAMD64_OpAMD64VADDPS128(v) - case OpAMD64VADDPS256: - return rewriteValueAMD64_OpAMD64VADDPS256(v) case OpAMD64VADDPS512: return rewriteValueAMD64_OpAMD64VADDPS512(v) case OpAMD64VADDPSMasked128: @@ -543,10 +535,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked256(v) case OpAMD64VCVTPS2UDQMasked512: return rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked512(v) - case OpAMD64VCVTTPS2DQ128: - return rewriteValueAMD64_OpAMD64VCVTTPS2DQ128(v) - case OpAMD64VCVTTPS2DQ256: - return rewriteValueAMD64_OpAMD64VCVTTPS2DQ256(v) case OpAMD64VCVTTPS2DQ512: return rewriteValueAMD64_OpAMD64VCVTTPS2DQ512(v) case OpAMD64VCVTTPS2DQMasked128: @@ -555,10 +543,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VCVTTPS2DQMasked256(v) case OpAMD64VCVTTPS2DQMasked512: return rewriteValueAMD64_OpAMD64VCVTTPS2DQMasked512(v) - case OpAMD64VDIVPD128: - return rewriteValueAMD64_OpAMD64VDIVPD128(v) - case OpAMD64VDIVPD256: - return rewriteValueAMD64_OpAMD64VDIVPD256(v) case OpAMD64VDIVPD512: return rewriteValueAMD64_OpAMD64VDIVPD512(v) case OpAMD64VDIVPDMasked128: @@ -567,10 +551,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VDIVPDMasked256(v) case OpAMD64VDIVPDMasked512: return rewriteValueAMD64_OpAMD64VDIVPDMasked512(v) - case OpAMD64VDIVPS128: - return rewriteValueAMD64_OpAMD64VDIVPS128(v) - case OpAMD64VDIVPS256: - return rewriteValueAMD64_OpAMD64VDIVPS256(v) case OpAMD64VDIVPS512: return rewriteValueAMD64_OpAMD64VDIVPS512(v) case OpAMD64VDIVPSMasked128: @@ -651,10 +631,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VFMSUBADD213PSMasked256(v) case OpAMD64VFMSUBADD213PSMasked512: return rewriteValueAMD64_OpAMD64VFMSUBADD213PSMasked512(v) - case OpAMD64VMAXPD128: - return rewriteValueAMD64_OpAMD64VMAXPD128(v) - case OpAMD64VMAXPD256: - return rewriteValueAMD64_OpAMD64VMAXPD256(v) case OpAMD64VMAXPD512: return rewriteValueAMD64_OpAMD64VMAXPD512(v) case OpAMD64VMAXPDMasked128: @@ -663,10 +639,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VMAXPDMasked256(v) case OpAMD64VMAXPDMasked512: return rewriteValueAMD64_OpAMD64VMAXPDMasked512(v) - case OpAMD64VMAXPS128: - return rewriteValueAMD64_OpAMD64VMAXPS128(v) - case OpAMD64VMAXPS256: - return rewriteValueAMD64_OpAMD64VMAXPS256(v) case OpAMD64VMAXPS512: return rewriteValueAMD64_OpAMD64VMAXPS512(v) case OpAMD64VMAXPSMasked128: @@ -675,10 +647,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VMAXPSMasked256(v) case OpAMD64VMAXPSMasked512: return rewriteValueAMD64_OpAMD64VMAXPSMasked512(v) - case OpAMD64VMINPD128: - return rewriteValueAMD64_OpAMD64VMINPD128(v) - case OpAMD64VMINPD256: - return rewriteValueAMD64_OpAMD64VMINPD256(v) case OpAMD64VMINPD512: return rewriteValueAMD64_OpAMD64VMINPD512(v) case OpAMD64VMINPDMasked128: @@ -687,10 +655,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VMINPDMasked256(v) case OpAMD64VMINPDMasked512: return rewriteValueAMD64_OpAMD64VMINPDMasked512(v) - case OpAMD64VMINPS128: - return rewriteValueAMD64_OpAMD64VMINPS128(v) - case OpAMD64VMINPS256: - return rewriteValueAMD64_OpAMD64VMINPS256(v) case OpAMD64VMINPS512: return rewriteValueAMD64_OpAMD64VMINPS512(v) case OpAMD64VMINPSMasked128: @@ -727,10 +691,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VMOVSDf2v(v) case OpAMD64VMOVSSf2v: return rewriteValueAMD64_OpAMD64VMOVSSf2v(v) - case OpAMD64VMULPD128: - return rewriteValueAMD64_OpAMD64VMULPD128(v) - case OpAMD64VMULPD256: - return rewriteValueAMD64_OpAMD64VMULPD256(v) case OpAMD64VMULPD512: return rewriteValueAMD64_OpAMD64VMULPD512(v) case OpAMD64VMULPDMasked128: @@ -739,10 +699,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VMULPDMasked256(v) case OpAMD64VMULPDMasked512: return rewriteValueAMD64_OpAMD64VMULPDMasked512(v) - case OpAMD64VMULPS128: - return rewriteValueAMD64_OpAMD64VMULPS128(v) - case OpAMD64VMULPS256: - return rewriteValueAMD64_OpAMD64VMULPS256(v) case OpAMD64VMULPS512: return rewriteValueAMD64_OpAMD64VMULPS512(v) case OpAMD64VMULPSMasked128: @@ -751,10 +707,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VMULPSMasked256(v) case OpAMD64VMULPSMasked512: return rewriteValueAMD64_OpAMD64VMULPSMasked512(v) - case OpAMD64VPABSD128: - return rewriteValueAMD64_OpAMD64VPABSD128(v) - case OpAMD64VPABSD256: - return rewriteValueAMD64_OpAMD64VPABSD256(v) case OpAMD64VPABSD512: return rewriteValueAMD64_OpAMD64VPABSD512(v) case OpAMD64VPABSDMasked128: @@ -775,10 +727,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPABSQMasked256(v) case OpAMD64VPABSQMasked512: return rewriteValueAMD64_OpAMD64VPABSQMasked512(v) - case OpAMD64VPACKSSDW128: - return rewriteValueAMD64_OpAMD64VPACKSSDW128(v) - case OpAMD64VPACKSSDW256: - return rewriteValueAMD64_OpAMD64VPACKSSDW256(v) case OpAMD64VPACKSSDW512: return rewriteValueAMD64_OpAMD64VPACKSSDW512(v) case OpAMD64VPACKSSDWMasked128: @@ -787,10 +735,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPACKSSDWMasked256(v) case OpAMD64VPACKSSDWMasked512: return rewriteValueAMD64_OpAMD64VPACKSSDWMasked512(v) - case OpAMD64VPACKUSDW128: - return rewriteValueAMD64_OpAMD64VPACKUSDW128(v) - case OpAMD64VPACKUSDW256: - return rewriteValueAMD64_OpAMD64VPACKUSDW256(v) case OpAMD64VPACKUSDW512: return rewriteValueAMD64_OpAMD64VPACKUSDW512(v) case OpAMD64VPACKUSDWMasked128: @@ -799,10 +743,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPACKUSDWMasked256(v) case OpAMD64VPACKUSDWMasked512: return rewriteValueAMD64_OpAMD64VPACKUSDWMasked512(v) - case OpAMD64VPADDD128: - return rewriteValueAMD64_OpAMD64VPADDD128(v) - case OpAMD64VPADDD256: - return rewriteValueAMD64_OpAMD64VPADDD256(v) case OpAMD64VPADDD512: return rewriteValueAMD64_OpAMD64VPADDD512(v) case OpAMD64VPADDDMasked128: @@ -811,10 +751,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPADDDMasked256(v) case OpAMD64VPADDDMasked512: return rewriteValueAMD64_OpAMD64VPADDDMasked512(v) - case OpAMD64VPADDQ128: - return rewriteValueAMD64_OpAMD64VPADDQ128(v) - case OpAMD64VPADDQ256: - return rewriteValueAMD64_OpAMD64VPADDQ256(v) case OpAMD64VPADDQ512: return rewriteValueAMD64_OpAMD64VPADDQ512(v) case OpAMD64VPADDQMasked128: @@ -871,34 +807,14 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPBROADCASTW256(v) case OpAMD64VPBROADCASTW512: return rewriteValueAMD64_OpAMD64VPBROADCASTW512(v) - case OpAMD64VPCMPEQD128: - return rewriteValueAMD64_OpAMD64VPCMPEQD128(v) - case OpAMD64VPCMPEQD256: - return rewriteValueAMD64_OpAMD64VPCMPEQD256(v) case OpAMD64VPCMPEQD512: return rewriteValueAMD64_OpAMD64VPCMPEQD512(v) - case OpAMD64VPCMPEQQ128: - return rewriteValueAMD64_OpAMD64VPCMPEQQ128(v) - case OpAMD64VPCMPEQQ256: - return rewriteValueAMD64_OpAMD64VPCMPEQQ256(v) case OpAMD64VPCMPEQQ512: return rewriteValueAMD64_OpAMD64VPCMPEQQ512(v) - case OpAMD64VPCMPGTD128: - return rewriteValueAMD64_OpAMD64VPCMPGTD128(v) - case OpAMD64VPCMPGTD256: - return rewriteValueAMD64_OpAMD64VPCMPGTD256(v) case OpAMD64VPCMPGTD512: return rewriteValueAMD64_OpAMD64VPCMPGTD512(v) - case OpAMD64VPCMPGTQ128: - return rewriteValueAMD64_OpAMD64VPCMPGTQ128(v) - case OpAMD64VPCMPGTQ256: - return rewriteValueAMD64_OpAMD64VPCMPGTQ256(v) case OpAMD64VPCMPGTQ512: return rewriteValueAMD64_OpAMD64VPCMPGTQ512(v) - case OpAMD64VPDPBUSD128: - return rewriteValueAMD64_OpAMD64VPDPBUSD128(v) - case OpAMD64VPDPBUSD256: - return rewriteValueAMD64_OpAMD64VPDPBUSD256(v) case OpAMD64VPDPBUSD512: return rewriteValueAMD64_OpAMD64VPDPBUSD512(v) case OpAMD64VPDPBUSDMasked128: @@ -907,10 +823,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPDPBUSDMasked256(v) case OpAMD64VPDPBUSDMasked512: return rewriteValueAMD64_OpAMD64VPDPBUSDMasked512(v) - case OpAMD64VPDPBUSDS128: - return rewriteValueAMD64_OpAMD64VPDPBUSDS128(v) - case OpAMD64VPDPBUSDS256: - return rewriteValueAMD64_OpAMD64VPDPBUSDS256(v) case OpAMD64VPDPBUSDS512: return rewriteValueAMD64_OpAMD64VPDPBUSDS512(v) case OpAMD64VPDPBUSDSMasked128: @@ -919,10 +831,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPDPBUSDSMasked256(v) case OpAMD64VPDPBUSDSMasked512: return rewriteValueAMD64_OpAMD64VPDPBUSDSMasked512(v) - case OpAMD64VPDPWSSD128: - return rewriteValueAMD64_OpAMD64VPDPWSSD128(v) - case OpAMD64VPDPWSSD256: - return rewriteValueAMD64_OpAMD64VPDPWSSD256(v) case OpAMD64VPDPWSSD512: return rewriteValueAMD64_OpAMD64VPDPWSSD512(v) case OpAMD64VPDPWSSDMasked128: @@ -931,10 +839,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPDPWSSDMasked256(v) case OpAMD64VPDPWSSDMasked512: return rewriteValueAMD64_OpAMD64VPDPWSSDMasked512(v) - case OpAMD64VPDPWSSDS128: - return rewriteValueAMD64_OpAMD64VPDPWSSDS128(v) - case OpAMD64VPDPWSSDS256: - return rewriteValueAMD64_OpAMD64VPDPWSSDS256(v) case OpAMD64VPDPWSSDS512: return rewriteValueAMD64_OpAMD64VPDPWSSDS512(v) case OpAMD64VPDPWSSDSMasked128: @@ -943,8 +847,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPDPWSSDSMasked256(v) case OpAMD64VPDPWSSDSMasked512: return rewriteValueAMD64_OpAMD64VPDPWSSDSMasked512(v) - case OpAMD64VPERMD256: - return rewriteValueAMD64_OpAMD64VPERMD256(v) case OpAMD64VPERMD512: return rewriteValueAMD64_OpAMD64VPERMD512(v) case OpAMD64VPERMDMasked256: @@ -1007,8 +909,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPERMPDMasked256(v) case OpAMD64VPERMPDMasked512: return rewriteValueAMD64_OpAMD64VPERMPDMasked512(v) - case OpAMD64VPERMPS256: - return rewriteValueAMD64_OpAMD64VPERMPS256(v) case OpAMD64VPERMPS512: return rewriteValueAMD64_OpAMD64VPERMPS512(v) case OpAMD64VPERMPSMasked256: @@ -1051,10 +951,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPLZCNTQMasked256(v) case OpAMD64VPLZCNTQMasked512: return rewriteValueAMD64_OpAMD64VPLZCNTQMasked512(v) - case OpAMD64VPMAXSD128: - return rewriteValueAMD64_OpAMD64VPMAXSD128(v) - case OpAMD64VPMAXSD256: - return rewriteValueAMD64_OpAMD64VPMAXSD256(v) case OpAMD64VPMAXSD512: return rewriteValueAMD64_OpAMD64VPMAXSD512(v) case OpAMD64VPMAXSDMasked128: @@ -1075,10 +971,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPMAXSQMasked256(v) case OpAMD64VPMAXSQMasked512: return rewriteValueAMD64_OpAMD64VPMAXSQMasked512(v) - case OpAMD64VPMAXUD128: - return rewriteValueAMD64_OpAMD64VPMAXUD128(v) - case OpAMD64VPMAXUD256: - return rewriteValueAMD64_OpAMD64VPMAXUD256(v) case OpAMD64VPMAXUD512: return rewriteValueAMD64_OpAMD64VPMAXUD512(v) case OpAMD64VPMAXUDMasked128: @@ -1099,10 +991,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPMAXUQMasked256(v) case OpAMD64VPMAXUQMasked512: return rewriteValueAMD64_OpAMD64VPMAXUQMasked512(v) - case OpAMD64VPMINSD128: - return rewriteValueAMD64_OpAMD64VPMINSD128(v) - case OpAMD64VPMINSD256: - return rewriteValueAMD64_OpAMD64VPMINSD256(v) case OpAMD64VPMINSD512: return rewriteValueAMD64_OpAMD64VPMINSD512(v) case OpAMD64VPMINSDMasked128: @@ -1123,10 +1011,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPMINSQMasked256(v) case OpAMD64VPMINSQMasked512: return rewriteValueAMD64_OpAMD64VPMINSQMasked512(v) - case OpAMD64VPMINUD128: - return rewriteValueAMD64_OpAMD64VPMINUD128(v) - case OpAMD64VPMINUD256: - return rewriteValueAMD64_OpAMD64VPMINUD256(v) case OpAMD64VPMINUD512: return rewriteValueAMD64_OpAMD64VPMINUD512(v) case OpAMD64VPMINUDMasked128: @@ -1171,14 +1055,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPMOVVec8x32ToM(v) case OpAMD64VPMOVVec8x64ToM: return rewriteValueAMD64_OpAMD64VPMOVVec8x64ToM(v) - case OpAMD64VPMULDQ128: - return rewriteValueAMD64_OpAMD64VPMULDQ128(v) - case OpAMD64VPMULDQ256: - return rewriteValueAMD64_OpAMD64VPMULDQ256(v) - case OpAMD64VPMULLD128: - return rewriteValueAMD64_OpAMD64VPMULLD128(v) - case OpAMD64VPMULLD256: - return rewriteValueAMD64_OpAMD64VPMULLD256(v) case OpAMD64VPMULLD512: return rewriteValueAMD64_OpAMD64VPMULLD512(v) case OpAMD64VPMULLDMasked128: @@ -1199,10 +1075,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPMULLQMasked256(v) case OpAMD64VPMULLQMasked512: return rewriteValueAMD64_OpAMD64VPMULLQMasked512(v) - case OpAMD64VPMULUDQ128: - return rewriteValueAMD64_OpAMD64VPMULUDQ128(v) - case OpAMD64VPMULUDQ256: - return rewriteValueAMD64_OpAMD64VPMULUDQ256(v) case OpAMD64VPOPCNTD128: return rewriteValueAMD64_OpAMD64VPOPCNTD128(v) case OpAMD64VPOPCNTD256: @@ -1363,10 +1235,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPSLLQMasked256(v) case OpAMD64VPSLLQMasked512: return rewriteValueAMD64_OpAMD64VPSLLQMasked512(v) - case OpAMD64VPSLLVD128: - return rewriteValueAMD64_OpAMD64VPSLLVD128(v) - case OpAMD64VPSLLVD256: - return rewriteValueAMD64_OpAMD64VPSLLVD256(v) case OpAMD64VPSLLVD512: return rewriteValueAMD64_OpAMD64VPSLLVD512(v) case OpAMD64VPSLLVDMasked128: @@ -1375,10 +1243,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPSLLVDMasked256(v) case OpAMD64VPSLLVDMasked512: return rewriteValueAMD64_OpAMD64VPSLLVDMasked512(v) - case OpAMD64VPSLLVQ128: - return rewriteValueAMD64_OpAMD64VPSLLVQ128(v) - case OpAMD64VPSLLVQ256: - return rewriteValueAMD64_OpAMD64VPSLLVQ256(v) case OpAMD64VPSLLVQ512: return rewriteValueAMD64_OpAMD64VPSLLVQ512(v) case OpAMD64VPSLLVQMasked128: @@ -1423,10 +1287,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPSRAQMasked256(v) case OpAMD64VPSRAQMasked512: return rewriteValueAMD64_OpAMD64VPSRAQMasked512(v) - case OpAMD64VPSRAVD128: - return rewriteValueAMD64_OpAMD64VPSRAVD128(v) - case OpAMD64VPSRAVD256: - return rewriteValueAMD64_OpAMD64VPSRAVD256(v) case OpAMD64VPSRAVD512: return rewriteValueAMD64_OpAMD64VPSRAVD512(v) case OpAMD64VPSRAVDMasked128: @@ -1459,10 +1319,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPSRAWMasked256(v) case OpAMD64VPSRAWMasked512: return rewriteValueAMD64_OpAMD64VPSRAWMasked512(v) - case OpAMD64VPSRLVD128: - return rewriteValueAMD64_OpAMD64VPSRLVD128(v) - case OpAMD64VPSRLVD256: - return rewriteValueAMD64_OpAMD64VPSRLVD256(v) case OpAMD64VPSRLVD512: return rewriteValueAMD64_OpAMD64VPSRLVD512(v) case OpAMD64VPSRLVDMasked128: @@ -1471,10 +1327,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPSRLVDMasked256(v) case OpAMD64VPSRLVDMasked512: return rewriteValueAMD64_OpAMD64VPSRLVDMasked512(v) - case OpAMD64VPSRLVQ128: - return rewriteValueAMD64_OpAMD64VPSRLVQ128(v) - case OpAMD64VPSRLVQ256: - return rewriteValueAMD64_OpAMD64VPSRLVQ256(v) case OpAMD64VPSRLVQ512: return rewriteValueAMD64_OpAMD64VPSRLVQ512(v) case OpAMD64VPSRLVQMasked128: @@ -1483,10 +1335,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPSRLVQMasked256(v) case OpAMD64VPSRLVQMasked512: return rewriteValueAMD64_OpAMD64VPSRLVQMasked512(v) - case OpAMD64VPSUBD128: - return rewriteValueAMD64_OpAMD64VPSUBD128(v) - case OpAMD64VPSUBD256: - return rewriteValueAMD64_OpAMD64VPSUBD256(v) case OpAMD64VPSUBD512: return rewriteValueAMD64_OpAMD64VPSUBD512(v) case OpAMD64VPSUBDMasked128: @@ -1495,10 +1343,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPSUBDMasked256(v) case OpAMD64VPSUBDMasked512: return rewriteValueAMD64_OpAMD64VPSUBDMasked512(v) - case OpAMD64VPSUBQ128: - return rewriteValueAMD64_OpAMD64VPSUBQ128(v) - case OpAMD64VPSUBQ256: - return rewriteValueAMD64_OpAMD64VPSUBQ256(v) case OpAMD64VPSUBQ512: return rewriteValueAMD64_OpAMD64VPSUBQ512(v) case OpAMD64VPSUBQMasked128: @@ -1507,28 +1351,12 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VPSUBQMasked256(v) case OpAMD64VPSUBQMasked512: return rewriteValueAMD64_OpAMD64VPSUBQMasked512(v) - case OpAMD64VPUNPCKHDQ128: - return rewriteValueAMD64_OpAMD64VPUNPCKHDQ128(v) - case OpAMD64VPUNPCKHDQ256: - return rewriteValueAMD64_OpAMD64VPUNPCKHDQ256(v) case OpAMD64VPUNPCKHDQ512: return rewriteValueAMD64_OpAMD64VPUNPCKHDQ512(v) - case OpAMD64VPUNPCKHQDQ128: - return rewriteValueAMD64_OpAMD64VPUNPCKHQDQ128(v) - case OpAMD64VPUNPCKHQDQ256: - return rewriteValueAMD64_OpAMD64VPUNPCKHQDQ256(v) case OpAMD64VPUNPCKHQDQ512: return rewriteValueAMD64_OpAMD64VPUNPCKHQDQ512(v) - case OpAMD64VPUNPCKLDQ128: - return rewriteValueAMD64_OpAMD64VPUNPCKLDQ128(v) - case OpAMD64VPUNPCKLDQ256: - return rewriteValueAMD64_OpAMD64VPUNPCKLDQ256(v) case OpAMD64VPUNPCKLDQ512: return rewriteValueAMD64_OpAMD64VPUNPCKLDQ512(v) - case OpAMD64VPUNPCKLQDQ128: - return rewriteValueAMD64_OpAMD64VPUNPCKLQDQ128(v) - case OpAMD64VPUNPCKLQDQ256: - return rewriteValueAMD64_OpAMD64VPUNPCKLQDQ256(v) case OpAMD64VPUNPCKLQDQ512: return rewriteValueAMD64_OpAMD64VPUNPCKLQDQ512(v) case OpAMD64VPXORD512: @@ -1611,10 +1439,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VSCALEFPSMasked256(v) case OpAMD64VSCALEFPSMasked512: return rewriteValueAMD64_OpAMD64VSCALEFPSMasked512(v) - case OpAMD64VSQRTPD128: - return rewriteValueAMD64_OpAMD64VSQRTPD128(v) - case OpAMD64VSQRTPD256: - return rewriteValueAMD64_OpAMD64VSQRTPD256(v) case OpAMD64VSQRTPD512: return rewriteValueAMD64_OpAMD64VSQRTPD512(v) case OpAMD64VSQRTPDMasked128: @@ -1623,10 +1447,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VSQRTPDMasked256(v) case OpAMD64VSQRTPDMasked512: return rewriteValueAMD64_OpAMD64VSQRTPDMasked512(v) - case OpAMD64VSQRTPS128: - return rewriteValueAMD64_OpAMD64VSQRTPS128(v) - case OpAMD64VSQRTPS256: - return rewriteValueAMD64_OpAMD64VSQRTPS256(v) case OpAMD64VSQRTPS512: return rewriteValueAMD64_OpAMD64VSQRTPS512(v) case OpAMD64VSQRTPSMasked128: @@ -1635,10 +1455,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VSQRTPSMasked256(v) case OpAMD64VSQRTPSMasked512: return rewriteValueAMD64_OpAMD64VSQRTPSMasked512(v) - case OpAMD64VSUBPD128: - return rewriteValueAMD64_OpAMD64VSUBPD128(v) - case OpAMD64VSUBPD256: - return rewriteValueAMD64_OpAMD64VSUBPD256(v) case OpAMD64VSUBPD512: return rewriteValueAMD64_OpAMD64VSUBPD512(v) case OpAMD64VSUBPDMasked128: @@ -1647,10 +1463,6 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64VSUBPDMasked256(v) case OpAMD64VSUBPDMasked512: return rewriteValueAMD64_OpAMD64VSUBPDMasked512(v) - case OpAMD64VSUBPS128: - return rewriteValueAMD64_OpAMD64VSUBPS128(v) - case OpAMD64VSUBPS256: - return rewriteValueAMD64_OpAMD64VSUBPS256(v) case OpAMD64VSUBPS512: return rewriteValueAMD64_OpAMD64VSUBPS512(v) case OpAMD64VSUBPSMasked128: @@ -27616,66 +27428,6 @@ func rewriteValueAMD64_OpAMD64TESTWconst(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VADDPD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VADDPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VADDPD128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VADDPD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VADDPD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VADDPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VADDPD256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VADDPD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VADDPD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -27802,66 +27554,6 @@ func rewriteValueAMD64_OpAMD64VADDPDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VADDPS128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VADDPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VADDPS128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VADDPS128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VADDPS256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VADDPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VADDPS256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VADDPS256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VADDPS512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -28144,56 +27836,6 @@ func rewriteValueAMD64_OpAMD64VCVTPS2UDQMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VCVTTPS2DQ128(v *Value) bool { - v_0 := v.Args[0] - // match: (VCVTTPS2DQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VCVTTPS2DQ128load {sym} [off] ptr mem) - for { - l := v_0 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VCVTTPS2DQ128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VCVTTPS2DQ256(v *Value) bool { - v_0 := v.Args[0] - // match: (VCVTTPS2DQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VCVTTPS2DQ256load {sym} [off] ptr mem) - for { - l := v_0 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VCVTTPS2DQ256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VCVTTPS2DQ512(v *Value) bool { v_0 := v.Args[0] // match: (VCVTTPS2DQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) @@ -28300,60 +27942,6 @@ func rewriteValueAMD64_OpAMD64VCVTTPS2DQMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VDIVPD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VDIVPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VDIVPD128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VDIVPD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VDIVPD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VDIVPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VDIVPD256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VDIVPD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VDIVPD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -28468,60 +28056,6 @@ func rewriteValueAMD64_OpAMD64VDIVPDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VDIVPS128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VDIVPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VDIVPS128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VDIVPS128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VDIVPS256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VDIVPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VDIVPS256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VDIVPS256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VDIVPS512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -29716,66 +29250,6 @@ func rewriteValueAMD64_OpAMD64VFMSUBADD213PSMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VMAXPD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VMAXPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VMAXPD128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VMAXPD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VMAXPD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VMAXPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VMAXPD256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VMAXPD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VMAXPD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -29902,66 +29376,6 @@ func rewriteValueAMD64_OpAMD64VMAXPDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VMAXPS128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VMAXPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VMAXPS128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VMAXPS128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VMAXPS256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VMAXPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VMAXPS256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VMAXPS256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VMAXPS512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -30088,66 +29502,6 @@ func rewriteValueAMD64_OpAMD64VMAXPSMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VMINPD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VMINPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VMINPD128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VMINPD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VMINPD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VMINPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VMINPD256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VMINPD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VMINPD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -30274,66 +29628,6 @@ func rewriteValueAMD64_OpAMD64VMINPDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VMINPS128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VMINPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VMINPS128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VMINPS128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VMINPS256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VMINPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VMINPS256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VMINPS256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VMINPS512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -33286,66 +32580,6 @@ func rewriteValueAMD64_OpAMD64VMOVSSf2v(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VMULPD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VMULPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VMULPD128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VMULPD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VMULPD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VMULPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VMULPD256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VMULPD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VMULPD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -33472,66 +32706,6 @@ func rewriteValueAMD64_OpAMD64VMULPDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VMULPS128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VMULPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VMULPS128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VMULPS128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VMULPS256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VMULPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VMULPS256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VMULPS256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VMULPS512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -33658,56 +32832,6 @@ func rewriteValueAMD64_OpAMD64VMULPSMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPABSD128(v *Value) bool { - v_0 := v.Args[0] - // match: (VPABSD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPABSD128load {sym} [off] ptr mem) - for { - l := v_0 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPABSD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPABSD256(v *Value) bool { - v_0 := v.Args[0] - // match: (VPABSD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPABSD256load {sym} [off] ptr mem) - for { - l := v_0 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPABSD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPABSD512(v *Value) bool { v_0 := v.Args[0] // match: (VPABSD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) @@ -33970,60 +33094,6 @@ func rewriteValueAMD64_OpAMD64VPABSQMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPACKSSDW128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPACKSSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPACKSSDW128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPACKSSDW128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPACKSSDW256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPACKSSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPACKSSDW256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPACKSSDW256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPACKSSDW512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -34138,60 +33208,6 @@ func rewriteValueAMD64_OpAMD64VPACKSSDWMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPACKUSDW128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPACKUSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPACKUSDW128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPACKUSDW128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPACKUSDW256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPACKUSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPACKUSDW256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPACKUSDW256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPACKUSDW512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -34306,66 +33322,6 @@ func rewriteValueAMD64_OpAMD64VPACKUSDWMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPADDD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPADDD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPADDD128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPADDD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VPADDD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPADDD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPADDD256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPADDD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VPADDD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -34492,66 +33448,6 @@ func rewriteValueAMD64_OpAMD64VPADDDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPADDQ128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPADDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPADDQ128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPADDQ128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VPADDQ256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPADDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPADDQ256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPADDQ256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VPADDQ512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -35498,66 +34394,6 @@ func rewriteValueAMD64_OpAMD64VPBROADCASTW512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPCMPEQD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPCMPEQD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPCMPEQD128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPCMPEQD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VPCMPEQD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPCMPEQD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPCMPEQD256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPCMPEQD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VPCMPEQD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -35588,66 +34424,6 @@ func rewriteValueAMD64_OpAMD64VPCMPEQD512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPCMPEQQ128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPCMPEQQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPCMPEQQ128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPCMPEQQ128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VPCMPEQQ256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPCMPEQQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPCMPEQQ256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPCMPEQQ256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VPCMPEQQ512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -35678,60 +34454,6 @@ func rewriteValueAMD64_OpAMD64VPCMPEQQ512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPCMPGTD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPCMPGTD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPCMPGTD128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPCMPGTD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPCMPGTD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPCMPGTD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPCMPGTD256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPCMPGTD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPCMPGTD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -35759,60 +34481,6 @@ func rewriteValueAMD64_OpAMD64VPCMPGTD512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPCMPGTQ128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPCMPGTQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPCMPGTQ128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPCMPGTQ128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPCMPGTQ256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPCMPGTQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPCMPGTQ256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPCMPGTQ256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPCMPGTQ512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -35840,64 +34508,6 @@ func rewriteValueAMD64_OpAMD64VPCMPGTQ512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPDPBUSD128(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPDPBUSD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPDPBUSD128load {sym} [off] x y ptr mem) - for { - x := v_0 - y := v_1 - l := v_2 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPDPBUSD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg4(x, y, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPDPBUSD256(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPDPBUSD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPDPBUSD256load {sym} [off] x y ptr mem) - for { - x := v_0 - y := v_1 - l := v_2 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPDPBUSD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg4(x, y, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPDPBUSD512(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -36020,64 +34630,6 @@ func rewriteValueAMD64_OpAMD64VPDPBUSDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPDPBUSDS128(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPDPBUSDS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPDPBUSDS128load {sym} [off] x y ptr mem) - for { - x := v_0 - y := v_1 - l := v_2 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPDPBUSDS128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg4(x, y, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPDPBUSDS256(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPDPBUSDS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPDPBUSDS256load {sym} [off] x y ptr mem) - for { - x := v_0 - y := v_1 - l := v_2 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPDPBUSDS256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg4(x, y, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPDPBUSDS512(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -36200,64 +34752,6 @@ func rewriteValueAMD64_OpAMD64VPDPBUSDSMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPDPWSSD128(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPDPWSSD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPDPWSSD128load {sym} [off] x y ptr mem) - for { - x := v_0 - y := v_1 - l := v_2 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPDPWSSD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg4(x, y, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPDPWSSD256(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPDPWSSD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPDPWSSD256load {sym} [off] x y ptr mem) - for { - x := v_0 - y := v_1 - l := v_2 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPDPWSSD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg4(x, y, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPDPWSSD512(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -36380,64 +34874,6 @@ func rewriteValueAMD64_OpAMD64VPDPWSSDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPDPWSSDS128(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPDPWSSDS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPDPWSSDS128load {sym} [off] x y ptr mem) - for { - x := v_0 - y := v_1 - l := v_2 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPDPWSSDS128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg4(x, y, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPDPWSSDS256(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPDPWSSDS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPDPWSSDS256load {sym} [off] x y ptr mem) - for { - x := v_0 - y := v_1 - l := v_2 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPDPWSSDS256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg4(x, y, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPDPWSSDS512(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -36560,33 +34996,6 @@ func rewriteValueAMD64_OpAMD64VPDPWSSDSMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPERMD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPERMD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPERMD256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPERMD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPERMD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -37504,33 +35913,6 @@ func rewriteValueAMD64_OpAMD64VPERMPDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPERMPS256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPERMPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPERMPS256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPERMPS256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPERMPS512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -38114,66 +36496,6 @@ func rewriteValueAMD64_OpAMD64VPLZCNTQMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPMAXSD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMAXSD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMAXSD128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMAXSD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VPMAXSD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMAXSD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMAXSD256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMAXSD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VPMAXSD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -38486,66 +36808,6 @@ func rewriteValueAMD64_OpAMD64VPMAXSQMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPMAXUD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMAXUD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMAXUD128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMAXUD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VPMAXUD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMAXUD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMAXUD256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMAXUD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VPMAXUD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -38858,66 +37120,6 @@ func rewriteValueAMD64_OpAMD64VPMAXUQMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPMINSD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMINSD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMINSD128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMINSD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VPMINSD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMINSD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMINSD256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMINSD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VPMINSD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -39230,66 +37432,6 @@ func rewriteValueAMD64_OpAMD64VPMINSQMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPMINUD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMINUD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMINUD128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMINUD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VPMINUD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMINUD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMINUD256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMINUD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VPMINUD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -39770,126 +37912,6 @@ func rewriteValueAMD64_OpAMD64VPMOVVec8x64ToM(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPMULDQ128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMULDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMULDQ128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMULDQ128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VPMULDQ256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMULDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMULDQ256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMULDQ256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VPMULLD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMULLD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMULLD128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMULLD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VPMULLD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMULLD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMULLD256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMULLD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VPMULLD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -40202,66 +38224,6 @@ func rewriteValueAMD64_OpAMD64VPMULLQMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPMULUDQ128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMULUDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMULUDQ128load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMULUDQ128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} -func rewriteValueAMD64_OpAMD64VPMULUDQ256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPMULUDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPMULUDQ256load {sym} [off] x ptr mem) - for { - for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - continue - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - continue - } - v.reset(OpAMD64VPMULUDQ256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - break - } - return false -} func rewriteValueAMD64_OpAMD64VPOPCNTD128(v *Value) bool { v_0 := v.Args[0] // match: (VPOPCNTD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) @@ -42446,60 +40408,6 @@ func rewriteValueAMD64_OpAMD64VPSLLQMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPSLLVD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSLLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSLLVD128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSLLVD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPSLLVD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSLLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSLLVD256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSLLVD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPSLLVD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -42614,60 +40522,6 @@ func rewriteValueAMD64_OpAMD64VPSLLVDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPSLLVQ128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSLLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSLLVQ128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSLLVQ128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPSLLVQ256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSLLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSLLVQ256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSLLVQ256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPSLLVQ512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -43124,60 +40978,6 @@ func rewriteValueAMD64_OpAMD64VPSRAQMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPSRAVD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSRAVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSRAVD128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSRAVD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPSRAVD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSRAVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSRAVD256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSRAVD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPSRAVD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -43574,60 +41374,6 @@ func rewriteValueAMD64_OpAMD64VPSRAWMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPSRLVD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSRLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSRLVD128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSRLVD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPSRLVD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSRLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSRLVD256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSRLVD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPSRLVD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -43742,60 +41488,6 @@ func rewriteValueAMD64_OpAMD64VPSRLVDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPSRLVQ128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSRLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSRLVQ128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSRLVQ128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPSRLVQ256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSRLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSRLVQ256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSRLVQ256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPSRLVQ512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -43910,60 +41602,6 @@ func rewriteValueAMD64_OpAMD64VPSRLVQMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPSUBD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSUBD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSUBD128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSUBD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPSUBD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSUBD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSUBD256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSUBD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPSUBD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -44078,60 +41716,6 @@ func rewriteValueAMD64_OpAMD64VPSUBDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPSUBQ128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSUBQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSUBQ128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSUBQ128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPSUBQ256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPSUBQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPSUBQ256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPSUBQ256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPSUBQ512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -44246,60 +41830,6 @@ func rewriteValueAMD64_OpAMD64VPSUBQMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPUNPCKHDQ128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPUNPCKHDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPUNPCKHDQ128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPUNPCKHDQ128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPUNPCKHDQ256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPUNPCKHDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPUNPCKHDQ256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPUNPCKHDQ256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPUNPCKHDQ512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -44327,60 +41857,6 @@ func rewriteValueAMD64_OpAMD64VPUNPCKHDQ512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPUNPCKHQDQ128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPUNPCKHQDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPUNPCKHQDQ128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPUNPCKHQDQ128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPUNPCKHQDQ256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPUNPCKHQDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPUNPCKHQDQ256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPUNPCKHQDQ256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPUNPCKHQDQ512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -44408,60 +41884,6 @@ func rewriteValueAMD64_OpAMD64VPUNPCKHQDQ512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPUNPCKLDQ128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPUNPCKLDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPUNPCKLDQ128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPUNPCKLDQ128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPUNPCKLDQ256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPUNPCKLDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPUNPCKLDQ256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPUNPCKLDQ256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPUNPCKLDQ512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -44489,60 +41911,6 @@ func rewriteValueAMD64_OpAMD64VPUNPCKLDQ512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VPUNPCKLQDQ128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPUNPCKLQDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPUNPCKLQDQ128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPUNPCKLQDQ128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VPUNPCKLQDQ256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VPUNPCKLQDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VPUNPCKLQDQ256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VPUNPCKLQDQ256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VPUNPCKLQDQ512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -45682,56 +43050,6 @@ func rewriteValueAMD64_OpAMD64VSCALEFPSMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VSQRTPD128(v *Value) bool { - v_0 := v.Args[0] - // match: (VSQRTPD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VSQRTPD128load {sym} [off] ptr mem) - for { - l := v_0 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VSQRTPD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VSQRTPD256(v *Value) bool { - v_0 := v.Args[0] - // match: (VSQRTPD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VSQRTPD256load {sym} [off] ptr mem) - for { - l := v_0 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VSQRTPD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VSQRTPD512(v *Value) bool { v_0 := v.Args[0] // match: (VSQRTPD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) @@ -45838,56 +43156,6 @@ func rewriteValueAMD64_OpAMD64VSQRTPDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VSQRTPS128(v *Value) bool { - v_0 := v.Args[0] - // match: (VSQRTPS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VSQRTPS128load {sym} [off] ptr mem) - for { - l := v_0 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VSQRTPS128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VSQRTPS256(v *Value) bool { - v_0 := v.Args[0] - // match: (VSQRTPS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VSQRTPS256load {sym} [off] ptr mem) - for { - l := v_0 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VSQRTPS256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg2(ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VSQRTPS512(v *Value) bool { v_0 := v.Args[0] // match: (VSQRTPS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) @@ -45994,60 +43262,6 @@ func rewriteValueAMD64_OpAMD64VSQRTPSMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VSUBPD128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VSUBPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VSUBPD128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VSUBPD128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VSUBPD256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VSUBPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VSUBPD256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VSUBPD256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VSUBPD512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -46162,60 +43376,6 @@ func rewriteValueAMD64_OpAMD64VSUBPDMasked512(v *Value) bool { } return false } -func rewriteValueAMD64_OpAMD64VSUBPS128(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VSUBPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VSUBPS128load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload128 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VSUBPS128load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} -func rewriteValueAMD64_OpAMD64VSUBPS256(v *Value) bool { - v_1 := v.Args[1] - v_0 := v.Args[0] - // match: (VSUBPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem)) - // cond: canMergeLoad(v, l) && clobber(l) - // result: (VSUBPS256load {sym} [off] x ptr mem) - for { - x := v_0 - l := v_1 - if l.Op != OpAMD64VMOVDQUload256 { - break - } - off := auxIntToInt32(l.AuxInt) - sym := auxToSym(l.Aux) - mem := l.Args[1] - ptr := l.Args[0] - if !(canMergeLoad(v, l) && clobber(l)) { - break - } - v.reset(OpAMD64VSUBPS256load) - v.AuxInt = int32ToAuxInt(off) - v.Aux = symToAux(sym) - v.AddArg3(x, ptr, mem) - return true - } - return false -} func rewriteValueAMD64_OpAMD64VSUBPS512(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] diff --git a/src/simd/_gen/simdgen/gen_utility.go b/src/simd/_gen/simdgen/gen_utility.go index 3fb1edfab41..78a214783b1 100644 --- a/src/simd/_gen/simdgen/gen_utility.go +++ b/src/simd/_gen/simdgen/gen_utility.go @@ -632,7 +632,21 @@ func dedupGodef(ops []Operation) ([]Operation, error) { if isAVX512(i) && !isAVX512(j) { return 1 } - return strings.Compare(i.CPUFeature, j.CPUFeature) + if i.CPUFeature != j.CPUFeature { + return strings.Compare(i.CPUFeature, j.CPUFeature) + } + // Weirdly Intel sometimes has duplicated definitions for the same instruction, + // this confuses the XED mem-op merge logic: [MemFeature] will only be attached to an instruction + // for only once, which means that for essentially duplicated instructions only one will have the + // proper [MemFeature] set. We have to make this sort deterministic for [MemFeature]. + if i.MemFeatures != nil && j.MemFeatures == nil { + return -1 + } + if i.MemFeatures == nil && j.MemFeatures != nil { + return 1 + } + // Their order does not matter anymore, at least for now. + return 0 }) } deduped = append(deduped, dup[0]) diff --git a/src/simd/_gen/simdgen/xed.go b/src/simd/_gen/simdgen/xed.go index 411c8bcf5c3..e521f0c8d44 100644 --- a/src/simd/_gen/simdgen/xed.go +++ b/src/simd/_gen/simdgen/xed.go @@ -9,6 +9,7 @@ import ( "fmt" "log" "maps" + "reflect" "regexp" "slices" "strconv" @@ -137,14 +138,24 @@ func loadXED(xedPath string) []*unify.Value { } if len(o.ops) == len(m.ops) { for j := range o.ops { - v1, ok3 := o.ops[j].(operandVReg) - v2, ok4 := m.ops[j].(operandVReg) - if !ok3 || !ok4 { - continue - } - if v1.vecShape != v2.vecShape { - // A mismatch, skip this memOp - continue outer + if reflect.TypeOf(o.ops[j]) == reflect.TypeOf(m.ops[j]) { + v1, ok3 := o.ops[j].(operandVReg) + v2, _ := m.ops[j].(operandVReg) + if !ok3 { + continue + } + if v1.vecShape != v2.vecShape { + // A mismatch, skip this memOp + continue outer + } + } else { + _, ok3 := o.ops[j].(operandVReg) + _, ok4 := m.ops[j].(operandMem) + // The only difference must be the vreg and mem, no other cases. + if !ok3 || !ok4 { + // A mismatch, skip this memOp + continue outer + } } } // Found a match, break early @@ -155,10 +166,10 @@ func loadXED(xedPath string) []*unify.Value { // Remove the match from memOps, it's now merged to this pure vreg operation if matchIdx != -1 { memOps[opcode] = append(memOps[opcode][:matchIdx], memOps[opcode][matchIdx+1:]...) + // Merge is done by adding a new field + // Right now we only have vbcst + addFields["memFeatures"] = "vbcst" } - // Merge is done by adding a new field - // Right now we only have vbcst - addFields["memFeatures"] = "vbcst" } } appendDefs(o.inst, o.ops, addFields)