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cmd/internal/obj: move ARM64RegisterExtension from cmd/asm/internal/arch
Change-Id: Iab41674953655efa7be3d306dfb3f5be486be501 Reviewed-on: https://go-review.googlesource.com/c/go/+/701455 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Randall <khr@google.com>
This commit is contained in:
Vasily Leonenko
Cherry Mui
parent
27f9a6705c
commit
45eee553e2
3 changed files with 145 additions and 144 deletions
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@ -195,149 +195,6 @@ func ARM64RegisterShift(reg, op, count int16) (int64, error) {
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return int64(reg&31)<<16 | int64(op)<<22 | int64(uint16(count)), nil
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}
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// ARM64RegisterExtension constructs an ARM64 register with extension or arrangement.
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func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error {
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Rnum := (reg & 31) + int16(num<<5)
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if isAmount {
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if num < 0 || num > 7 {
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return errors.New("index shift amount is out of range")
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}
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}
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if reg <= arm64.REG_R31 && reg >= arm64.REG_R0 {
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if !isAmount {
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return errors.New("invalid register extension")
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}
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switch ext {
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case "UXTB":
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_UXTB + Rnum
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case "UXTH":
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_UXTH + Rnum
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case "UXTW":
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// effective address of memory is a base register value and an offset register value.
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if a.Type == obj.TYPE_MEM {
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a.Index = arm64.REG_UXTW + Rnum
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} else {
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a.Reg = arm64.REG_UXTW + Rnum
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}
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case "UXTX":
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_UXTX + Rnum
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case "SXTB":
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_SXTB + Rnum
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case "SXTH":
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_SXTH + Rnum
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case "SXTW":
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if a.Type == obj.TYPE_MEM {
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a.Index = arm64.REG_SXTW + Rnum
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} else {
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a.Reg = arm64.REG_SXTW + Rnum
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}
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case "SXTX":
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if a.Type == obj.TYPE_MEM {
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a.Index = arm64.REG_SXTX + Rnum
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} else {
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a.Reg = arm64.REG_SXTX + Rnum
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}
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case "LSL":
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a.Index = arm64.REG_LSL + Rnum
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default:
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return errors.New("unsupported general register extension type: " + ext)
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}
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} else if reg <= arm64.REG_V31 && reg >= arm64.REG_V0 {
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switch ext {
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case "B8":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8B & 15) << 5)
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case "B16":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_16B & 15) << 5)
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case "H4":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4H & 15) << 5)
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case "H8":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8H & 15) << 5)
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case "S2":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2S & 15) << 5)
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case "S4":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4S & 15) << 5)
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case "D1":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1D & 15) << 5)
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case "D2":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2D & 15) << 5)
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case "Q1":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1Q & 15) << 5)
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case "B":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_B & 15) << 5)
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a.Index = num
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case "H":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_H & 15) << 5)
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a.Index = num
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case "S":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_S & 15) << 5)
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a.Index = num
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case "D":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_D & 15) << 5)
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a.Index = num
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default:
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return errors.New("unsupported simd register extension type: " + ext)
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}
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} else {
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return errors.New("invalid register and extension combination")
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}
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return nil
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}
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// ARM64RegisterArrangement constructs an ARM64 vector register arrangement.
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func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) {
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var curQ, curSize uint16
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@ -775,7 +775,7 @@ func (p *Parser) registerExtension(a *obj.Addr, name string, prefix rune) {
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switch p.arch.Family {
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case sys.ARM64:
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err := arch.ARM64RegisterExtension(a, ext, reg, num, isAmount, isIndex)
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err := arm64.ARM64RegisterExtension(a, ext, reg, num, isAmount, isIndex)
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if err != nil {
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p.errorf("%v", err)
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}
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@ -34,6 +34,7 @@ import (
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"cmd/internal/obj"
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"cmd/internal/objabi"
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"encoding/binary"
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"errors"
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"fmt"
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"log"
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"math"
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@ -7855,3 +7856,146 @@ func (c *ctxt7) encRegShiftOrExt(p *obj.Prog, a *obj.Addr, r int16) uint32 {
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func pack(q uint32, arngA, arngB uint8) uint32 {
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return uint32(q)<<16 | uint32(arngA)<<8 | uint32(arngB)
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}
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// ARM64RegisterExtension constructs an ARM64 register with extension or arrangement.
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func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error {
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Rnum := (reg & 31) + int16(num<<5)
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if isAmount {
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if num < 0 || num > 7 {
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return errors.New("index shift amount is out of range")
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}
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}
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if reg <= REG_R31 && reg >= REG_R0 {
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if !isAmount {
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return errors.New("invalid register extension")
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}
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switch ext {
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case "UXTB":
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = REG_UXTB + Rnum
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case "UXTH":
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = REG_UXTH + Rnum
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case "UXTW":
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// effective address of memory is a base register value and an offset register value.
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if a.Type == obj.TYPE_MEM {
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a.Index = REG_UXTW + Rnum
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} else {
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a.Reg = REG_UXTW + Rnum
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}
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case "UXTX":
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = REG_UXTX + Rnum
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case "SXTB":
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = REG_SXTB + Rnum
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case "SXTH":
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = REG_SXTH + Rnum
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case "SXTW":
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if a.Type == obj.TYPE_MEM {
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a.Index = REG_SXTW + Rnum
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} else {
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a.Reg = REG_SXTW + Rnum
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}
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case "SXTX":
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if a.Type == obj.TYPE_MEM {
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a.Index = REG_SXTX + Rnum
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} else {
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a.Reg = REG_SXTX + Rnum
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}
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case "LSL":
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a.Index = REG_LSL + Rnum
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default:
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return errors.New("unsupported general register extension type: " + ext)
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}
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} else if reg <= REG_V31 && reg >= REG_V0 {
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switch ext {
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case "B8":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = REG_ARNG + (reg & 31) + ((ARNG_8B & 15) << 5)
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case "B16":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = REG_ARNG + (reg & 31) + ((ARNG_16B & 15) << 5)
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case "H4":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = REG_ARNG + (reg & 31) + ((ARNG_4H & 15) << 5)
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case "H8":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = REG_ARNG + (reg & 31) + ((ARNG_8H & 15) << 5)
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case "S2":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = REG_ARNG + (reg & 31) + ((ARNG_2S & 15) << 5)
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case "S4":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = REG_ARNG + (reg & 31) + ((ARNG_4S & 15) << 5)
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case "D1":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = REG_ARNG + (reg & 31) + ((ARNG_1D & 15) << 5)
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case "D2":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = REG_ARNG + (reg & 31) + ((ARNG_2D & 15) << 5)
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case "Q1":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = REG_ARNG + (reg & 31) + ((ARNG_1Q & 15) << 5)
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case "B":
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if !isIndex {
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return nil
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}
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a.Reg = REG_ELEM + (reg & 31) + ((ARNG_B & 15) << 5)
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a.Index = num
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case "H":
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if !isIndex {
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return nil
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}
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a.Reg = REG_ELEM + (reg & 31) + ((ARNG_H & 15) << 5)
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a.Index = num
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case "S":
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if !isIndex {
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return nil
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}
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a.Reg = REG_ELEM + (reg & 31) + ((ARNG_S & 15) << 5)
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a.Index = num
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case "D":
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if !isIndex {
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return nil
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}
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a.Reg = REG_ELEM + (reg & 31) + ((ARNG_D & 15) << 5)
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a.Index = num
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default:
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return errors.New("unsupported simd register extension type: " + ext)
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}
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} else {
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return errors.New("invalid register and extension combination")
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}
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return nil
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}
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