[dev.simd] cmd/compile: correct register mask of some AVX512 ops

Change-Id: Ifce9d6667955c9b16b1cd78d6dd216a9c568c17a
Reviewed-on: https://go-review.googlesource.com/c/go/+/698239
Reviewed-by: Junyang Shao <shaojunyang@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: David Chase <drchase@google.com>

src/cmd/compile/internal/ssa/_gen/AMD64Ops.go

@@ -231,13 +231,13 @@ func init() {
 		w21   = regInfo{inputs: []regMask{wz, wz}, outputs: wonly}
 		wk    = regInfo{inputs: wzonly, outputs: maskonly}
 		kw    = regInfo{inputs: maskonly, outputs: wonly}
-		w2k   = regInfo{inputs: []regMask{fp, fp}, outputs: maskonly}
-		wkw   = regInfo{inputs: []regMask{fp, mask}, outputs: fponly}
-		w2kw  = regInfo{inputs: []regMask{fp, fp, mask}, outputs: fponly}
-		w2kk  = regInfo{inputs: []regMask{fp, fp, mask}, outputs: maskonly}
-		w31   = regInfo{inputs: []regMask{fp, fp, fp}, outputs: fponly}
-		w3kw  = regInfo{inputs: []regMask{fp, fp, fp, mask}, outputs: fponly}
-		wgpw  = regInfo{inputs: []regMask{fp, gp}, outputs: fponly}
+		w2k   = regInfo{inputs: []regMask{wz, wz}, outputs: maskonly}
+		wkw   = regInfo{inputs: []regMask{wz, mask}, outputs: wonly}
+		w2kw  = regInfo{inputs: []regMask{wz, wz, mask}, outputs: wonly}
+		w2kk  = regInfo{inputs: []regMask{wz, wz, mask}, outputs: maskonly}
+		w31   = regInfo{inputs: []regMask{w, wz, wz}, outputs: wonly}       // used in resultInArg0 ops, arg0 must not be x15
+		w3kw  = regInfo{inputs: []regMask{w, wz, wz, mask}, outputs: wonly} // used in resultInArg0 ops, arg0 must not be x15
+		wgpw  = regInfo{inputs: []regMask{wz, gp}, outputs: wonly}
 		wgp   = regInfo{inputs: wzonly, outputs: gponly}
 		wfpw  = regInfo{inputs: []regMask{wz, fp}, outputs: wonly}
 		wfpkw = regInfo{inputs: []regMask{wz, fp, mask}, outputs: wonly}