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cmd/asm: fix operand order of ARM's MULA instruction
As discussion in issue #19141, the addend should be the third argument of MULA. This patch fixes it in both the front end and the back end of the assembler. And also tests are added to the encoding test. Fixes #19141 Change-Id: Idbc6f338b8fdfcad97a135f27a98c5b375b27d43 Reviewed-on: https://go-review.googlesource.com/42028 Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
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4 changed files with 11 additions and 11 deletions
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@ -639,12 +639,12 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
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// All must be registers.
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// All must be registers.
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p.getRegister(prog, op, &a[0])
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p.getRegister(prog, op, &a[0])
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r1 := p.getRegister(prog, op, &a[1])
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r1 := p.getRegister(prog, op, &a[1])
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p.getRegister(prog, op, &a[2])
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r2 := p.getRegister(prog, op, &a[2])
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r3 := p.getRegister(prog, op, &a[3])
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p.getRegister(prog, op, &a[3])
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prog.From = a[0]
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prog.From = a[0]
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prog.To = a[2]
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prog.To = a[3]
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prog.To.Type = obj.TYPE_REGREG2
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prog.To.Type = obj.TYPE_REGREG2
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prog.To.Offset = int64(r3)
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prog.To.Offset = int64(r2)
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prog.Reg = r1
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prog.Reg = r1
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break
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break
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}
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}
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2
src/cmd/asm/internal/asm/testdata/arm.s
vendored
2
src/cmd/asm/internal/asm/testdata/arm.s
vendored
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@ -951,6 +951,8 @@ jmp_label_3:
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MULAWT R1, R2, R3, R4 // c23124e1
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MULAWT R1, R2, R3, R4 // c23124e1
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MULAWB R1, R2, R3, R4 // 823124e1
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MULAWB R1, R2, R3, R4 // 823124e1
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MULS R1, R2, R3, R4 // 923164e0
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MULS R1, R2, R3, R4 // 923164e0
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MULA R1, R2, R3, R4 // 923124e0
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MULA.S R1, R2, R3, R4 // 923134e0
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MMULA R1, R2, R3, R4 // 123154e7
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MMULA R1, R2, R3, R4 // 123154e7
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MMULS R1, R2, R3, R4 // d23154e7
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MMULS R1, R2, R3, R4 // d23154e7
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MULABB R1, R2, R3, R4 // 823104e1
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MULABB R1, R2, R3, R4 // 823104e1
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@ -165,7 +165,6 @@ var optab = []Optab{
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{ADIVHW, C_REG, C_REG, C_REG, 105, 4, 0, 0, 0},
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{ADIVHW, C_REG, C_REG, C_REG, 105, 4, 0, 0, 0},
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{ADIVHW, C_REG, C_NONE, C_REG, 105, 4, 0, 0, 0},
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{ADIVHW, C_REG, C_NONE, C_REG, 105, 4, 0, 0, 0},
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{AMULL, C_REG, C_REG, C_REGREG, 17, 4, 0, 0, 0},
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{AMULL, C_REG, C_REG, C_REGREG, 17, 4, 0, 0, 0},
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{AMULA, C_REG, C_REG, C_REGREG2, 17, 4, 0, 0, 0},
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{AMOVW, C_REG, C_NONE, C_SAUTO, 20, 4, REGSP, 0, 0},
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{AMOVW, C_REG, C_NONE, C_SAUTO, 20, 4, REGSP, 0, 0},
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{AMOVW, C_REG, C_NONE, C_SOREG, 20, 4, 0, 0, 0},
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{AMOVW, C_REG, C_NONE, C_SOREG, 20, 4, 0, 0, 0},
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{AMOVB, C_REG, C_NONE, C_SAUTO, 20, 4, REGSP, 0, 0},
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{AMOVB, C_REG, C_NONE, C_SAUTO, 20, 4, REGSP, 0, 0},
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@ -1526,6 +1525,7 @@ func buildop(ctxt *obj.Link) {
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case AMULAWT:
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case AMULAWT:
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opset(AMULAWB, r0)
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opset(AMULAWB, r0)
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opset(AMULABB, r0)
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opset(AMULABB, r0)
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opset(AMULA, r0)
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opset(AMULS, r0)
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opset(AMULS, r0)
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opset(AMMULA, r0)
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opset(AMMULA, r0)
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opset(AMMULS, r0)
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opset(AMMULS, r0)
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@ -1536,12 +1536,10 @@ func buildop(ctxt *obj.Link) {
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opset(AREVSH, r0)
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opset(AREVSH, r0)
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opset(ARBIT, r0)
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opset(ARBIT, r0)
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case AMULA,
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case ALDREX,
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ALDREX,
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ASTREX,
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ASTREX,
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ALDREXD,
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ALDREXD,
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ASTREXD,
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ASTREXD,
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ATST,
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APLD,
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APLD,
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obj.AUNDEF,
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obj.AUNDEF,
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obj.AFUNCDATA,
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obj.AFUNCDATA,
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@ -2489,10 +2487,10 @@ func (c *ctxt5) asmout(p *obj.Prog, o *Optab, out []uint32) {
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case 99: /* MULAW{T,B} Rs, Rm, Rn, Rd */
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case 99: /* MULAW{T,B} Rs, Rm, Rn, Rd */
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o1 = c.oprrr(p, p.As, int(p.Scond))
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o1 = c.oprrr(p, p.As, int(p.Scond))
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o1 |= (uint32(p.To.Reg) & 15) << 12
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o1 |= (uint32(p.To.Reg) & 15) << 16
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o1 |= (uint32(p.From.Reg) & 15) << 8
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o1 |= (uint32(p.From.Reg) & 15) << 8
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o1 |= (uint32(p.Reg) & 15) << 0
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o1 |= (uint32(p.Reg) & 15) << 0
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o1 |= uint32((p.To.Offset & 15) << 16)
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o1 |= uint32((p.To.Offset & 15) << 12)
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// DATABUNDLE: BKPT $0x5be0, signify the start of NaCl data bundle;
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// DATABUNDLE: BKPT $0x5be0, signify the start of NaCl data bundle;
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// DATABUNDLEEND: zero width alignment marker
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// DATABUNDLEEND: zero width alignment marker
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@ -240,7 +240,7 @@ func Dconv(p *Prog, a *Addr) string {
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str = fmt.Sprintf("(%v, %v)", Rconv(int(a.Reg)), Rconv(int(a.Offset)))
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str = fmt.Sprintf("(%v, %v)", Rconv(int(a.Reg)), Rconv(int(a.Offset)))
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case TYPE_REGREG2:
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case TYPE_REGREG2:
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str = fmt.Sprintf("%v, %v", Rconv(int(a.Reg)), Rconv(int(a.Offset)))
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str = fmt.Sprintf("%v, %v", Rconv(int(a.Offset)), Rconv(int(a.Reg)))
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case TYPE_REGLIST:
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case TYPE_REGLIST:
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str = regListConv(int(a.Offset))
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str = regListConv(int(a.Offset))
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