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cmd/compile: start on ARM port
Start working on arm port. Gets close to correct
code for fibonacci:
func fib(n int) int {
if n < 2 {
return n
}
return fib(n-1) + fib(n-2)
}
Still a lot to do, but this is a good starting point.
Cleaned up some arch-specific dependencies in regalloc.
Change-Id: I4301c6c31a8402168e50dcfee8bcf7aee73ea9d5
Reviewed-on: https://go-review.googlesource.com/21000
Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Keith Randall
parent
44d3f89e99
commit
4c9a470d46
13 changed files with 807 additions and 73 deletions
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@ -129,10 +129,11 @@ type regMask uint64
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func (m regMask) String() string {
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s := ""
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for r := register(0); r < numRegs; r++ {
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for r := register(0); m != 0; r++ {
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if m>>r&1 == 0 {
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continue
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}
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m &^= regMask(1) << r
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if s != "" {
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s += " "
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}
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@ -141,47 +142,6 @@ func (m regMask) String() string {
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return s
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}
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// TODO: make arch-dependent
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var numRegs register = 64
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var registers = [...]Register{
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Register{0, "AX"},
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Register{1, "CX"},
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Register{2, "DX"},
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Register{3, "BX"},
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Register{4, "SP"},
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Register{5, "BP"},
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Register{6, "SI"},
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Register{7, "DI"},
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Register{8, "R8"},
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Register{9, "R9"},
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Register{10, "R10"},
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Register{11, "R11"},
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Register{12, "R12"},
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Register{13, "R13"},
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Register{14, "R14"},
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Register{15, "R15"},
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Register{16, "X0"},
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Register{17, "X1"},
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Register{18, "X2"},
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Register{19, "X3"},
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Register{20, "X4"},
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Register{21, "X5"},
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Register{22, "X6"},
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Register{23, "X7"},
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Register{24, "X8"},
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Register{25, "X9"},
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Register{26, "X10"},
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Register{27, "X11"},
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Register{28, "X12"},
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Register{29, "X13"},
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Register{30, "X14"},
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Register{31, "X15"},
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Register{32, "SB"}, // pseudo-register for global base pointer (aka %rip)
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// TODO: make arch-dependent
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}
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// countRegs returns the number of set bits in the register mask.
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func countRegs(r regMask) int {
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n := 0
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@ -231,6 +191,11 @@ type regState struct {
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type regAllocState struct {
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f *Func
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registers []Register
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numRegs register
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SPReg register
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SBReg register
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// for each block, its primary predecessor.
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// A predecessor of b is primary if it is the closest
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// predecessor that appears before b in the layout order.
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@ -298,7 +263,7 @@ func (s *regAllocState) freeReg(r register) {
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// Mark r as unused.
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if s.f.pass.debug > regDebug {
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fmt.Printf("freeReg %s (dump %s/%s)\n", registers[r].Name(), v, s.regs[r].c)
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fmt.Printf("freeReg %s (dump %s/%s)\n", s.registers[r].Name(), v, s.regs[r].c)
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}
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s.regs[r] = regState{}
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s.values[v.ID].regs &^= regMask(1) << r
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@ -328,7 +293,7 @@ func (s *regAllocState) setOrig(c *Value, v *Value) {
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// r must be unused.
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func (s *regAllocState) assignReg(r register, v *Value, c *Value) {
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if s.f.pass.debug > regDebug {
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fmt.Printf("assignReg %s %s/%s\n", registers[r].Name(), v, c)
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fmt.Printf("assignReg %s %s/%s\n", s.registers[r].Name(), v, c)
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}
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if s.regs[r].v != nil {
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s.f.Fatalf("tried to assign register %d to %s/%s but it is already used by %s", r, v, c, s.regs[r].v)
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@ -338,7 +303,7 @@ func (s *regAllocState) assignReg(r register, v *Value, c *Value) {
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s.regs[r] = regState{v, c}
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s.values[v.ID].regs |= regMask(1) << r
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s.used |= regMask(1) << r
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s.f.setHome(c, ®isters[r])
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s.f.setHome(c, &s.registers[r])
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}
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// allocReg chooses a register for v from the set of registers in mask.
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@ -377,14 +342,14 @@ func (s *regAllocState) allocReg(v *Value, mask regMask) register {
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// SP and SB are allocated specially. No regular value should
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// be allocated to them.
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mask &^= 1<<4 | 1<<32
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mask &^= 1<<s.SPReg | 1<<s.SBReg
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// Find a register to spill. We spill the register containing the value
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// whose next use is as far in the future as possible.
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// https://en.wikipedia.org/wiki/Page_replacement_algorithm#The_theoretically_optimal_page_replacement_algorithm
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var r register
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maxuse := int32(-1)
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for t := register(0); t < numRegs; t++ {
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for t := register(0); t < s.numRegs; t++ {
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if mask>>t&1 == 0 {
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continue
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}
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@ -425,10 +390,10 @@ func (s *regAllocState) allocValToReg(v *Value, mask regMask, nospill bool, line
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}
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if v.Op != OpSP {
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mask &^= 1 << 4 // dont' spill SP
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mask &^= 1 << s.SPReg // dont' spill SP
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}
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if v.Op != OpSB {
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mask &^= 1 << 32 // don't spill SB
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mask &^= 1 << s.SBReg // don't spill SB
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}
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mask &^= s.reserved()
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@ -469,12 +434,22 @@ func (s *regAllocState) allocValToReg(v *Value, mask regMask, nospill bool, line
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}
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func (s *regAllocState) init(f *Func) {
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if numRegs > noRegister || numRegs > register(unsafe.Sizeof(regMask(0))*8) {
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s.registers = f.Config.registers
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s.numRegs = register(len(s.registers))
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if s.numRegs > noRegister || s.numRegs > register(unsafe.Sizeof(regMask(0))*8) {
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panic("too many registers")
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}
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for r := register(0); r < s.numRegs; r++ {
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if s.registers[r].Name() == "SP" {
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s.SPReg = r
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}
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if s.registers[r].Name() == "SB" {
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s.SBReg = r
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}
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}
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s.f = f
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s.regs = make([]regState, numRegs)
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s.regs = make([]regState, s.numRegs)
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s.values = make([]valState, f.NumValues())
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s.orig = make([]*Value, f.NumValues())
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for _, b := range f.Blocks {
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@ -663,7 +638,7 @@ func (s *regAllocState) regalloc(f *Func) {
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// Drop any values which are no longer live.
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// This may happen because at the end of p, a value may be
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// live but only used by some other successor of p.
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for r := register(0); r < numRegs; r++ {
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for r := register(0); r < s.numRegs; r++ {
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v := s.regs[r].v
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if v != nil && !liveSet.contains(v.ID) {
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s.freeReg(r)
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@ -687,7 +662,7 @@ func (s *regAllocState) regalloc(f *Func) {
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if s.f.pass.debug > regDebug {
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fmt.Printf("starting merge block %s with end state of %s:\n", b, p)
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for _, x := range s.endRegs[p.ID] {
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fmt.Printf(" %s: orig:%s cache:%s\n", registers[x.r].Name(), x.v, x.c)
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fmt.Printf(" %s: orig:%s cache:%s\n", s.registers[x.r].Name(), x.v, x.c)
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}
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}
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@ -769,7 +744,7 @@ func (s *regAllocState) regalloc(f *Func) {
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// Save the starting state for use by merge edges.
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var regList []startReg
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for r := register(0); r < numRegs; r++ {
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for r := register(0); r < s.numRegs; r++ {
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v := s.regs[r].v
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if v == nil {
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continue
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@ -786,7 +761,7 @@ func (s *regAllocState) regalloc(f *Func) {
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if s.f.pass.debug > regDebug {
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fmt.Printf("after phis\n")
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for _, x := range s.startRegs[b.ID] {
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fmt.Printf(" %s: v%d\n", registers[x.r].Name(), x.vid)
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fmt.Printf(" %s: v%d\n", s.registers[x.r].Name(), x.vid)
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}
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}
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}
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@ -866,13 +841,13 @@ func (s *regAllocState) regalloc(f *Func) {
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f.Fatalf("phi %s not at start of block", v)
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}
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if v.Op == OpSP {
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s.assignReg(4, v, v) // TODO: arch-dependent
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s.assignReg(s.SPReg, v, v)
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b.Values = append(b.Values, v)
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s.advanceUses(v)
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continue
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}
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if v.Op == OpSB {
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s.assignReg(32, v, v) // TODO: arch-dependent
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s.assignReg(s.SBReg, v, v)
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b.Values = append(b.Values, v)
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s.advanceUses(v)
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continue
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@ -1030,7 +1005,7 @@ func (s *regAllocState) regalloc(f *Func) {
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// Save end-of-block register state.
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// First count how many, this cuts allocations in half.
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k := 0
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for r := register(0); r < numRegs; r++ {
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for r := register(0); r < s.numRegs; r++ {
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v := s.regs[r].v
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if v == nil {
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continue
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@ -1038,7 +1013,7 @@ func (s *regAllocState) regalloc(f *Func) {
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k++
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}
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regList := make([]endReg, 0, k)
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for r := register(0); r < numRegs; r++ {
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for r := register(0); r < s.numRegs; r++ {
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v := s.regs[r].v
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if v == nil {
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continue
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@ -1053,7 +1028,7 @@ func (s *regAllocState) regalloc(f *Func) {
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for _, x := range s.live[b.ID] {
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liveSet.add(x.ID)
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}
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for r := register(0); r < numRegs; r++ {
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for r := register(0); r < s.numRegs; r++ {
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v := s.regs[r].v
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if v == nil {
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continue
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@ -1214,7 +1189,7 @@ func (e *edgeState) setup(idx int, srcReg []endReg, dstReg []startReg, stacklive
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// Live registers can be sources.
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for _, x := range srcReg {
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e.set(®isters[x.r], x.v.ID, x.c, false)
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e.set(&e.s.registers[x.r], x.v.ID, x.c, false)
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}
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// So can all of the spill locations.
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for _, spillID := range stacklive {
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@ -1226,7 +1201,7 @@ func (e *edgeState) setup(idx int, srcReg []endReg, dstReg []startReg, stacklive
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// Figure out all the destinations we need.
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dsts := e.destinations[:0]
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for _, x := range dstReg {
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dsts = append(dsts, dstRecord{®isters[x.r], x.vid, nil})
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dsts = append(dsts, dstRecord{&e.s.registers[x.r], x.vid, nil})
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}
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// Phis need their args to end up in a specific location.
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for _, v := range e.b.Values {
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@ -1519,15 +1494,15 @@ func (e *edgeState) findRegFor(typ Type) Location {
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// 3) a non-unique register
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x := m &^ e.usedRegs
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if x != 0 {
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return ®isters[pickReg(x)]
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return &e.s.registers[pickReg(x)]
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}
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x = m &^ e.uniqueRegs &^ e.finalRegs
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if x != 0 {
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return ®isters[pickReg(x)]
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return &e.s.registers[pickReg(x)]
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}
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x = m &^ e.uniqueRegs
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if x != 0 {
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return ®isters[pickReg(x)]
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return &e.s.registers[pickReg(x)]
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}
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// No register is available. Allocate a temp location to spill a register to.
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