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cmd/compile: use generated loops instead of DUFFCOPY on riscv64
MemmoveKnownSize112-4 632.1Mi ± 1% 1288.5Mi ± 0% +103.85% (p=0.000 n=10) MemmoveKnownSize128-4 636.1Mi ± 0% 1280.9Mi ± 1% +101.36% (p=0.000 n=10) MemmoveKnownSize192-4 645.3Mi ± 0% 1306.9Mi ± 1% +102.53% (p=0.000 n=10) MemmoveKnownSize248-4 650.2Mi ± 2% 1312.5Mi ± 1% +101.87% (p=0.000 n=10) MemmoveKnownSize256-4 650.7Mi ± 0% 1303.6Mi ± 1% +100.33% (p=0.000 n=10) MemmoveKnownSize512-4 658.2Mi ± 1% 1293.9Mi ± 0% +96.60% (p=0.000 n=10) MemmoveKnownSize1024-4 662.1Mi ± 0% 1312.6Mi ± 0% +98.26% (p=0.000 n=10) Change-Id: I43681ca029880025558b33ddc4295da3947c9b28 Reviewed-on: https://go-review.googlesource.com/c/go/+/700537 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Mark Freeman <markfreeman@google.com>
This commit is contained in:
Meng Zhuo
parent
879ff736d3
commit
4dac9e093f
5 changed files with 186 additions and 222 deletions
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@ -822,44 +822,99 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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}
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case ssa.OpRISCV64LoweredMove:
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mov, sz := largestMove(v.AuxInt)
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dst := v.Args[0].Reg()
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src := v.Args[1].Reg()
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if dst == src {
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break
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}
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// mov (Rarg1), T2
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// mov T2, (Rarg0)
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// ADD $sz, Rarg0
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// ADD $sz, Rarg1
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// BGEU Rarg2, Rarg0, -4(PC)
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sa := v.AuxValAndOff()
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n := sa.Val64()
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mov, sz := largestMove(sa.Off64())
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p := s.Prog(mov)
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[1].Reg()
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var off int64
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tmp := int16(riscv.REG_X5)
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for n >= sz {
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moveOp(s, mov, dst, src, tmp, off)
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off += sz
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n -= sz
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}
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for i := len(fracMovOps) - 1; i >= 0; i-- {
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tsz := int64(1 << i)
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if n < tsz {
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continue
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}
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moveOp(s, fracMovOps[i], dst, src, tmp, off)
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off += tsz
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n -= tsz
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}
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case ssa.OpRISCV64LoweredMoveLoop:
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dst := v.Args[0].Reg()
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src := v.Args[1].Reg()
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if dst == src {
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break
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}
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sc := v.AuxValAndOff()
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n := sc.Val64()
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mov, sz := largestMove(sc.Off64())
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chunk := 8 * sz
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if n <= 3*chunk {
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v.Fatalf("MoveLoop too small:%d, expect:%d", n, 3*chunk)
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}
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tmp := int16(riscv.REG_X5)
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p := s.Prog(riscv.AADD)
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = n - n%chunk
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p.Reg = src
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p.To.Type = obj.TYPE_REG
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p.To.Reg = riscv.REG_T2
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p.To.Reg = riscv.REG_X6
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p2 := s.Prog(mov)
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p2.From.Type = obj.TYPE_REG
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p2.From.Reg = riscv.REG_T2
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p2.To.Type = obj.TYPE_MEM
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p2.To.Reg = v.Args[0].Reg()
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for i := int64(0); i < 8; i++ {
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moveOp(s, mov, dst, src, tmp, sz*i)
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}
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p3 := s.Prog(riscv.AADD)
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p3.From.Type = obj.TYPE_CONST
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p3.From.Offset = sz
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p3.To.Type = obj.TYPE_REG
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p3.To.Reg = v.Args[0].Reg()
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p1 := s.Prog(riscv.AADD)
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p1.From.Type = obj.TYPE_CONST
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p1.From.Offset = chunk
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p1.To.Type = obj.TYPE_REG
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p1.To.Reg = src
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p4 := s.Prog(riscv.AADD)
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p4.From.Type = obj.TYPE_CONST
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p4.From.Offset = sz
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p4.To.Type = obj.TYPE_REG
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p4.To.Reg = v.Args[1].Reg()
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p2 := s.Prog(riscv.AADD)
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p2.From.Type = obj.TYPE_CONST
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p2.From.Offset = chunk
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p2.To.Type = obj.TYPE_REG
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p2.To.Reg = dst
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p5 := s.Prog(riscv.ABGEU)
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p5.To.Type = obj.TYPE_BRANCH
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p5.Reg = v.Args[1].Reg()
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p5.From.Type = obj.TYPE_REG
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p5.From.Reg = v.Args[2].Reg()
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p5.To.SetTarget(p)
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p3 := s.Prog(riscv.ABNE)
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p3.From.Reg = riscv.REG_X6
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p3.From.Type = obj.TYPE_REG
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p3.Reg = src
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p3.To.Type = obj.TYPE_BRANCH
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p3.To.SetTarget(p.Link)
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n %= chunk
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var off int64
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for n >= sz {
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moveOp(s, mov, dst, src, tmp, off)
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off += sz
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n -= sz
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}
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for i := len(fracMovOps) - 1; i >= 0; i-- {
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tsz := int64(1 << i)
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if n < tsz {
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continue
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}
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moveOp(s, fracMovOps[i], dst, src, tmp, off)
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off += tsz
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n -= tsz
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}
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case ssa.OpRISCV64LoweredNilCheck:
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// Issue a load which will fault if arg is nil.
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@ -1023,3 +1078,21 @@ func zeroOp(s *ssagen.State, mov obj.As, reg int16, off int64) {
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p.To.Offset = off
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return
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}
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func moveOp(s *ssagen.State, mov obj.As, dst int16, src int16, tmp int16, off int64) {
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p := s.Prog(mov)
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = src
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p.From.Offset = off
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p.To.Type = obj.TYPE_REG
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p.To.Reg = tmp
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p1 := s.Prog(mov)
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p1.From.Type = obj.TYPE_REG
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p1.From.Reg = tmp
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p1.To.Type = obj.TYPE_MEM
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p1.To.Reg = dst
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p1.To.Offset = off
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return
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}
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@ -442,37 +442,16 @@
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(MOVHstore [4] dst (MOVHload [4] src mem)
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(MOVHstore [2] dst (MOVHload [2] src mem)
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(MOVHstore dst (MOVHload src mem) mem)))
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(Move [12] {t} dst src mem) && t.Alignment()%4 == 0 =>
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(MOVWstore [8] dst (MOVWload [8] src mem)
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(MOVWstore [4] dst (MOVWload [4] src mem)
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(MOVWstore dst (MOVWload src mem) mem)))
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(Move [16] {t} dst src mem) && t.Alignment()%8 == 0 =>
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(MOVDstore [8] dst (MOVDload [8] src mem)
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(MOVDstore dst (MOVDload src mem) mem))
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(Move [24] {t} dst src mem) && t.Alignment()%8 == 0 =>
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(MOVDstore [16] dst (MOVDload [16] src mem)
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(MOVDstore [8] dst (MOVDload [8] src mem)
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(MOVDstore dst (MOVDload src mem) mem)))
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(Move [32] {t} dst src mem) && t.Alignment()%8 == 0 =>
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(MOVDstore [24] dst (MOVDload [24] src mem)
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(MOVDstore [16] dst (MOVDload [16] src mem)
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(MOVDstore [8] dst (MOVDload [8] src mem)
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(MOVDstore dst (MOVDload src mem) mem))))
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// Medium 8-aligned move uses a Duff's device
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// 16 and 128 are magic constants, see runtime/mkduff.go
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(Move [s] {t} dst src mem)
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&& s%8 == 0 && s <= 8*128 && t.Alignment()%8 == 0
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// Generic move
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(Move [s] {t} dst src mem) && s > 0 && s <= 3*8*moveSize(t.Alignment(), config)
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&& logLargeCopy(v, s) =>
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(DUFFCOPY [16 * (128 - s/8)] dst src mem)
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(LoweredMove [makeValAndOff(int32(s),int32(t.Alignment()))] dst src mem)
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// Generic move uses a loop
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(Move [s] {t} dst src mem) && (s <= 16 || logLargeCopy(v, s)) =>
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(LoweredMove [t.Alignment()]
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dst
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src
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(ADDI <src.Type> [s-moveSize(t.Alignment(), config)] src)
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mem)
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(Move [s] {t} dst src mem) && s > 3*8*moveSize(t.Alignment(), config)
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&& logLargeCopy(v, s) =>
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(LoweredMoveLoop [makeValAndOff(int32(s),int32(t.Alignment()))] dst src mem)
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// Boolean ops; 0=false, 1=true
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(AndB ...) => (AND ...)
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@ -117,6 +117,7 @@ func init() {
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regCtxt := regNamed["X26"]
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callerSave := gpMask | fpMask | regNamed["g"]
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r5toR6 := regNamed["X5"] | regNamed["X6"]
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var (
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gpstore = regInfo{inputs: []regMask{gpspsbMask, gpspMask, 0}} // SB in first input so we can load from a global, but not in second to avoid using SB as a temporary register
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@ -354,27 +355,51 @@ func init() {
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},
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// general unaligned move
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// arg0 = address of dst memory (in X5, changed as side effect)
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// arg1 = address of src memory (in X6, changed as side effect)
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// arg2 = address of the last element of src (can't be X7 as we clobber it before using arg2)
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// arg3 = mem
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// auxint = alignment
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// clobbers X7 as a tmp register.
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// arg0 = address of dst memory (clobber)
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// arg1 = address of src memory (clobber)
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// arg2 = mem
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// auxint = size and type alignment
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// returns mem
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// mov (X6), X7
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// mov X7, (X5)
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// ADD $sz, X5
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// ADD $sz, X6
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// BGEU Rarg2, X5, -4(PC)
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// mov (offset)(Rarg1), TMP
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// mov TMP, (offset)(Rarg0)
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{
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name: "LoweredMove",
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aux: "Int64",
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argLength: 4,
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aux: "SymValAndOff",
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symEffect: "Write",
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argLength: 3,
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reg: regInfo{
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inputs: []regMask{regNamed["X5"], regNamed["X6"], gpMask &^ regNamed["X7"]},
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clobbers: regNamed["X5"] | regNamed["X6"] | regNamed["X7"],
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inputs: []regMask{gpMask &^ regNamed["X5"], gpMask &^ regNamed["X5"]},
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clobbers: regNamed["X5"],
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},
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faultOnNilArg0: true,
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faultOnNilArg1: true,
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},
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// general unaligned move
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// arg0 = address of dst memory (clobber)
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// arg1 = address of src memory (clobber)
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// arg3 = mem
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// auxint = alignment
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// returns mem
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// ADD $sz, X6
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//loop:
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// mov (Rarg1), X5
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// mov X5, (Rarg0)
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// ...rest 7 mov...
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// ADD $sz, Rarg0
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// ADD $sz, Rarg1
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// BNE X6, Rarg1, loop
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{
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name: "LoweredMoveLoop",
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aux: "SymValAndOff",
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argLength: 3,
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symEffect: "Write",
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reg: regInfo{
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inputs: []regMask{gpMask &^ r5toR6, gpMask &^ r5toR6},
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clobbers: r5toR6,
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clobbersArg0: true,
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clobbersArg1: true,
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},
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typ: "Mem",
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faultOnNilArg0: true,
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faultOnNilArg1: true,
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},
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@ -2571,6 +2571,7 @@ const (
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OpRISCV64LoweredZero
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OpRISCV64LoweredZeroLoop
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OpRISCV64LoweredMove
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OpRISCV64LoweredMoveLoop
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OpRISCV64LoweredAtomicLoad8
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OpRISCV64LoweredAtomicLoad32
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OpRISCV64LoweredAtomicLoad64
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@ -34585,17 +34586,34 @@ var opcodeTable = [...]opInfo{
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},
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{
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name: "LoweredMove",
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auxType: auxInt64,
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argLen: 4,
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auxType: auxSymValAndOff,
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argLen: 3,
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faultOnNilArg0: true,
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faultOnNilArg1: true,
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symEffect: SymWrite,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 16}, // X5
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{1, 32}, // X6
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{2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
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{0, 1006632928}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
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{1, 1006632928}, // X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
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},
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clobbers: 112, // X5 X6 X7
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clobbers: 16, // X5
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},
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},
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{
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name: "LoweredMoveLoop",
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auxType: auxSymValAndOff,
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argLen: 3,
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faultOnNilArg0: true,
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faultOnNilArg1: true,
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symEffect: SymWrite,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1006632896}, // X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
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{1, 1006632896}, // X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
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},
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clobbers: 48, // X5 X6
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clobbersArg0: true,
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clobbersArg1: true,
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},
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},
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{
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@ -3090,169 +3090,38 @@ func rewriteValueRISCV64_OpMove(v *Value) bool {
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v.AddArg3(dst, v0, v1)
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return true
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}
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// match: (Move [12] {t} dst src mem)
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// cond: t.Alignment()%4 == 0
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// result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVWstore [4] dst (MOVWload [4] src mem) (MOVWstore dst (MOVWload src mem) mem)))
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for {
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if auxIntToInt64(v.AuxInt) != 12 {
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break
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}
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t := auxToType(v.Aux)
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dst := v_0
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src := v_1
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mem := v_2
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if !(t.Alignment()%4 == 0) {
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break
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}
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v.reset(OpRISCV64MOVWstore)
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v.AuxInt = int32ToAuxInt(8)
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v0 := b.NewValue0(v.Pos, OpRISCV64MOVWload, typ.Int32)
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v0.AuxInt = int32ToAuxInt(8)
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v0.AddArg2(src, mem)
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v1 := b.NewValue0(v.Pos, OpRISCV64MOVWstore, types.TypeMem)
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v1.AuxInt = int32ToAuxInt(4)
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v2 := b.NewValue0(v.Pos, OpRISCV64MOVWload, typ.Int32)
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v2.AuxInt = int32ToAuxInt(4)
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v2.AddArg2(src, mem)
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v3 := b.NewValue0(v.Pos, OpRISCV64MOVWstore, types.TypeMem)
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v4 := b.NewValue0(v.Pos, OpRISCV64MOVWload, typ.Int32)
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v4.AddArg2(src, mem)
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v3.AddArg3(dst, v4, mem)
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v1.AddArg3(dst, v2, v3)
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v.AddArg3(dst, v0, v1)
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return true
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}
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// match: (Move [16] {t} dst src mem)
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// cond: t.Alignment()%8 == 0
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// result: (MOVDstore [8] dst (MOVDload [8] src mem) (MOVDstore dst (MOVDload src mem) mem))
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for {
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if auxIntToInt64(v.AuxInt) != 16 {
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break
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}
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t := auxToType(v.Aux)
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dst := v_0
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src := v_1
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mem := v_2
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if !(t.Alignment()%8 == 0) {
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break
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}
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v.reset(OpRISCV64MOVDstore)
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v.AuxInt = int32ToAuxInt(8)
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v0 := b.NewValue0(v.Pos, OpRISCV64MOVDload, typ.Int64)
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v0.AuxInt = int32ToAuxInt(8)
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v0.AddArg2(src, mem)
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v1 := b.NewValue0(v.Pos, OpRISCV64MOVDstore, types.TypeMem)
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v2 := b.NewValue0(v.Pos, OpRISCV64MOVDload, typ.Int64)
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v2.AddArg2(src, mem)
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v1.AddArg3(dst, v2, mem)
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v.AddArg3(dst, v0, v1)
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return true
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}
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// match: (Move [24] {t} dst src mem)
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// cond: t.Alignment()%8 == 0
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// result: (MOVDstore [16] dst (MOVDload [16] src mem) (MOVDstore [8] dst (MOVDload [8] src mem) (MOVDstore dst (MOVDload src mem) mem)))
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for {
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if auxIntToInt64(v.AuxInt) != 24 {
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break
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}
|
||||
t := auxToType(v.Aux)
|
||||
dst := v_0
|
||||
src := v_1
|
||||
mem := v_2
|
||||
if !(t.Alignment()%8 == 0) {
|
||||
break
|
||||
}
|
||||
v.reset(OpRISCV64MOVDstore)
|
||||
v.AuxInt = int32ToAuxInt(16)
|
||||
v0 := b.NewValue0(v.Pos, OpRISCV64MOVDload, typ.Int64)
|
||||
v0.AuxInt = int32ToAuxInt(16)
|
||||
v0.AddArg2(src, mem)
|
||||
v1 := b.NewValue0(v.Pos, OpRISCV64MOVDstore, types.TypeMem)
|
||||
v1.AuxInt = int32ToAuxInt(8)
|
||||
v2 := b.NewValue0(v.Pos, OpRISCV64MOVDload, typ.Int64)
|
||||
v2.AuxInt = int32ToAuxInt(8)
|
||||
v2.AddArg2(src, mem)
|
||||
v3 := b.NewValue0(v.Pos, OpRISCV64MOVDstore, types.TypeMem)
|
||||
v4 := b.NewValue0(v.Pos, OpRISCV64MOVDload, typ.Int64)
|
||||
v4.AddArg2(src, mem)
|
||||
v3.AddArg3(dst, v4, mem)
|
||||
v1.AddArg3(dst, v2, v3)
|
||||
v.AddArg3(dst, v0, v1)
|
||||
return true
|
||||
}
|
||||
// match: (Move [32] {t} dst src mem)
|
||||
// cond: t.Alignment()%8 == 0
|
||||
// result: (MOVDstore [24] dst (MOVDload [24] src mem) (MOVDstore [16] dst (MOVDload [16] src mem) (MOVDstore [8] dst (MOVDload [8] src mem) (MOVDstore dst (MOVDload src mem) mem))))
|
||||
for {
|
||||
if auxIntToInt64(v.AuxInt) != 32 {
|
||||
break
|
||||
}
|
||||
t := auxToType(v.Aux)
|
||||
dst := v_0
|
||||
src := v_1
|
||||
mem := v_2
|
||||
if !(t.Alignment()%8 == 0) {
|
||||
break
|
||||
}
|
||||
v.reset(OpRISCV64MOVDstore)
|
||||
v.AuxInt = int32ToAuxInt(24)
|
||||
v0 := b.NewValue0(v.Pos, OpRISCV64MOVDload, typ.Int64)
|
||||
v0.AuxInt = int32ToAuxInt(24)
|
||||
v0.AddArg2(src, mem)
|
||||
v1 := b.NewValue0(v.Pos, OpRISCV64MOVDstore, types.TypeMem)
|
||||
v1.AuxInt = int32ToAuxInt(16)
|
||||
v2 := b.NewValue0(v.Pos, OpRISCV64MOVDload, typ.Int64)
|
||||
v2.AuxInt = int32ToAuxInt(16)
|
||||
v2.AddArg2(src, mem)
|
||||
v3 := b.NewValue0(v.Pos, OpRISCV64MOVDstore, types.TypeMem)
|
||||
v3.AuxInt = int32ToAuxInt(8)
|
||||
v4 := b.NewValue0(v.Pos, OpRISCV64MOVDload, typ.Int64)
|
||||
v4.AuxInt = int32ToAuxInt(8)
|
||||
v4.AddArg2(src, mem)
|
||||
v5 := b.NewValue0(v.Pos, OpRISCV64MOVDstore, types.TypeMem)
|
||||
v6 := b.NewValue0(v.Pos, OpRISCV64MOVDload, typ.Int64)
|
||||
v6.AddArg2(src, mem)
|
||||
v5.AddArg3(dst, v6, mem)
|
||||
v3.AddArg3(dst, v4, v5)
|
||||
v1.AddArg3(dst, v2, v3)
|
||||
v.AddArg3(dst, v0, v1)
|
||||
return true
|
||||
}
|
||||
// match: (Move [s] {t} dst src mem)
|
||||
// cond: s%8 == 0 && s <= 8*128 && t.Alignment()%8 == 0 && logLargeCopy(v, s)
|
||||
// result: (DUFFCOPY [16 * (128 - s/8)] dst src mem)
|
||||
// cond: s > 0 && s <= 3*8*moveSize(t.Alignment(), config) && logLargeCopy(v, s)
|
||||
// result: (LoweredMove [makeValAndOff(int32(s),int32(t.Alignment()))] dst src mem)
|
||||
for {
|
||||
s := auxIntToInt64(v.AuxInt)
|
||||
t := auxToType(v.Aux)
|
||||
dst := v_0
|
||||
src := v_1
|
||||
mem := v_2
|
||||
if !(s%8 == 0 && s <= 8*128 && t.Alignment()%8 == 0 && logLargeCopy(v, s)) {
|
||||
if !(s > 0 && s <= 3*8*moveSize(t.Alignment(), config) && logLargeCopy(v, s)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpRISCV64DUFFCOPY)
|
||||
v.AuxInt = int64ToAuxInt(16 * (128 - s/8))
|
||||
v.reset(OpRISCV64LoweredMove)
|
||||
v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(s), int32(t.Alignment())))
|
||||
v.AddArg3(dst, src, mem)
|
||||
return true
|
||||
}
|
||||
// match: (Move [s] {t} dst src mem)
|
||||
// cond: (s <= 16 || logLargeCopy(v, s))
|
||||
// result: (LoweredMove [t.Alignment()] dst src (ADDI <src.Type> [s-moveSize(t.Alignment(), config)] src) mem)
|
||||
// cond: s > 3*8*moveSize(t.Alignment(), config) && logLargeCopy(v, s)
|
||||
// result: (LoweredMoveLoop [makeValAndOff(int32(s),int32(t.Alignment()))] dst src mem)
|
||||
for {
|
||||
s := auxIntToInt64(v.AuxInt)
|
||||
t := auxToType(v.Aux)
|
||||
dst := v_0
|
||||
src := v_1
|
||||
mem := v_2
|
||||
if !(s <= 16 || logLargeCopy(v, s)) {
|
||||
if !(s > 3*8*moveSize(t.Alignment(), config) && logLargeCopy(v, s)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpRISCV64LoweredMove)
|
||||
v.AuxInt = int64ToAuxInt(t.Alignment())
|
||||
v0 := b.NewValue0(v.Pos, OpRISCV64ADDI, src.Type)
|
||||
v0.AuxInt = int64ToAuxInt(s - moveSize(t.Alignment(), config))
|
||||
v0.AddArg(src)
|
||||
v.AddArg4(dst, src, v0, mem)
|
||||
v.reset(OpRISCV64LoweredMoveLoop)
|
||||
v.AuxInt = valAndOffToAuxInt(makeValAndOff(int32(s), int32(t.Alignment())))
|
||||
v.AddArg3(dst, src, mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue