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[dev.simd] cmd/compile: change register mask names for simd ops
This CL contains codes generated by CL 686556. Change-Id: I4d7287476b478efdc186a64c12de33528c7fb0af Reviewed-on: https://go-review.googlesource.com/c/go/+/686476 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
This commit is contained in:
Junyang Shao
David Chase
parent
029d7ec3e9
commit
5429328b0c
4 changed files with 1000 additions and 959 deletions
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@ -54,7 +54,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VSQRTPD128,
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ssa.OpAMD64VSQRTPD256,
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ssa.OpAMD64VSQRTPD512:
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p = simdFp11(s, v)
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p = simdV11(s, v)
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case ssa.OpAMD64VADDPS128,
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ssa.OpAMD64VADDPS256,
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@ -318,7 +318,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPXOR256,
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ssa.OpAMD64VPXORD512,
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ssa.OpAMD64VPXORQ512:
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p = simdFp21(s, v)
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p = simdV21(s, v)
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case ssa.OpAMD64VADDPSMasked128,
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ssa.OpAMD64VADDPSMasked256,
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@ -545,7 +545,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPXORQMasked128,
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ssa.OpAMD64VPXORQMasked256,
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ssa.OpAMD64VPXORQMasked512:
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p = simdFp2kfp(s, v)
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p = simdV2kv(s, v)
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case ssa.OpAMD64VPABSBMasked128,
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ssa.OpAMD64VPABSBMasked256,
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@ -589,7 +589,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VSQRTPDMasked128,
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ssa.OpAMD64VSQRTPDMasked256,
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ssa.OpAMD64VSQRTPDMasked512:
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p = simdFpkfp(s, v)
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p = simdVkv(s, v)
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case ssa.OpAMD64VROUNDPS128,
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ssa.OpAMD64VROUNDPS256,
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@ -621,7 +621,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPRORQ128,
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ssa.OpAMD64VPRORQ256,
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ssa.OpAMD64VPRORQ512:
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p = simdFp11Imm8(s, v)
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p = simdV11Imm8(s, v)
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case ssa.OpAMD64VRNDSCALEPSMasked128,
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ssa.OpAMD64VRNDSCALEPSMasked256,
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@ -647,7 +647,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPRORQMasked128,
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ssa.OpAMD64VPRORQMasked256,
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ssa.OpAMD64VPRORQMasked512:
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p = simdFpkfpImm8(s, v)
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p = simdVkvImm8(s, v)
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case ssa.OpAMD64VDPPD128,
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ssa.OpAMD64VCMPPS128,
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@ -680,7 +680,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPSHRDQ128,
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ssa.OpAMD64VPSHRDQ256,
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ssa.OpAMD64VPSHRDQ512:
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p = simdFp21Imm8(s, v)
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p = simdV21Imm8(s, v)
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case ssa.OpAMD64VCMPPS512,
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ssa.OpAMD64VCMPPD512,
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@ -708,7 +708,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPCMPD128,
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ssa.OpAMD64VPCMPD256,
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ssa.OpAMD64VPCMPQ256:
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p = simdFp2kImm8(s, v)
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p = simdV2kImm8(s, v)
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case ssa.OpAMD64VCMPPSMasked128,
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ssa.OpAMD64VCMPPSMasked256,
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@ -740,7 +740,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPCMPUQMasked128,
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ssa.OpAMD64VPCMPUQMasked256,
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ssa.OpAMD64VPCMPUQMasked512:
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p = simdFp2kkImm8(s, v)
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p = simdV2kkImm8(s, v)
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case ssa.OpAMD64VFMADD213PS128,
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ssa.OpAMD64VFMADD213PS256,
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@ -790,7 +790,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPDPBUSD128,
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ssa.OpAMD64VPDPBUSD256,
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ssa.OpAMD64VPDPBUSD512:
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p = simdFp31ResultInArg0(s, v)
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p = simdV31ResultInArg0(s, v)
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case ssa.OpAMD64VFMADD213PSMasked128,
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ssa.OpAMD64VFMADD213PSMasked256,
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@ -840,7 +840,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPDPBUSDMasked128,
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ssa.OpAMD64VPDPBUSDMasked256,
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ssa.OpAMD64VPDPBUSDMasked512:
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p = simdFp3kfpResultInArg0(s, v)
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p = simdV3kvResultInArg0(s, v)
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case ssa.OpAMD64VPSLLW128,
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ssa.OpAMD64VPSLLW256,
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@ -863,7 +863,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPSRAQ128,
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ssa.OpAMD64VPSRAQ256,
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ssa.OpAMD64VPSRAQ512:
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p = simdFpXfp(s, v)
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p = simdVfpv(s, v)
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case ssa.OpAMD64VPSLLQMasked128,
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ssa.OpAMD64VPSLLQMasked256,
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@ -874,19 +874,19 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPSRAQMasked128,
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ssa.OpAMD64VPSRAQMasked256,
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ssa.OpAMD64VPSRAQMasked512:
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p = simdFpXkfp(s, v)
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p = simdVfpkv(s, v)
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case ssa.OpAMD64VPINSRB128,
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ssa.OpAMD64VPINSRW128,
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ssa.OpAMD64VPINSRD128,
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ssa.OpAMD64VPINSRQ128:
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p = simdFpgpfpImm8(s, v)
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p = simdVgpvImm8(s, v)
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case ssa.OpAMD64VPEXTRB128,
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ssa.OpAMD64VPEXTRW128,
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ssa.OpAMD64VPEXTRD128,
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ssa.OpAMD64VPEXTRQ128:
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p = simdFpgpImm8(s, v)
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p = simdVgpImm8(s, v)
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case ssa.OpAMD64VGF2P8AFFINEINVQBMasked128,
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ssa.OpAMD64VGF2P8AFFINEINVQBMasked256,
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@ -912,7 +912,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPSHRDQMasked128,
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ssa.OpAMD64VPSHRDQMasked256,
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ssa.OpAMD64VPSHRDQMasked512:
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p = simdFp2kfpImm8(s, v)
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p = simdV2kvImm8(s, v)
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default:
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// Unknown reg shape
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@ -1518,7 +1518,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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}
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// Example instruction: VRSQRTPS X1, X1
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func simdFp11(s *ssagen.State, v *ssa.Value) *obj.Prog {
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func simdV11(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = simdReg(v.Args[0])
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@ -1528,7 +1528,7 @@ func simdFp11(s *ssagen.State, v *ssa.Value) *obj.Prog {
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}
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// Example instruction: VPSUBD X1, X2, X3
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func simdFp21(s *ssagen.State, v *ssa.Value) *obj.Prog {
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func simdV21(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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// Vector registers operands follows a right-to-left order.
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@ -1543,7 +1543,7 @@ func simdFp21(s *ssagen.State, v *ssa.Value) *obj.Prog {
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// This function is to accustomize the shifts.
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// The 2nd arg is an XMM, and this function merely checks that.
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// Example instruction: VPSLLQ Z1, X1, Z2
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func simdFpXfp(s *ssagen.State, v *ssa.Value) *obj.Prog {
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func simdVfpv(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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// Vector registers operands follows a right-to-left order.
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@ -1556,13 +1556,18 @@ func simdFpXfp(s *ssagen.State, v *ssa.Value) *obj.Prog {
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}
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// Example instruction: VPCMPEQW Z26, Z30, K4
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func simdFp2k(s *ssagen.State, v *ssa.Value) *obj.Prog {
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// simdReg handles mask and vector registers altogether
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return simdFp21(s, v)
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func simdV2k(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = simdReg(v.Args[1])
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p.AddRestSourceReg(simdReg(v.Args[0]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = maskReg(v)
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return p
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}
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// Example instruction: VPMINUQ X21, X3, K3, X31
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func simdFp2kfp(s *ssagen.State, v *ssa.Value) *obj.Prog {
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func simdV2kv(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = simdReg(v.Args[1])
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@ -1572,7 +1577,7 @@ func simdFp2kfp(s *ssagen.State, v *ssa.Value) *obj.Prog {
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// or "predicate" for "predicated AVX512 instructions"
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// sits right at the end of the operand list.
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// TODO: verify this assumption.
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p.AddRestSourceReg(simdReg(v.Args[2]))
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p.AddRestSourceReg(maskReg(v.Args[2]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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@ -1581,35 +1586,42 @@ func simdFp2kfp(s *ssagen.State, v *ssa.Value) *obj.Prog {
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// This function is to accustomize the shifts.
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// The 2nd arg is an XMM, and this function merely checks that.
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// Example instruction: VPSLLQ Z1, X1, K1, Z2
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func simdFpXkfp(s *ssagen.State, v *ssa.Value) *obj.Prog {
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func simdVfpkv(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[1].Reg()
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p.AddRestSourceReg(simdReg(v.Args[0]))
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p.AddRestSourceReg(simdReg(v.Args[2]))
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p.AddRestSourceReg(maskReg(v.Args[2]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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// Example instruction: VPCMPEQW Z26, Z30, K1, K4
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func simdFp2kk(s *ssagen.State, v *ssa.Value) *obj.Prog {
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return simdFp2kfp(s, v)
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func simdV2kk(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = simdReg(v.Args[1])
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p.AddRestSourceReg(simdReg(v.Args[0]))
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p.AddRestSourceReg(maskReg(v.Args[2]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = maskReg(v)
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return p
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}
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// Example instruction: VPOPCNTB X14, K4, X16
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func simdFpkfp(s *ssagen.State, v *ssa.Value) *obj.Prog {
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func simdVkv(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = simdReg(v.Args[0])
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p.AddRestSourceReg(simdReg(v.Args[1]))
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p.AddRestSourceReg(maskReg(v.Args[1]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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// Example instruction: VROUNDPD $7, X2, X2
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func simdFp11Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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func simdV11Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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imm := v.AuxInt
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if imm < 0 || imm > 255 {
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@ -1624,7 +1636,7 @@ func simdFp11Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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}
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// Example instruction: VREDUCEPD $126, X1, K3, X31
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func simdFpkfpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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func simdVkvImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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imm := v.AuxInt
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if imm < 0 || imm > 255 {
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@ -1633,14 +1645,14 @@ func simdFpkfpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p.From.Offset = imm
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p.From.Type = obj.TYPE_CONST
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p.AddRestSourceReg(simdReg(v.Args[0]))
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p.AddRestSourceReg(simdReg(v.Args[1]))
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p.AddRestSourceReg(maskReg(v.Args[1]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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return p
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}
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// Example instruction: VCMPPS $7, X2, X9, X2
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func simdFp21Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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func simdV21Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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imm := v.AuxInt
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if imm < 0 || imm > 255 {
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@ -1656,7 +1668,7 @@ func simdFp21Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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}
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// Example instruction: VPINSRB $3, DX, X0, X0
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func simdFpgpfpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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func simdVgpvImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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imm := v.AuxInt
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if imm < 0 || imm > 255 {
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@ -1672,12 +1684,7 @@ func simdFpgpfpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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}
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// Example instruction: VPCMPD $1, Z1, Z2, K1
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func simdFp2kImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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return simdFp21Imm8(s, v)
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}
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// Example instruction: VPCMPD $1, Z1, Z2, K2, K1
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func simdFp2kkImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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func simdV2kImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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imm := v.AuxInt
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if imm < 0 || imm > 255 {
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@ -1687,18 +1694,34 @@ func simdFp2kkImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p.From.Type = obj.TYPE_CONST
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p.AddRestSourceReg(simdReg(v.Args[1]))
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p.AddRestSourceReg(simdReg(v.Args[0]))
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p.AddRestSourceReg(simdReg(v.Args[2]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = simdReg(v)
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p.To.Reg = maskReg(v)
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return p
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}
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func simdFp2kfpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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return simdFp2kkImm8(s, v)
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// Example instruction: VPCMPD $1, Z1, Z2, K2, K1
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func simdV2kkImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
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imm := v.AuxInt
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if imm < 0 || imm > 255 {
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v.Fatalf("Invalid source selection immediate")
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}
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p.From.Offset = imm
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p.From.Type = obj.TYPE_CONST
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p.AddRestSourceReg(simdReg(v.Args[1]))
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p.AddRestSourceReg(simdReg(v.Args[0]))
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p.AddRestSourceReg(maskReg(v.Args[2]))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = maskReg(v)
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return p
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}
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func simdV2kvImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
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return simdV2kkImm8(s, v)
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}
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// Example instruction: VFMADD213PD Z2, Z1, Z0
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func simdFp31ResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog {
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func simdV31ResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog {
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p := s.Prog(v.Op.Asm())
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = simdReg(v.Args[2])
|
||||
|
|
@ -1709,18 +1732,18 @@ func simdFp31ResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog {
|
|||
}
|
||||
|
||||
// Example instruction: VFMADD213PD Z2, Z1, K1, Z0
|
||||
func simdFp3kfpResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog {
|
||||
func simdV3kvResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog {
|
||||
p := s.Prog(v.Op.Asm())
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = simdReg(v.Args[2])
|
||||
p.AddRestSourceReg(simdReg(v.Args[1]))
|
||||
p.AddRestSourceReg(simdReg(v.Args[3]))
|
||||
p.AddRestSourceReg(maskReg(v.Args[3]))
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = simdReg(v)
|
||||
return p
|
||||
}
|
||||
|
||||
func simdFpgpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
|
||||
func simdVgpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
|
||||
p := s.Prog(v.Op.Asm())
|
||||
imm := v.AuxInt
|
||||
if imm < 0 || imm > 255 {
|
||||
|
|
@ -1735,7 +1758,7 @@ func simdFpgpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
|
|||
}
|
||||
|
||||
// Currently unused
|
||||
func simdFp31(s *ssagen.State, v *ssa.Value) *obj.Prog {
|
||||
func simdV31(s *ssagen.State, v *ssa.Value) *obj.Prog {
|
||||
p := s.Prog(v.Op.Asm())
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = simdReg(v.Args[2])
|
||||
|
|
@ -1747,13 +1770,13 @@ func simdFp31(s *ssagen.State, v *ssa.Value) *obj.Prog {
|
|||
}
|
||||
|
||||
// Currently unused
|
||||
func simdFp3kfp(s *ssagen.State, v *ssa.Value) *obj.Prog {
|
||||
func simdV3kv(s *ssagen.State, v *ssa.Value) *obj.Prog {
|
||||
p := s.Prog(v.Op.Asm())
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = simdReg(v.Args[2])
|
||||
p.AddRestSourceReg(simdReg(v.Args[1]))
|
||||
p.AddRestSourceReg(simdReg(v.Args[0]))
|
||||
p.AddRestSourceReg(simdReg(v.Args[3]))
|
||||
p.AddRestSourceReg(maskReg(v.Args[3]))
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = simdReg(v)
|
||||
return p
|
||||
|
|
@ -1869,8 +1892,6 @@ func simdReg(v *ssa.Value) int16 {
|
|||
base.Fatalf("simdReg: not a simd type; v=%s, b=b%d, f=%s", v.LongString(), v.Block.ID, v.Block.Func.Name)
|
||||
}
|
||||
switch t.Size() {
|
||||
case 8:
|
||||
return v.Reg() // K registers
|
||||
case 16:
|
||||
return v.Reg()
|
||||
case 32:
|
||||
|
|
@ -1881,6 +1902,19 @@ func simdReg(v *ssa.Value) int16 {
|
|||
panic("unreachable")
|
||||
}
|
||||
|
||||
// XXX k mask
|
||||
func maskReg(v *ssa.Value) int16 {
|
||||
t := v.Type
|
||||
if !t.IsSIMD() {
|
||||
base.Fatalf("simdReg: not a simd type; v=%s, b=b%d, f=%s", v.LongString(), v.Block.ID, v.Block.Func.Name)
|
||||
}
|
||||
switch t.Size() {
|
||||
case 8:
|
||||
return v.Reg()
|
||||
}
|
||||
panic("unreachable")
|
||||
}
|
||||
|
||||
// XXX this is used for shift operations only.
|
||||
// regalloc will issue OpCopy with incorrect type, but the assigned
|
||||
// register should be correct, and this function is merely checking
|
||||
|
|
|
|||
|
|
@ -109,6 +109,7 @@ func init() {
|
|||
gp = buildReg("AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15")
|
||||
g = buildReg("g")
|
||||
fp = buildReg("X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14")
|
||||
v = buildReg("X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14")
|
||||
x15 = buildReg("X15")
|
||||
mask = buildReg("K1 K2 K3 K4 K5 K6 K7")
|
||||
gpsp = gp | buildReg("SP")
|
||||
|
|
@ -120,6 +121,7 @@ func init() {
|
|||
var (
|
||||
gponly = []regMask{gp}
|
||||
fponly = []regMask{fp}
|
||||
vonly = []regMask{v}
|
||||
maskonly = []regMask{mask}
|
||||
)
|
||||
|
||||
|
|
@ -182,15 +184,20 @@ func init() {
|
|||
fpstore = regInfo{inputs: []regMask{gpspsb, fp, 0}}
|
||||
fpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, fp, 0}}
|
||||
|
||||
fp1k1 = regInfo{inputs: fponly, outputs: maskonly}
|
||||
k1fp1 = regInfo{inputs: maskonly, outputs: fponly}
|
||||
fp2k1 = regInfo{inputs: []regMask{fp, fp}, outputs: maskonly}
|
||||
fp1k1fp1 = regInfo{inputs: []regMask{fp, mask}, outputs: fponly}
|
||||
fp2k1fp1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: fponly}
|
||||
fp2k1k1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: maskonly}
|
||||
fp3fp1 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: fponly}
|
||||
fp3k1fp1 = regInfo{inputs: []regMask{fp, fp, fp, mask}, outputs: fponly}
|
||||
fp1gp1fp1 = regInfo{inputs: []regMask{fp, gp}, outputs: fponly}
|
||||
v11 = regInfo{inputs: vonly, outputs: vonly}
|
||||
v21 = regInfo{inputs: []regMask{v, v}, outputs: vonly}
|
||||
vk = regInfo{inputs: vonly, outputs: maskonly}
|
||||
kv = regInfo{inputs: maskonly, outputs: vonly}
|
||||
v2k = regInfo{inputs: []regMask{v, v}, outputs: maskonly}
|
||||
vkv = regInfo{inputs: []regMask{v, mask}, outputs: vonly}
|
||||
v2kv = regInfo{inputs: []regMask{v, v, mask}, outputs: vonly}
|
||||
v2kk = regInfo{inputs: []regMask{v, v, mask}, outputs: maskonly}
|
||||
v31 = regInfo{inputs: []regMask{v, v, v}, outputs: vonly}
|
||||
v3kv = regInfo{inputs: []regMask{v, v, v, mask}, outputs: vonly}
|
||||
vgpv = regInfo{inputs: []regMask{v, gp}, outputs: vonly}
|
||||
vgp = regInfo{inputs: vonly, outputs: gponly}
|
||||
vfpv = regInfo{inputs: []regMask{v, fp}, outputs: vonly}
|
||||
vfpkv = regInfo{inputs: []regMask{v, fp, mask}, outputs: vonly}
|
||||
|
||||
prefreg = regInfo{inputs: []regMask{gpspsbg}}
|
||||
)
|
||||
|
|
@ -1234,37 +1241,37 @@ func init() {
|
|||
{name: "VMOVDQUload512", argLength: 2, reg: fpload, asm: "VMOVDQU64", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1 = mem
|
||||
{name: "VMOVDQUstore512", argLength: 3, reg: fpstore, asm: "VMOVDQU64", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg1, arg2 = mem
|
||||
|
||||
{name: "VPMOVMToVec8x16", argLength: 1, reg: k1fp1, asm: "VPMOVM2B"},
|
||||
{name: "VPMOVMToVec8x32", argLength: 1, reg: k1fp1, asm: "VPMOVM2B"},
|
||||
{name: "VPMOVMToVec8x64", argLength: 1, reg: k1fp1, asm: "VPMOVM2B"},
|
||||
{name: "VPMOVMToVec8x16", argLength: 1, reg: kv, asm: "VPMOVM2B"},
|
||||
{name: "VPMOVMToVec8x32", argLength: 1, reg: kv, asm: "VPMOVM2B"},
|
||||
{name: "VPMOVMToVec8x64", argLength: 1, reg: kv, asm: "VPMOVM2B"},
|
||||
|
||||
{name: "VPMOVMToVec16x8", argLength: 1, reg: k1fp1, asm: "VPMOVM2W"},
|
||||
{name: "VPMOVMToVec16x16", argLength: 1, reg: k1fp1, asm: "VPMOVM2W"},
|
||||
{name: "VPMOVMToVec16x32", argLength: 1, reg: k1fp1, asm: "VPMOVM2W"},
|
||||
{name: "VPMOVMToVec16x8", argLength: 1, reg: kv, asm: "VPMOVM2W"},
|
||||
{name: "VPMOVMToVec16x16", argLength: 1, reg: kv, asm: "VPMOVM2W"},
|
||||
{name: "VPMOVMToVec16x32", argLength: 1, reg: kv, asm: "VPMOVM2W"},
|
||||
|
||||
{name: "VPMOVMToVec32x4", argLength: 1, reg: k1fp1, asm: "VPMOVM2D"},
|
||||
{name: "VPMOVMToVec32x8", argLength: 1, reg: k1fp1, asm: "VPMOVM2D"},
|
||||
{name: "VPMOVMToVec32x16", argLength: 1, reg: k1fp1, asm: "VPMOVM2D"},
|
||||
{name: "VPMOVMToVec32x4", argLength: 1, reg: kv, asm: "VPMOVM2D"},
|
||||
{name: "VPMOVMToVec32x8", argLength: 1, reg: kv, asm: "VPMOVM2D"},
|
||||
{name: "VPMOVMToVec32x16", argLength: 1, reg: kv, asm: "VPMOVM2D"},
|
||||
|
||||
{name: "VPMOVMToVec64x2", argLength: 1, reg: k1fp1, asm: "VPMOVM2Q"},
|
||||
{name: "VPMOVMToVec64x4", argLength: 1, reg: k1fp1, asm: "VPMOVM2Q"},
|
||||
{name: "VPMOVMToVec64x8", argLength: 1, reg: k1fp1, asm: "VPMOVM2Q"},
|
||||
{name: "VPMOVMToVec64x2", argLength: 1, reg: kv, asm: "VPMOVM2Q"},
|
||||
{name: "VPMOVMToVec64x4", argLength: 1, reg: kv, asm: "VPMOVM2Q"},
|
||||
{name: "VPMOVMToVec64x8", argLength: 1, reg: kv, asm: "VPMOVM2Q"},
|
||||
|
||||
{name: "VPMOVVec8x16ToM", argLength: 1, reg: fp1k1, asm: "VPMOVB2M"},
|
||||
{name: "VPMOVVec8x32ToM", argLength: 1, reg: fp1k1, asm: "VPMOVB2M"},
|
||||
{name: "VPMOVVec8x64ToM", argLength: 1, reg: fp1k1, asm: "VPMOVB2M"},
|
||||
{name: "VPMOVVec8x16ToM", argLength: 1, reg: vk, asm: "VPMOVB2M"},
|
||||
{name: "VPMOVVec8x32ToM", argLength: 1, reg: vk, asm: "VPMOVB2M"},
|
||||
{name: "VPMOVVec8x64ToM", argLength: 1, reg: vk, asm: "VPMOVB2M"},
|
||||
|
||||
{name: "VPMOVVec16x8ToM", argLength: 1, reg: fp1k1, asm: "VPMOVW2M"},
|
||||
{name: "VPMOVVec16x16ToM", argLength: 1, reg: fp1k1, asm: "VPMOVW2M"},
|
||||
{name: "VPMOVVec16x32ToM", argLength: 1, reg: fp1k1, asm: "VPMOVW2M"},
|
||||
{name: "VPMOVVec16x8ToM", argLength: 1, reg: vk, asm: "VPMOVW2M"},
|
||||
{name: "VPMOVVec16x16ToM", argLength: 1, reg: vk, asm: "VPMOVW2M"},
|
||||
{name: "VPMOVVec16x32ToM", argLength: 1, reg: vk, asm: "VPMOVW2M"},
|
||||
|
||||
{name: "VPMOVVec32x4ToM", argLength: 1, reg: fp1k1, asm: "VPMOVD2M"},
|
||||
{name: "VPMOVVec32x8ToM", argLength: 1, reg: fp1k1, asm: "VPMOVD2M"},
|
||||
{name: "VPMOVVec32x16ToM", argLength: 1, reg: fp1k1, asm: "VPMOVD2M"},
|
||||
{name: "VPMOVVec32x4ToM", argLength: 1, reg: vk, asm: "VPMOVD2M"},
|
||||
{name: "VPMOVVec32x8ToM", argLength: 1, reg: vk, asm: "VPMOVD2M"},
|
||||
{name: "VPMOVVec32x16ToM", argLength: 1, reg: vk, asm: "VPMOVD2M"},
|
||||
|
||||
{name: "VPMOVVec64x2ToM", argLength: 1, reg: fp1k1, asm: "VPMOVQ2M"},
|
||||
{name: "VPMOVVec64x4ToM", argLength: 1, reg: fp1k1, asm: "VPMOVQ2M"},
|
||||
{name: "VPMOVVec64x8ToM", argLength: 1, reg: fp1k1, asm: "VPMOVQ2M"},
|
||||
{name: "VPMOVVec64x2ToM", argLength: 1, reg: vk, asm: "VPMOVQ2M"},
|
||||
{name: "VPMOVVec64x4ToM", argLength: 1, reg: vk, asm: "VPMOVQ2M"},
|
||||
{name: "VPMOVVec64x8ToM", argLength: 1, reg: vk, asm: "VPMOVQ2M"},
|
||||
|
||||
{name: "Zero128", argLength: 0, reg: fp01, asm: "VPXOR"},
|
||||
{name: "Zero256", argLength: 0, reg: fp01, asm: "VPXOR"},
|
||||
|
|
@ -1301,7 +1308,7 @@ func init() {
|
|||
pkg: "cmd/internal/obj/x86",
|
||||
genfile: "../../amd64/ssa.go",
|
||||
genSIMDfile: "../../amd64/simdssa.go",
|
||||
ops: append(AMD64ops, simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp3fp1, fp3k1fp1, fp1gp1fp1, fpgp)...), // AMD64ops,
|
||||
ops: append(AMD64ops, simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vfpkv)...), // AMD64ops,
|
||||
blocks: AMD64blocks,
|
||||
regnames: regNamesAMD64,
|
||||
ParamIntRegNames: "AX BX CX DI SI R8 R9 R10 R11",
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
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Add table
Add a link
Reference in a new issue