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[dev.simd] cmd/compile, simd: remove FP bitwise logic operations.

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This CL is generated by CL 686555.

Change-Id: I0efb86a919692cd97c1c5b6365d77361a30bf7cf
Reviewed-on: https://go-review.googlesource.com/c/go/+/686496
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Junyang Shao 2025-07-08 17:26:59 +00:00
parent 0870ed04a3
commit 56ca67682b
9 changed files with 0 additions and 2256 deletions
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72
src/cmd/compile/internal/amd64/simdssa.go
View file

@ -78,22 +78,10 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VADDSUBPS256,
ssa.OpAMD64VADDSUBPD128,
ssa.OpAMD64VADDSUBPD256,
ssa.OpAMD64VANDPS128,
ssa.OpAMD64VANDPS256,
ssa.OpAMD64VANDPS512,
ssa.OpAMD64VANDPD128,
ssa.OpAMD64VANDPD256,
ssa.OpAMD64VANDPD512,
ssa.OpAMD64VPAND128,
ssa.OpAMD64VPAND256,
ssa.OpAMD64VPANDD512,
ssa.OpAMD64VPANDQ512,
ssa.OpAMD64VANDNPS128,
ssa.OpAMD64VANDNPS256,
ssa.OpAMD64VANDNPS512,
ssa.OpAMD64VANDNPD128,
ssa.OpAMD64VANDNPD256,
ssa.OpAMD64VANDNPD512,
ssa.OpAMD64VPANDN128,
ssa.OpAMD64VPANDN256,
ssa.OpAMD64VPANDND512,
@ -221,12 +209,6 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMULLQ128,
ssa.OpAMD64VPMULLQ256,
ssa.OpAMD64VPMULLQ512,
ssa.OpAMD64VORPS128,
ssa.OpAMD64VORPS256,
ssa.OpAMD64VORPS512,
ssa.OpAMD64VORPD128,
ssa.OpAMD64VORPD256,
ssa.OpAMD64VORPD512,
ssa.OpAMD64VPOR128,
ssa.OpAMD64VPOR256,
ssa.OpAMD64VPORD512,
@ -332,12 +314,6 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPSUBQ128,
ssa.OpAMD64VPSUBQ256,
ssa.OpAMD64VPSUBQ512,
ssa.OpAMD64VXORPS128,
ssa.OpAMD64VXORPS256,
ssa.OpAMD64VXORPS512,
ssa.OpAMD64VXORPD128,
ssa.OpAMD64VXORPD256,
ssa.OpAMD64VXORPD512,
ssa.OpAMD64VPXOR128,
ssa.OpAMD64VPXOR256,
ssa.OpAMD64VPXORD512,
@ -362,24 +338,12 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPADDQMasked128,
ssa.OpAMD64VPADDQMasked256,
ssa.OpAMD64VPADDQMasked512,
ssa.OpAMD64VANDPSMasked128,
ssa.OpAMD64VANDPSMasked256,
ssa.OpAMD64VANDPSMasked512,
ssa.OpAMD64VANDPDMasked128,
ssa.OpAMD64VANDPDMasked256,
ssa.OpAMD64VANDPDMasked512,
ssa.OpAMD64VPANDDMasked128,
ssa.OpAMD64VPANDDMasked256,
ssa.OpAMD64VPANDDMasked512,
ssa.OpAMD64VPANDQMasked128,
ssa.OpAMD64VPANDQMasked256,
ssa.OpAMD64VPANDQMasked512,
ssa.OpAMD64VANDNPSMasked128,
ssa.OpAMD64VANDNPSMasked256,
ssa.OpAMD64VANDNPSMasked512,
ssa.OpAMD64VANDNPDMasked128,
ssa.OpAMD64VANDNPDMasked256,
ssa.OpAMD64VANDNPDMasked512,
ssa.OpAMD64VPANDNDMasked128,
ssa.OpAMD64VPANDNDMasked256,
ssa.OpAMD64VPANDNDMasked512,
@ -494,12 +458,6 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMULLQMasked128,
ssa.OpAMD64VPMULLQMasked256,
ssa.OpAMD64VPMULLQMasked512,
ssa.OpAMD64VORPSMasked128,
ssa.OpAMD64VORPSMasked256,
ssa.OpAMD64VORPSMasked512,
ssa.OpAMD64VORPDMasked128,
ssa.OpAMD64VORPDMasked256,
ssa.OpAMD64VORPDMasked512,
ssa.OpAMD64VPORDMasked128,
ssa.OpAMD64VPORDMasked256,
ssa.OpAMD64VPORDMasked512,
@ -581,12 +539,6 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPSUBQMasked128,
ssa.OpAMD64VPSUBQMasked256,
ssa.OpAMD64VPSUBQMasked512,
ssa.OpAMD64VXORPSMasked128,
ssa.OpAMD64VXORPSMasked256,
ssa.OpAMD64VXORPSMasked512,
ssa.OpAMD64VXORPDMasked128,
ssa.OpAMD64VXORPDMasked256,
ssa.OpAMD64VXORPDMasked512,
ssa.OpAMD64VPXORDMasked128,
ssa.OpAMD64VPXORDMasked256,
ssa.OpAMD64VPXORDMasked512,
@ -999,24 +951,12 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPADDQMasked128,
ssa.OpAMD64VPADDQMasked256,
ssa.OpAMD64VPADDQMasked512,
ssa.OpAMD64VANDPSMasked128,
ssa.OpAMD64VANDPSMasked256,
ssa.OpAMD64VANDPSMasked512,
ssa.OpAMD64VANDPDMasked128,
ssa.OpAMD64VANDPDMasked256,
ssa.OpAMD64VANDPDMasked512,
ssa.OpAMD64VPANDDMasked128,
ssa.OpAMD64VPANDDMasked256,
ssa.OpAMD64VPANDDMasked512,
ssa.OpAMD64VPANDQMasked128,
ssa.OpAMD64VPANDQMasked256,
ssa.OpAMD64VPANDQMasked512,
ssa.OpAMD64VANDNPSMasked128,
ssa.OpAMD64VANDNPSMasked256,
ssa.OpAMD64VANDNPSMasked512,
ssa.OpAMD64VANDNPDMasked128,
ssa.OpAMD64VANDNPDMasked256,
ssa.OpAMD64VANDNPDMasked512,
ssa.OpAMD64VPANDNDMasked128,
ssa.OpAMD64VPANDNDMasked256,
ssa.OpAMD64VPANDNDMasked512,
@ -1179,12 +1119,6 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMULLQMasked128,
ssa.OpAMD64VPMULLQMasked256,
ssa.OpAMD64VPMULLQMasked512,
ssa.OpAMD64VORPSMasked128,
ssa.OpAMD64VORPSMasked256,
ssa.OpAMD64VORPSMasked512,
ssa.OpAMD64VORPDMasked128,
ssa.OpAMD64VORPDMasked256,
ssa.OpAMD64VORPDMasked512,
ssa.OpAMD64VPORDMasked128,
ssa.OpAMD64VPORDMasked256,
ssa.OpAMD64VPORDMasked512,
@ -1353,12 +1287,6 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPDPBUSDMasked128,
ssa.OpAMD64VPDPBUSDMasked256,
ssa.OpAMD64VPDPBUSDMasked512,
ssa.OpAMD64VXORPSMasked128,
ssa.OpAMD64VXORPSMasked256,
ssa.OpAMD64VXORPSMasked512,
ssa.OpAMD64VXORPDMasked128,
ssa.OpAMD64VXORPDMasked256,
ssa.OpAMD64VXORPDMasked512,
ssa.OpAMD64VPXORDMasked128,
ssa.OpAMD64VPXORDMasked256,
ssa.OpAMD64VPXORDMasked512,

48
src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
View file

@ -46,12 +46,6 @@
(AddSubFloat32x8 ...) => (VADDSUBPS256 ...)
(AddSubFloat64x2 ...) => (VADDSUBPD128 ...)
(AddSubFloat64x4 ...) => (VADDSUBPD256 ...)
(AndFloat32x4 ...) => (VANDPS128 ...)
(AndFloat32x8 ...) => (VANDPS256 ...)
(AndFloat32x16 ...) => (VANDPS512 ...)
(AndFloat64x2 ...) => (VANDPD128 ...)
(AndFloat64x4 ...) => (VANDPD256 ...)
(AndFloat64x8 ...) => (VANDPD512 ...)
(AndInt8x16 ...) => (VPAND128 ...)
(AndInt8x32 ...) => (VPAND256 ...)
(AndInt16x8 ...) => (VPAND128 ...)
@ -72,12 +66,6 @@
(AndUint64x2 ...) => (VPAND128 ...)
(AndUint64x4 ...) => (VPAND256 ...)
(AndUint64x8 ...) => (VPANDQ512 ...)
(AndNotFloat32x4 ...) => (VANDNPS128 ...)
(AndNotFloat32x8 ...) => (VANDNPS256 ...)
(AndNotFloat32x16 ...) => (VANDNPS512 ...)
(AndNotFloat64x2 ...) => (VANDNPD128 ...)
(AndNotFloat64x4 ...) => (VANDNPD256 ...)
(AndNotFloat64x8 ...) => (VANDNPD512 ...)
(AndNotInt8x16 ...) => (VPANDN128 ...)
(AndNotInt8x32 ...) => (VPANDN256 ...)
(AndNotInt16x8 ...) => (VPANDN128 ...)
@ -410,12 +398,6 @@
(MaskedAddUint64x2 x y mask) => (VPADDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
(MaskedAddUint64x4 x y mask) => (VPADDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
(MaskedAddUint64x8 x y mask) => (VPADDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
(MaskedAndFloat32x4 x y mask) => (VANDPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
(MaskedAndFloat32x8 x y mask) => (VANDPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
(MaskedAndFloat32x16 x y mask) => (VANDPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
(MaskedAndFloat64x2 x y mask) => (VANDPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
(MaskedAndFloat64x4 x y mask) => (VANDPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
(MaskedAndFloat64x8 x y mask) => (VANDPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
(MaskedAndInt32x4 x y mask) => (VPANDDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
(MaskedAndInt32x8 x y mask) => (VPANDDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
(MaskedAndInt32x16 x y mask) => (VPANDDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
@ -428,12 +410,6 @@
(MaskedAndUint64x2 x y mask) => (VPANDQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
(MaskedAndUint64x4 x y mask) => (VPANDQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
(MaskedAndUint64x8 x y mask) => (VPANDQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
(MaskedAndNotFloat32x4 x y mask) => (VANDNPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
(MaskedAndNotFloat32x8 x y mask) => (VANDNPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
(MaskedAndNotFloat32x16 x y mask) => (VANDNPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
(MaskedAndNotFloat64x2 x y mask) => (VANDNPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
(MaskedAndNotFloat64x4 x y mask) => (VANDNPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
(MaskedAndNotFloat64x8 x y mask) => (VANDNPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
(MaskedAndNotInt32x4 x y mask) => (VPANDNDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
(MaskedAndNotInt32x8 x y mask) => (VPANDNDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
(MaskedAndNotInt32x16 x y mask) => (VPANDNDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
@ -812,12 +788,6 @@
(MaskedNotEqualUint64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPUQMasked128 [4] x y (VPMOVVec64x2ToM <types.TypeMask> mask)))
(MaskedNotEqualUint64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPUQMasked256 [4] x y (VPMOVVec64x4ToM <types.TypeMask> mask)))
(MaskedNotEqualUint64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPUQMasked512 [4] x y (VPMOVVec64x8ToM <types.TypeMask> mask)))
(MaskedOrFloat32x4 x y mask) => (VORPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
(MaskedOrFloat32x8 x y mask) => (VORPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
(MaskedOrFloat32x16 x y mask) => (VORPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
(MaskedOrFloat64x2 x y mask) => (VORPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
(MaskedOrFloat64x4 x y mask) => (VORPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
(MaskedOrFloat64x8 x y mask) => (VORPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
(MaskedOrInt32x4 x y mask) => (VPORDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
(MaskedOrInt32x8 x y mask) => (VPORDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
(MaskedOrInt32x16 x y mask) => (VPORDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
@ -1139,12 +1109,6 @@
(MaskedUnsignedSignedQuadDotProdAccumulateUint32x4 x y z mask) => (VPDPBUSDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
(MaskedUnsignedSignedQuadDotProdAccumulateUint32x8 x y z mask) => (VPDPBUSDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
(MaskedUnsignedSignedQuadDotProdAccumulateUint32x16 x y z mask) => (VPDPBUSDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
(MaskedXorFloat32x4 x y mask) => (VXORPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
(MaskedXorFloat32x8 x y mask) => (VXORPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
(MaskedXorFloat32x16 x y mask) => (VXORPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
(MaskedXorFloat64x2 x y mask) => (VXORPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
(MaskedXorFloat64x4 x y mask) => (VXORPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
(MaskedXorFloat64x8 x y mask) => (VXORPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
(MaskedXorInt32x4 x y mask) => (VPXORDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
(MaskedXorInt32x8 x y mask) => (VPXORDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
(MaskedXorInt32x16 x y mask) => (VPXORDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
@ -1284,12 +1248,6 @@
(NotEqualUint64x2 x y) => (VPMOVMToVec64x2 (VPCMPUQ128 [4] x y))
(NotEqualUint64x4 x y) => (VPMOVMToVec64x4 (VPCMPUQ256 [4] x y))
(NotEqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [4] x y))
(OrFloat32x4 ...) => (VORPS128 ...)
(OrFloat32x8 ...) => (VORPS256 ...)
(OrFloat32x16 ...) => (VORPS512 ...)
(OrFloat64x2 ...) => (VORPD128 ...)
(OrFloat64x4 ...) => (VORPD256 ...)
(OrFloat64x8 ...) => (VORPD512 ...)
(OrInt8x16 ...) => (VPOR128 ...)
(OrInt8x32 ...) => (VPOR256 ...)
(OrInt16x8 ...) => (VPOR128 ...)
@ -1699,12 +1657,6 @@
(UnsignedSignedQuadDotProdAccumulateUint32x4 ...) => (VPDPBUSD128 ...)
(UnsignedSignedQuadDotProdAccumulateUint32x8 ...) => (VPDPBUSD256 ...)
(UnsignedSignedQuadDotProdAccumulateUint32x16 ...) => (VPDPBUSD512 ...)
(XorFloat32x4 ...) => (VXORPS128 ...)
(XorFloat32x8 ...) => (VXORPS256 ...)
(XorFloat32x16 ...) => (VXORPS512 ...)
(XorFloat64x2 ...) => (VXORPD128 ...)
(XorFloat64x4 ...) => (VXORPD256 ...)
(XorFloat64x8 ...) => (VXORPD512 ...)
(XorInt8x16 ...) => (VPXOR128 ...)
(XorInt8x32 ...) => (VPXOR256 ...)
(XorInt16x8 ...) => (VPXOR128 ...)

48
src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
View file

@ -4,8 +4,6 @@ package main
func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp, fpgp regInfo) []opData {
return []opData{
{name: "VADDPS512", argLength: 2, reg: fp21, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDPS512", argLength: 2, reg: fp21, asm: "VANDPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDNPS512", argLength: 2, reg: fp21, asm: "VANDNPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRCP14PS512", argLength: 1, reg: fp11, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRSQRT14PS512", argLength: 1, reg: fp11, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VDIVPS512", argLength: 2, reg: fp21, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false},
@ -13,8 +11,6 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
{name: "VFMADDSUB213PS512", argLength: 3, reg: fp31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMSUBADD213PS512", argLength: 3, reg: fp31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VADDPSMasked512", argLength: 3, reg: fp2kfp, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDPSMasked512", argLength: 3, reg: fp2kfp, asm: "VANDPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDNPSMasked512", argLength: 3, reg: fp2kfp, asm: "VANDNPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRCP14PSMasked512", argLength: 2, reg: fpkfp, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRSQRT14PSMasked512", argLength: 2, reg: fpkfp, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VDIVPSMasked512", argLength: 3, reg: fp2kfp, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false},
@ -25,22 +21,16 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
{name: "VMINPSMasked512", argLength: 3, reg: fp2kfp, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMULPSMasked512", argLength: 3, reg: fp2kfp, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSCALEFPSMasked512", argLength: 3, reg: fp2kfp, asm: "VSCALEFPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VORPSMasked512", argLength: 3, reg: fp2kfp, asm: "VORPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSQRTPSMasked512", argLength: 2, reg: fpkfp, asm: "VSQRTPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VSUBPSMasked512", argLength: 3, reg: fp2kfp, asm: "VSUBPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VXORPSMasked512", argLength: 3, reg: fp2kfp, asm: "VXORPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMAXPS512", argLength: 2, reg: fp21, asm: "VMAXPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMINPS512", argLength: 2, reg: fp21, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMULPS512", argLength: 2, reg: fp21, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSCALEFPS512", argLength: 2, reg: fp21, asm: "VSCALEFPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VORPS512", argLength: 2, reg: fp21, asm: "VORPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSQRTPS512", argLength: 1, reg: fp11, asm: "VSQRTPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VSUBPS512", argLength: 2, reg: fp21, asm: "VSUBPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VXORPS512", argLength: 2, reg: fp21, asm: "VXORPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VADDPS128", argLength: 2, reg: fp21, asm: "VADDPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VADDSUBPS128", argLength: 2, reg: fp21, asm: "VADDSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VANDPS128", argLength: 2, reg: fp21, asm: "VANDPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDNPS128", argLength: 2, reg: fp21, asm: "VANDNPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRCP14PS128", argLength: 1, reg: fp11, asm: "VRCP14PS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRSQRTPS128", argLength: 1, reg: fp11, asm: "VRSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VDIVPS128", argLength: 2, reg: fp21, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false},
@ -48,8 +38,6 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
{name: "VFMADDSUB213PS128", argLength: 3, reg: fp31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMSUBADD213PS128", argLength: 3, reg: fp31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VADDPSMasked128", argLength: 3, reg: fp2kfp, asm: "VADDPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDPSMasked128", argLength: 3, reg: fp2kfp, asm: "VANDPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDNPSMasked128", argLength: 3, reg: fp2kfp, asm: "VANDNPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRCP14PSMasked128", argLength: 2, reg: fpkfp, asm: "VRCP14PS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRSQRT14PSMasked128", argLength: 2, reg: fpkfp, asm: "VRSQRT14PS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VDIVPSMasked128", argLength: 3, reg: fp2kfp, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false},
@ -60,24 +48,18 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
{name: "VMINPSMasked128", argLength: 3, reg: fp2kfp, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMULPSMasked128", argLength: 3, reg: fp2kfp, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSCALEFPSMasked128", argLength: 3, reg: fp2kfp, asm: "VSCALEFPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VORPSMasked128", argLength: 3, reg: fp2kfp, asm: "VORPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSQRTPSMasked128", argLength: 2, reg: fpkfp, asm: "VSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VSUBPSMasked128", argLength: 3, reg: fp2kfp, asm: "VSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VXORPSMasked128", argLength: 3, reg: fp2kfp, asm: "VXORPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMAXPS128", argLength: 2, reg: fp21, asm: "VMAXPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMINPS128", argLength: 2, reg: fp21, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMULPS128", argLength: 2, reg: fp21, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSCALEFPS128", argLength: 2, reg: fp21, asm: "VSCALEFPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VORPS128", argLength: 2, reg: fp21, asm: "VORPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VHADDPS128", argLength: 2, reg: fp21, asm: "VHADDPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VHSUBPS128", argLength: 2, reg: fp21, asm: "VHSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VSQRTPS128", argLength: 1, reg: fp11, asm: "VSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VSUBPS128", argLength: 2, reg: fp21, asm: "VSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VXORPS128", argLength: 2, reg: fp21, asm: "VXORPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VADDPS256", argLength: 2, reg: fp21, asm: "VADDPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VADDSUBPS256", argLength: 2, reg: fp21, asm: "VADDSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VANDPS256", argLength: 2, reg: fp21, asm: "VANDPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDNPS256", argLength: 2, reg: fp21, asm: "VANDNPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRCP14PS256", argLength: 1, reg: fp11, asm: "VRCP14PS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRSQRTPS256", argLength: 1, reg: fp11, asm: "VRSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VDIVPS256", argLength: 2, reg: fp21, asm: "VDIVPS", commutative: false, typ: "Vec256", resultInArg0: false},
@ -85,8 +67,6 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
{name: "VFMADDSUB213PS256", argLength: 3, reg: fp31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMSUBADD213PS256", argLength: 3, reg: fp31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VADDPSMasked256", argLength: 3, reg: fp2kfp, asm: "VADDPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDPSMasked256", argLength: 3, reg: fp2kfp, asm: "VANDPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDNPSMasked256", argLength: 3, reg: fp2kfp, asm: "VANDNPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRCP14PSMasked256", argLength: 2, reg: fpkfp, asm: "VRCP14PS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRSQRT14PSMasked256", argLength: 2, reg: fpkfp, asm: "VRSQRT14PS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VDIVPSMasked256", argLength: 3, reg: fp2kfp, asm: "VDIVPS", commutative: false, typ: "Vec256", resultInArg0: false},
@ -97,24 +77,18 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
{name: "VMINPSMasked256", argLength: 3, reg: fp2kfp, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMULPSMasked256", argLength: 3, reg: fp2kfp, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSCALEFPSMasked256", argLength: 3, reg: fp2kfp, asm: "VSCALEFPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VORPSMasked256", argLength: 3, reg: fp2kfp, asm: "VORPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSQRTPSMasked256", argLength: 2, reg: fpkfp, asm: "VSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VSUBPSMasked256", argLength: 3, reg: fp2kfp, asm: "VSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VXORPSMasked256", argLength: 3, reg: fp2kfp, asm: "VXORPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMAXPS256", argLength: 2, reg: fp21, asm: "VMAXPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMINPS256", argLength: 2, reg: fp21, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMULPS256", argLength: 2, reg: fp21, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSCALEFPS256", argLength: 2, reg: fp21, asm: "VSCALEFPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VORPS256", argLength: 2, reg: fp21, asm: "VORPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VHADDPS256", argLength: 2, reg: fp21, asm: "VHADDPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VHSUBPS256", argLength: 2, reg: fp21, asm: "VHSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VSQRTPS256", argLength: 1, reg: fp11, asm: "VSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VSUBPS256", argLength: 2, reg: fp21, asm: "VSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VXORPS256", argLength: 2, reg: fp21, asm: "VXORPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VADDPD128", argLength: 2, reg: fp21, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VADDSUBPD128", argLength: 2, reg: fp21, asm: "VADDSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VANDPD128", argLength: 2, reg: fp21, asm: "VANDPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDNPD128", argLength: 2, reg: fp21, asm: "VANDNPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRCP14PD128", argLength: 1, reg: fp11, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRSQRT14PD128", argLength: 1, reg: fp11, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VDIVPD128", argLength: 2, reg: fp21, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
@ -122,8 +96,6 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
{name: "VFMADDSUB213PD128", argLength: 3, reg: fp31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMSUBADD213PD128", argLength: 3, reg: fp31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VADDPDMasked128", argLength: 3, reg: fp2kfp, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDPDMasked128", argLength: 3, reg: fp2kfp, asm: "VANDPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDNPDMasked128", argLength: 3, reg: fp2kfp, asm: "VANDNPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRCP14PDMasked128", argLength: 2, reg: fpkfp, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRSQRT14PDMasked128", argLength: 2, reg: fpkfp, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VDIVPDMasked128", argLength: 3, reg: fp2kfp, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
@ -134,24 +106,18 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
{name: "VMINPDMasked128", argLength: 3, reg: fp2kfp, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMULPDMasked128", argLength: 3, reg: fp2kfp, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSCALEFPDMasked128", argLength: 3, reg: fp2kfp, asm: "VSCALEFPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VORPDMasked128", argLength: 3, reg: fp2kfp, asm: "VORPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSQRTPDMasked128", argLength: 2, reg: fpkfp, asm: "VSQRTPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VSUBPDMasked128", argLength: 3, reg: fp2kfp, asm: "VSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VXORPDMasked128", argLength: 3, reg: fp2kfp, asm: "VXORPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMAXPD128", argLength: 2, reg: fp21, asm: "VMAXPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMINPD128", argLength: 2, reg: fp21, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMULPD128", argLength: 2, reg: fp21, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSCALEFPD128", argLength: 2, reg: fp21, asm: "VSCALEFPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VORPD128", argLength: 2, reg: fp21, asm: "VORPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VHADDPD128", argLength: 2, reg: fp21, asm: "VHADDPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VHSUBPD128", argLength: 2, reg: fp21, asm: "VHSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VSQRTPD128", argLength: 1, reg: fp11, asm: "VSQRTPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VSUBPD128", argLength: 2, reg: fp21, asm: "VSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VXORPD128", argLength: 2, reg: fp21, asm: "VXORPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VADDPD256", argLength: 2, reg: fp21, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VADDSUBPD256", argLength: 2, reg: fp21, asm: "VADDSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VANDPD256", argLength: 2, reg: fp21, asm: "VANDPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDNPD256", argLength: 2, reg: fp21, asm: "VANDNPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRCP14PD256", argLength: 1, reg: fp11, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRSQRT14PD256", argLength: 1, reg: fp11, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VDIVPD256", argLength: 2, reg: fp21, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
@ -159,8 +125,6 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
{name: "VFMADDSUB213PD256", argLength: 3, reg: fp31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMSUBADD213PD256", argLength: 3, reg: fp31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VADDPDMasked256", argLength: 3, reg: fp2kfp, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDPDMasked256", argLength: 3, reg: fp2kfp, asm: "VANDPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDNPDMasked256", argLength: 3, reg: fp2kfp, asm: "VANDNPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRCP14PDMasked256", argLength: 2, reg: fpkfp, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRSQRT14PDMasked256", argLength: 2, reg: fpkfp, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VDIVPDMasked256", argLength: 3, reg: fp2kfp, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
@ -171,23 +135,17 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
{name: "VMINPDMasked256", argLength: 3, reg: fp2kfp, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMULPDMasked256", argLength: 3, reg: fp2kfp, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSCALEFPDMasked256", argLength: 3, reg: fp2kfp, asm: "VSCALEFPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VORPDMasked256", argLength: 3, reg: fp2kfp, asm: "VORPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSQRTPDMasked256", argLength: 2, reg: fpkfp, asm: "VSQRTPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VSUBPDMasked256", argLength: 3, reg: fp2kfp, asm: "VSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VXORPDMasked256", argLength: 3, reg: fp2kfp, asm: "VXORPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMAXPD256", argLength: 2, reg: fp21, asm: "VMAXPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMINPD256", argLength: 2, reg: fp21, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMULPD256", argLength: 2, reg: fp21, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSCALEFPD256", argLength: 2, reg: fp21, asm: "VSCALEFPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VORPD256", argLength: 2, reg: fp21, asm: "VORPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VHADDPD256", argLength: 2, reg: fp21, asm: "VHADDPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VHSUBPD256", argLength: 2, reg: fp21, asm: "VHSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VSQRTPD256", argLength: 1, reg: fp11, asm: "VSQRTPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VSUBPD256", argLength: 2, reg: fp21, asm: "VSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VXORPD256", argLength: 2, reg: fp21, asm: "VXORPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VADDPD512", argLength: 2, reg: fp21, asm: "VADDPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDPD512", argLength: 2, reg: fp21, asm: "VANDPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDNPD512", argLength: 2, reg: fp21, asm: "VANDNPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRCP14PD512", argLength: 1, reg: fp11, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRSQRT14PD512", argLength: 1, reg: fp11, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VDIVPD512", argLength: 2, reg: fp21, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
@ -195,8 +153,6 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
{name: "VFMADDSUB213PD512", argLength: 3, reg: fp31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMSUBADD213PD512", argLength: 3, reg: fp31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VADDPDMasked512", argLength: 3, reg: fp2kfp, asm: "VADDPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDPDMasked512", argLength: 3, reg: fp2kfp, asm: "VANDPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDNPDMasked512", argLength: 3, reg: fp2kfp, asm: "VANDNPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRCP14PDMasked512", argLength: 2, reg: fpkfp, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRSQRT14PDMasked512", argLength: 2, reg: fpkfp, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VDIVPDMasked512", argLength: 3, reg: fp2kfp, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
@ -207,18 +163,14 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
{name: "VMINPDMasked512", argLength: 3, reg: fp2kfp, asm: "VMINPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMULPDMasked512", argLength: 3, reg: fp2kfp, asm: "VMULPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSCALEFPDMasked512", argLength: 3, reg: fp2kfp, asm: "VSCALEFPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VORPDMasked512", argLength: 3, reg: fp2kfp, asm: "VORPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSQRTPDMasked512", argLength: 2, reg: fpkfp, asm: "VSQRTPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VSUBPDMasked512", argLength: 3, reg: fp2kfp, asm: "VSUBPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VXORPDMasked512", argLength: 3, reg: fp2kfp, asm: "VXORPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMAXPD512", argLength: 2, reg: fp21, asm: "VMAXPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMINPD512", argLength: 2, reg: fp21, asm: "VMINPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMULPD512", argLength: 2, reg: fp21, asm: "VMULPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSCALEFPD512", argLength: 2, reg: fp21, asm: "VSCALEFPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VORPD512", argLength: 2, reg: fp21, asm: "VORPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSQRTPD512", argLength: 1, reg: fp11, asm: "VSQRTPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VSUBPD512", argLength: 2, reg: fp21, asm: "VSUBPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VXORPD512", argLength: 2, reg: fp21, asm: "VXORPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPABSW256", argLength: 1, reg: fp11, asm: "VPABSW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPADDW256", argLength: 2, reg: fp21, asm: "VPADDW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPCMPEQW256", argLength: 2, reg: fp21, asm: "VPCMPEQW", commutative: true, typ: "Vec256", resultInArg0: false},

48
src/cmd/compile/internal/ssa/_gen/simdgenericOps.go
View file

@ -4,8 +4,6 @@ package main
func simdGenericOps() []opData {
return []opData{
{name: "AddFloat32x16", argLength: 2, commutative: true},
{name: "AndFloat32x16", argLength: 2, commutative: true},
{name: "AndNotFloat32x16", argLength: 2, commutative: false},
{name: "ApproximateReciprocalFloat32x16", argLength: 1, commutative: false},
{name: "ApproximateReciprocalOfSqrtFloat32x16", argLength: 1, commutative: false},
{name: "DivFloat32x16", argLength: 2, commutative: false},
@ -19,8 +17,6 @@ func simdGenericOps() []opData {
{name: "LessFloat32x16", argLength: 2, commutative: false},
{name: "LessEqualFloat32x16", argLength: 2, commutative: false},
{name: "MaskedAddFloat32x16", argLength: 3, commutative: true},
{name: "MaskedAndFloat32x16", argLength: 3, commutative: true},
{name: "MaskedAndNotFloat32x16", argLength: 3, commutative: false},
{name: "MaskedApproximateReciprocalFloat32x16", argLength: 2, commutative: false},
{name: "MaskedApproximateReciprocalOfSqrtFloat32x16", argLength: 2, commutative: false},
{name: "MaskedDivFloat32x16", argLength: 3, commutative: false},
@ -38,23 +34,17 @@ func simdGenericOps() []opData {
{name: "MaskedMulFloat32x16", argLength: 3, commutative: true},
{name: "MaskedMulByPowOf2Float32x16", argLength: 3, commutative: false},
{name: "MaskedNotEqualFloat32x16", argLength: 3, commutative: true},
{name: "MaskedOrFloat32x16", argLength: 3, commutative: true},
{name: "MaskedSqrtFloat32x16", argLength: 2, commutative: false},
{name: "MaskedSubFloat32x16", argLength: 3, commutative: false},
{name: "MaskedXorFloat32x16", argLength: 3, commutative: true},
{name: "MaxFloat32x16", argLength: 2, commutative: true},
{name: "MinFloat32x16", argLength: 2, commutative: true},
{name: "MulFloat32x16", argLength: 2, commutative: true},
{name: "MulByPowOf2Float32x16", argLength: 2, commutative: false},
{name: "NotEqualFloat32x16", argLength: 2, commutative: true},
{name: "OrFloat32x16", argLength: 2, commutative: true},
{name: "SqrtFloat32x16", argLength: 1, commutative: false},
{name: "SubFloat32x16", argLength: 2, commutative: false},
{name: "XorFloat32x16", argLength: 2, commutative: true},
{name: "AddFloat32x4", argLength: 2, commutative: true},
{name: "AddSubFloat32x4", argLength: 2, commutative: false},
{name: "AndFloat32x4", argLength: 2, commutative: true},
{name: "AndNotFloat32x4", argLength: 2, commutative: false},
{name: "ApproximateReciprocalFloat32x4", argLength: 1, commutative: false},
{name: "ApproximateReciprocalOfSqrtFloat32x4", argLength: 1, commutative: false},
{name: "CeilFloat32x4", argLength: 1, commutative: false},
@ -70,8 +60,6 @@ func simdGenericOps() []opData {
{name: "LessFloat32x4", argLength: 2, commutative: false},
{name: "LessEqualFloat32x4", argLength: 2, commutative: false},
{name: "MaskedAddFloat32x4", argLength: 3, commutative: true},
{name: "MaskedAndFloat32x4", argLength: 3, commutative: true},
{name: "MaskedAndNotFloat32x4", argLength: 3, commutative: false},
{name: "MaskedApproximateReciprocalFloat32x4", argLength: 2, commutative: false},
{name: "MaskedApproximateReciprocalOfSqrtFloat32x4", argLength: 2, commutative: false},
{name: "MaskedDivFloat32x4", argLength: 3, commutative: false},
@ -89,27 +77,21 @@ func simdGenericOps() []opData {
{name: "MaskedMulFloat32x4", argLength: 3, commutative: true},
{name: "MaskedMulByPowOf2Float32x4", argLength: 3, commutative: false},
{name: "MaskedNotEqualFloat32x4", argLength: 3, commutative: true},
{name: "MaskedOrFloat32x4", argLength: 3, commutative: true},
{name: "MaskedSqrtFloat32x4", argLength: 2, commutative: false},
{name: "MaskedSubFloat32x4", argLength: 3, commutative: false},
{name: "MaskedXorFloat32x4", argLength: 3, commutative: true},
{name: "MaxFloat32x4", argLength: 2, commutative: true},
{name: "MinFloat32x4", argLength: 2, commutative: true},
{name: "MulFloat32x4", argLength: 2, commutative: true},
{name: "MulByPowOf2Float32x4", argLength: 2, commutative: false},
{name: "NotEqualFloat32x4", argLength: 2, commutative: true},
{name: "OrFloat32x4", argLength: 2, commutative: true},
{name: "PairwiseAddFloat32x4", argLength: 2, commutative: false},
{name: "PairwiseSubFloat32x4", argLength: 2, commutative: false},
{name: "RoundFloat32x4", argLength: 1, commutative: false},
{name: "SqrtFloat32x4", argLength: 1, commutative: false},
{name: "SubFloat32x4", argLength: 2, commutative: false},
{name: "TruncFloat32x4", argLength: 1, commutative: false},
{name: "XorFloat32x4", argLength: 2, commutative: true},
{name: "AddFloat32x8", argLength: 2, commutative: true},
{name: "AddSubFloat32x8", argLength: 2, commutative: false},
{name: "AndFloat32x8", argLength: 2, commutative: true},
{name: "AndNotFloat32x8", argLength: 2, commutative: false},
{name: "ApproximateReciprocalFloat32x8", argLength: 1, commutative: false},
{name: "ApproximateReciprocalOfSqrtFloat32x8", argLength: 1, commutative: false},
{name: "CeilFloat32x8", argLength: 1, commutative: false},
@ -125,8 +107,6 @@ func simdGenericOps() []opData {
{name: "LessFloat32x8", argLength: 2, commutative: false},
{name: "LessEqualFloat32x8", argLength: 2, commutative: false},
{name: "MaskedAddFloat32x8", argLength: 3, commutative: true},
{name: "MaskedAndFloat32x8", argLength: 3, commutative: true},
{name: "MaskedAndNotFloat32x8", argLength: 3, commutative: false},
{name: "MaskedApproximateReciprocalFloat32x8", argLength: 2, commutative: false},
{name: "MaskedApproximateReciprocalOfSqrtFloat32x8", argLength: 2, commutative: false},
{name: "MaskedDivFloat32x8", argLength: 3, commutative: false},
@ -144,27 +124,21 @@ func simdGenericOps() []opData {
{name: "MaskedMulFloat32x8", argLength: 3, commutative: true},
{name: "MaskedMulByPowOf2Float32x8", argLength: 3, commutative: false},
{name: "MaskedNotEqualFloat32x8", argLength: 3, commutative: true},
{name: "MaskedOrFloat32x8", argLength: 3, commutative: true},
{name: "MaskedSqrtFloat32x8", argLength: 2, commutative: false},
{name: "MaskedSubFloat32x8", argLength: 3, commutative: false},
{name: "MaskedXorFloat32x8", argLength: 3, commutative: true},
{name: "MaxFloat32x8", argLength: 2, commutative: true},
{name: "MinFloat32x8", argLength: 2, commutative: true},
{name: "MulFloat32x8", argLength: 2, commutative: true},
{name: "MulByPowOf2Float32x8", argLength: 2, commutative: false},
{name: "NotEqualFloat32x8", argLength: 2, commutative: true},
{name: "OrFloat32x8", argLength: 2, commutative: true},
{name: "PairwiseAddFloat32x8", argLength: 2, commutative: false},
{name: "PairwiseSubFloat32x8", argLength: 2, commutative: false},
{name: "RoundFloat32x8", argLength: 1, commutative: false},
{name: "SqrtFloat32x8", argLength: 1, commutative: false},
{name: "SubFloat32x8", argLength: 2, commutative: false},
{name: "TruncFloat32x8", argLength: 1, commutative: false},
{name: "XorFloat32x8", argLength: 2, commutative: true},
{name: "AddFloat64x2", argLength: 2, commutative: true},
{name: "AddSubFloat64x2", argLength: 2, commutative: false},
{name: "AndFloat64x2", argLength: 2, commutative: true},
{name: "AndNotFloat64x2", argLength: 2, commutative: false},
{name: "ApproximateReciprocalFloat64x2", argLength: 1, commutative: false},
{name: "ApproximateReciprocalOfSqrtFloat64x2", argLength: 1, commutative: false},
{name: "CeilFloat64x2", argLength: 1, commutative: false},
@ -181,8 +155,6 @@ func simdGenericOps() []opData {
{name: "LessFloat64x2", argLength: 2, commutative: false},
{name: "LessEqualFloat64x2", argLength: 2, commutative: false},
{name: "MaskedAddFloat64x2", argLength: 3, commutative: true},
{name: "MaskedAndFloat64x2", argLength: 3, commutative: true},
{name: "MaskedAndNotFloat64x2", argLength: 3, commutative: false},
{name: "MaskedApproximateReciprocalFloat64x2", argLength: 2, commutative: false},
{name: "MaskedApproximateReciprocalOfSqrtFloat64x2", argLength: 2, commutative: false},
{name: "MaskedDivFloat64x2", argLength: 3, commutative: false},
@ -200,27 +172,21 @@ func simdGenericOps() []opData {
{name: "MaskedMulFloat64x2", argLength: 3, commutative: true},
{name: "MaskedMulByPowOf2Float64x2", argLength: 3, commutative: false},
{name: "MaskedNotEqualFloat64x2", argLength: 3, commutative: true},
{name: "MaskedOrFloat64x2", argLength: 3, commutative: true},
{name: "MaskedSqrtFloat64x2", argLength: 2, commutative: false},
{name: "MaskedSubFloat64x2", argLength: 3, commutative: false},
{name: "MaskedXorFloat64x2", argLength: 3, commutative: true},
{name: "MaxFloat64x2", argLength: 2, commutative: true},
{name: "MinFloat64x2", argLength: 2, commutative: true},
{name: "MulFloat64x2", argLength: 2, commutative: true},
{name: "MulByPowOf2Float64x2", argLength: 2, commutative: false},
{name: "NotEqualFloat64x2", argLength: 2, commutative: true},
{name: "OrFloat64x2", argLength: 2, commutative: true},
{name: "PairwiseAddFloat64x2", argLength: 2, commutative: false},
{name: "PairwiseSubFloat64x2", argLength: 2, commutative: false},
{name: "RoundFloat64x2", argLength: 1, commutative: false},
{name: "SqrtFloat64x2", argLength: 1, commutative: false},
{name: "SubFloat64x2", argLength: 2, commutative: false},
{name: "TruncFloat64x2", argLength: 1, commutative: false},
{name: "XorFloat64x2", argLength: 2, commutative: true},
{name: "AddFloat64x4", argLength: 2, commutative: true},
{name: "AddSubFloat64x4", argLength: 2, commutative: false},
{name: "AndFloat64x4", argLength: 2, commutative: true},
{name: "AndNotFloat64x4", argLength: 2, commutative: false},
{name: "ApproximateReciprocalFloat64x4", argLength: 1, commutative: false},
{name: "ApproximateReciprocalOfSqrtFloat64x4", argLength: 1, commutative: false},
{name: "CeilFloat64x4", argLength: 1, commutative: false},
@ -236,8 +202,6 @@ func simdGenericOps() []opData {
{name: "LessFloat64x4", argLength: 2, commutative: false},
{name: "LessEqualFloat64x4", argLength: 2, commutative: false},
{name: "MaskedAddFloat64x4", argLength: 3, commutative: true},
{name: "MaskedAndFloat64x4", argLength: 3, commutative: true},
{name: "MaskedAndNotFloat64x4", argLength: 3, commutative: false},
{name: "MaskedApproximateReciprocalFloat64x4", argLength: 2, commutative: false},
{name: "MaskedApproximateReciprocalOfSqrtFloat64x4", argLength: 2, commutative: false},
{name: "MaskedDivFloat64x4", argLength: 3, commutative: false},
@ -255,26 +219,20 @@ func simdGenericOps() []opData {
{name: "MaskedMulFloat64x4", argLength: 3, commutative: true},
{name: "MaskedMulByPowOf2Float64x4", argLength: 3, commutative: false},
{name: "MaskedNotEqualFloat64x4", argLength: 3, commutative: true},
{name: "MaskedOrFloat64x4", argLength: 3, commutative: true},
{name: "MaskedSqrtFloat64x4", argLength: 2, commutative: false},
{name: "MaskedSubFloat64x4", argLength: 3, commutative: false},
{name: "MaskedXorFloat64x4", argLength: 3, commutative: true},
{name: "MaxFloat64x4", argLength: 2, commutative: true},
{name: "MinFloat64x4", argLength: 2, commutative: true},
{name: "MulFloat64x4", argLength: 2, commutative: true},
{name: "MulByPowOf2Float64x4", argLength: 2, commutative: false},
{name: "NotEqualFloat64x4", argLength: 2, commutative: true},
{name: "OrFloat64x4", argLength: 2, commutative: true},
{name: "PairwiseAddFloat64x4", argLength: 2, commutative: false},
{name: "PairwiseSubFloat64x4", argLength: 2, commutative: false},
{name: "RoundFloat64x4", argLength: 1, commutative: false},
{name: "SqrtFloat64x4", argLength: 1, commutative: false},
{name: "SubFloat64x4", argLength: 2, commutative: false},
{name: "TruncFloat64x4", argLength: 1, commutative: false},
{name: "XorFloat64x4", argLength: 2, commutative: true},
{name: "AddFloat64x8", argLength: 2, commutative: true},
{name: "AndFloat64x8", argLength: 2, commutative: true},
{name: "AndNotFloat64x8", argLength: 2, commutative: false},
{name: "ApproximateReciprocalFloat64x8", argLength: 1, commutative: false},
{name: "ApproximateReciprocalOfSqrtFloat64x8", argLength: 1, commutative: false},
{name: "DivFloat64x8", argLength: 2, commutative: false},
@ -288,8 +246,6 @@ func simdGenericOps() []opData {
{name: "LessFloat64x8", argLength: 2, commutative: false},
{name: "LessEqualFloat64x8", argLength: 2, commutative: false},
{name: "MaskedAddFloat64x8", argLength: 3, commutative: true},
{name: "MaskedAndFloat64x8", argLength: 3, commutative: true},
{name: "MaskedAndNotFloat64x8", argLength: 3, commutative: false},
{name: "MaskedApproximateReciprocalFloat64x8", argLength: 2, commutative: false},
{name: "MaskedApproximateReciprocalOfSqrtFloat64x8", argLength: 2, commutative: false},
{name: "MaskedDivFloat64x8", argLength: 3, commutative: false},
@ -307,19 +263,15 @@ func simdGenericOps() []opData {
{name: "MaskedMulFloat64x8", argLength: 3, commutative: true},
{name: "MaskedMulByPowOf2Float64x8", argLength: 3, commutative: false},
{name: "MaskedNotEqualFloat64x8", argLength: 3, commutative: true},
{name: "MaskedOrFloat64x8", argLength: 3, commutative: true},
{name: "MaskedSqrtFloat64x8", argLength: 2, commutative: false},
{name: "MaskedSubFloat64x8", argLength: 3, commutative: false},
{name: "MaskedXorFloat64x8", argLength: 3, commutative: true},
{name: "MaxFloat64x8", argLength: 2, commutative: true},
{name: "MinFloat64x8", argLength: 2, commutative: true},
{name: "MulFloat64x8", argLength: 2, commutative: true},
{name: "MulByPowOf2Float64x8", argLength: 2, commutative: false},
{name: "NotEqualFloat64x8", argLength: 2, commutative: true},
{name: "OrFloat64x8", argLength: 2, commutative: true},
{name: "SqrtFloat64x8", argLength: 1, commutative: false},
{name: "SubFloat64x8", argLength: 2, commutative: false},
{name: "XorFloat64x8", argLength: 2, commutative: true},
{name: "AbsoluteInt16x16", argLength: 1, commutative: false},
{name: "AddInt16x16", argLength: 2, commutative: true},
{name: "AndInt16x16", argLength: 2, commutative: true},

1104
src/cmd/compile/internal/ssa/opGen.go
View file

File diff suppressed because it is too large Load diff

552
src/cmd/compile/internal/ssa/rewriteAMD64.go
View file

@ -729,24 +729,6 @@ func rewriteValueAMD64(v *Value) bool {
case OpAndB:
v.Op = OpAMD64ANDL
return true
case OpAndFloat32x16:
v.Op = OpAMD64VANDPS512
return true
case OpAndFloat32x4:
v.Op = OpAMD64VANDPS128
return true
case OpAndFloat32x8:
v.Op = OpAMD64VANDPS256
return true
case OpAndFloat64x2:
v.Op = OpAMD64VANDPD128
return true
case OpAndFloat64x4:
v.Op = OpAMD64VANDPD256
return true
case OpAndFloat64x8:
v.Op = OpAMD64VANDPD512
return true
case OpAndInt16x16:
v.Op = OpAMD64VPAND256
return true
@ -777,24 +759,6 @@ func rewriteValueAMD64(v *Value) bool {
case OpAndInt8x32:
v.Op = OpAMD64VPAND256
return true
case OpAndNotFloat32x16:
v.Op = OpAMD64VANDNPS512
return true
case OpAndNotFloat32x4:
v.Op = OpAMD64VANDNPS128
return true
case OpAndNotFloat32x8:
v.Op = OpAMD64VANDNPS256
return true
case OpAndNotFloat64x2:
v.Op = OpAMD64VANDNPD128
return true
case OpAndNotFloat64x4:
v.Op = OpAMD64VANDNPD256
return true
case OpAndNotFloat64x8:
v.Op = OpAMD64VANDNPD512
return true
case OpAndNotInt16x16:
v.Op = OpAMD64VPANDN256
return true
@ -1877,18 +1841,6 @@ func rewriteValueAMD64(v *Value) bool {
return rewriteValueAMD64_OpMaskedAddUint8x32(v)
case OpMaskedAddUint8x64:
return rewriteValueAMD64_OpMaskedAddUint8x64(v)
case OpMaskedAndFloat32x16:
return rewriteValueAMD64_OpMaskedAndFloat32x16(v)
case OpMaskedAndFloat32x4:
return rewriteValueAMD64_OpMaskedAndFloat32x4(v)
case OpMaskedAndFloat32x8:
return rewriteValueAMD64_OpMaskedAndFloat32x8(v)
case OpMaskedAndFloat64x2:
return rewriteValueAMD64_OpMaskedAndFloat64x2(v)
case OpMaskedAndFloat64x4:
return rewriteValueAMD64_OpMaskedAndFloat64x4(v)
case OpMaskedAndFloat64x8:
return rewriteValueAMD64_OpMaskedAndFloat64x8(v)
case OpMaskedAndInt32x16:
return rewriteValueAMD64_OpMaskedAndInt32x16(v)
case OpMaskedAndInt32x4:
@ -1901,18 +1853,6 @@ func rewriteValueAMD64(v *Value) bool {
return rewriteValueAMD64_OpMaskedAndInt64x4(v)
case OpMaskedAndInt64x8:
return rewriteValueAMD64_OpMaskedAndInt64x8(v)
case OpMaskedAndNotFloat32x16:
return rewriteValueAMD64_OpMaskedAndNotFloat32x16(v)
case OpMaskedAndNotFloat32x4:
return rewriteValueAMD64_OpMaskedAndNotFloat32x4(v)
case OpMaskedAndNotFloat32x8:
return rewriteValueAMD64_OpMaskedAndNotFloat32x8(v)
case OpMaskedAndNotFloat64x2:
return rewriteValueAMD64_OpMaskedAndNotFloat64x2(v)
case OpMaskedAndNotFloat64x4:
return rewriteValueAMD64_OpMaskedAndNotFloat64x4(v)
case OpMaskedAndNotFloat64x8:
return rewriteValueAMD64_OpMaskedAndNotFloat64x8(v)
case OpMaskedAndNotInt32x16:
return rewriteValueAMD64_OpMaskedAndNotInt32x16(v)
case OpMaskedAndNotInt32x4:
@ -2681,18 +2621,6 @@ func rewriteValueAMD64(v *Value) bool {
return rewriteValueAMD64_OpMaskedNotEqualUint8x32(v)
case OpMaskedNotEqualUint8x64:
return rewriteValueAMD64_OpMaskedNotEqualUint8x64(v)
case OpMaskedOrFloat32x16:
return rewriteValueAMD64_OpMaskedOrFloat32x16(v)
case OpMaskedOrFloat32x4:
return rewriteValueAMD64_OpMaskedOrFloat32x4(v)
case OpMaskedOrFloat32x8:
return rewriteValueAMD64_OpMaskedOrFloat32x8(v)
case OpMaskedOrFloat64x2:
return rewriteValueAMD64_OpMaskedOrFloat64x2(v)
case OpMaskedOrFloat64x4:
return rewriteValueAMD64_OpMaskedOrFloat64x4(v)
case OpMaskedOrFloat64x8:
return rewriteValueAMD64_OpMaskedOrFloat64x8(v)
case OpMaskedOrInt32x16:
return rewriteValueAMD64_OpMaskedOrInt32x16(v)
case OpMaskedOrInt32x4:
@ -3335,18 +3263,6 @@ func rewriteValueAMD64(v *Value) bool {
return rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x4(v)
case OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x8:
return rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x8(v)
case OpMaskedXorFloat32x16:
return rewriteValueAMD64_OpMaskedXorFloat32x16(v)
case OpMaskedXorFloat32x4:
return rewriteValueAMD64_OpMaskedXorFloat32x4(v)
case OpMaskedXorFloat32x8:
return rewriteValueAMD64_OpMaskedXorFloat32x8(v)
case OpMaskedXorFloat64x2:
return rewriteValueAMD64_OpMaskedXorFloat64x2(v)
case OpMaskedXorFloat64x4:
return rewriteValueAMD64_OpMaskedXorFloat64x4(v)
case OpMaskedXorFloat64x8:
return rewriteValueAMD64_OpMaskedXorFloat64x8(v)
case OpMaskedXorInt32x16:
return rewriteValueAMD64_OpMaskedXorInt32x16(v)
case OpMaskedXorInt32x4:
@ -3823,24 +3739,6 @@ func rewriteValueAMD64(v *Value) bool {
case OpOrB:
v.Op = OpAMD64ORL
return true
case OpOrFloat32x16:
v.Op = OpAMD64VORPS512
return true
case OpOrFloat32x4:
v.Op = OpAMD64VORPS128
return true
case OpOrFloat32x8:
v.Op = OpAMD64VORPS256
return true
case OpOrFloat64x2:
v.Op = OpAMD64VORPD128
return true
case OpOrFloat64x4:
v.Op = OpAMD64VORPD256
return true
case OpOrFloat64x8:
v.Op = OpAMD64VORPD512
return true
case OpOrInt16x16:
v.Op = OpAMD64VPOR256
return true
@ -5172,24 +5070,6 @@ func rewriteValueAMD64(v *Value) bool {
case OpXor8:
v.Op = OpAMD64XORL
return true
case OpXorFloat32x16:
v.Op = OpAMD64VXORPS512
return true
case OpXorFloat32x4:
v.Op = OpAMD64VXORPS128
return true
case OpXorFloat32x8:
v.Op = OpAMD64VXORPS256
return true
case OpXorFloat64x2:
v.Op = OpAMD64VXORPD128
return true
case OpXorFloat64x4:
v.Op = OpAMD64VXORPD256
return true
case OpXorFloat64x8:
v.Op = OpAMD64VXORPD512
return true
case OpXorInt16x16:
v.Op = OpAMD64VPXOR256
return true
@ -35257,114 +35137,6 @@ func rewriteValueAMD64_OpMaskedAddUint8x64(v *Value) bool {
return true
}
}
func rewriteValueAMD64_OpMaskedAndFloat32x16(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedAndFloat32x16 x y mask)
// result: (VANDPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VANDPSMasked512)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedAndFloat32x4(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedAndFloat32x4 x y mask)
// result: (VANDPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VANDPSMasked128)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedAndFloat32x8(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedAndFloat32x8 x y mask)
// result: (VANDPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VANDPSMasked256)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedAndFloat64x2(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedAndFloat64x2 x y mask)
// result: (VANDPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VANDPDMasked128)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedAndFloat64x4(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedAndFloat64x4 x y mask)
// result: (VANDPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VANDPDMasked256)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedAndFloat64x8(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedAndFloat64x8 x y mask)
// result: (VANDPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VANDPDMasked512)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedAndInt32x16(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
@ -35473,114 +35245,6 @@ func rewriteValueAMD64_OpMaskedAndInt64x8(v *Value) bool {
return true
}
}
func rewriteValueAMD64_OpMaskedAndNotFloat32x16(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedAndNotFloat32x16 x y mask)
// result: (VANDNPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VANDNPSMasked512)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedAndNotFloat32x4(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedAndNotFloat32x4 x y mask)
// result: (VANDNPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VANDNPSMasked128)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedAndNotFloat32x8(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedAndNotFloat32x8 x y mask)
// result: (VANDNPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VANDNPSMasked256)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedAndNotFloat64x2(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedAndNotFloat64x2 x y mask)
// result: (VANDNPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VANDNPDMasked128)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedAndNotFloat64x4(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedAndNotFloat64x4 x y mask)
// result: (VANDNPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VANDNPDMasked256)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedAndNotFloat64x8(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedAndNotFloat64x8 x y mask)
// result: (VANDNPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VANDNPDMasked512)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedAndNotInt32x16(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
@ -43261,114 +42925,6 @@ func rewriteValueAMD64_OpMaskedNotEqualUint8x64(v *Value) bool {
return true
}
}
func rewriteValueAMD64_OpMaskedOrFloat32x16(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedOrFloat32x16 x y mask)
// result: (VORPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VORPSMasked512)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedOrFloat32x4(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedOrFloat32x4 x y mask)
// result: (VORPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VORPSMasked128)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedOrFloat32x8(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedOrFloat32x8 x y mask)
// result: (VORPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VORPSMasked256)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedOrFloat64x2(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedOrFloat64x2 x y mask)
// result: (VORPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VORPDMasked128)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedOrFloat64x4(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedOrFloat64x4 x y mask)
// result: (VORPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VORPDMasked256)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedOrFloat64x8(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedOrFloat64x8 x y mask)
// result: (VORPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VORPDMasked512)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedOrInt32x16(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
@ -49267,114 +48823,6 @@ func rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x8(v *Va
return true
}
}
func rewriteValueAMD64_OpMaskedXorFloat32x16(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedXorFloat32x16 x y mask)
// result: (VXORPSMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VXORPSMasked512)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedXorFloat32x4(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedXorFloat32x4 x y mask)
// result: (VXORPSMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VXORPSMasked128)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedXorFloat32x8(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedXorFloat32x8 x y mask)
// result: (VXORPSMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VXORPSMasked256)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedXorFloat64x2(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedXorFloat64x2 x y mask)
// result: (VXORPDMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VXORPDMasked128)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedXorFloat64x4(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedXorFloat64x4 x y mask)
// result: (VXORPDMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VXORPDMasked256)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedXorFloat64x8(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]
v_0 := v.Args[0]
b := v.Block
// match: (MaskedXorFloat64x8 x y mask)
// result: (VXORPDMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
for {
x := v_0
y := v_1
mask := v_2
v.reset(OpAMD64VXORPDMasked512)
v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask)
v0.AddArg(mask)
v.AddArg3(x, y, v0)
return true
}
}
func rewriteValueAMD64_OpMaskedXorInt32x16(v *Value) bool {
v_2 := v.Args[2]
v_1 := v.Args[1]

48
src/cmd/compile/internal/ssagen/simdintrinsics.go
View file

@ -57,12 +57,6 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
addF(simdPackage, "Float32x8.AddSub", opLen2(ssa.OpAddSubFloat32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float64x2.AddSub", opLen2(ssa.OpAddSubFloat64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float64x4.AddSub", opLen2(ssa.OpAddSubFloat64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float32x4.And", opLen2(ssa.OpAndFloat32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float32x8.And", opLen2(ssa.OpAndFloat32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float32x16.And", opLen2(ssa.OpAndFloat32x16, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float64x2.And", opLen2(ssa.OpAndFloat64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float64x4.And", opLen2(ssa.OpAndFloat64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float64x8.And", opLen2(ssa.OpAndFloat64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Int8x16.And", opLen2(ssa.OpAndInt8x16, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Int8x32.And", opLen2(ssa.OpAndInt8x32, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Int16x8.And", opLen2(ssa.OpAndInt16x8, types.TypeVec128), sys.AMD64)
@ -83,12 +77,6 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
addF(simdPackage, "Uint64x2.And", opLen2(ssa.OpAndUint64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Uint64x4.And", opLen2(ssa.OpAndUint64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Uint64x8.And", opLen2(ssa.OpAndUint64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float32x4.AndNot", opLen2(ssa.OpAndNotFloat32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float32x8.AndNot", opLen2(ssa.OpAndNotFloat32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float32x16.AndNot", opLen2(ssa.OpAndNotFloat32x16, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float64x2.AndNot", opLen2(ssa.OpAndNotFloat64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float64x4.AndNot", opLen2(ssa.OpAndNotFloat64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float64x8.AndNot", opLen2(ssa.OpAndNotFloat64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Int8x16.AndNot", opLen2(ssa.OpAndNotInt8x16, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Int8x32.AndNot", opLen2(ssa.OpAndNotInt8x32, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Int16x8.AndNot", opLen2(ssa.OpAndNotInt16x8, types.TypeVec128), sys.AMD64)
@ -421,12 +409,6 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
addF(simdPackage, "Uint64x2.MaskedAdd", opLen3(ssa.OpMaskedAddUint64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Uint64x4.MaskedAdd", opLen3(ssa.OpMaskedAddUint64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Uint64x8.MaskedAdd", opLen3(ssa.OpMaskedAddUint64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float32x4.MaskedAnd", opLen3(ssa.OpMaskedAndFloat32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float32x8.MaskedAnd", opLen3(ssa.OpMaskedAndFloat32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float32x16.MaskedAnd", opLen3(ssa.OpMaskedAndFloat32x16, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float64x2.MaskedAnd", opLen3(ssa.OpMaskedAndFloat64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float64x4.MaskedAnd", opLen3(ssa.OpMaskedAndFloat64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float64x8.MaskedAnd", opLen3(ssa.OpMaskedAndFloat64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Int32x4.MaskedAnd", opLen3(ssa.OpMaskedAndInt32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Int32x8.MaskedAnd", opLen3(ssa.OpMaskedAndInt32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Int32x16.MaskedAnd", opLen3(ssa.OpMaskedAndInt32x16, types.TypeVec512), sys.AMD64)
@ -439,12 +421,6 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
addF(simdPackage, "Uint64x2.MaskedAnd", opLen3(ssa.OpMaskedAndUint64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Uint64x4.MaskedAnd", opLen3(ssa.OpMaskedAndUint64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Uint64x8.MaskedAnd", opLen3(ssa.OpMaskedAndUint64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float32x4.MaskedAndNot", opLen3(ssa.OpMaskedAndNotFloat32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float32x8.MaskedAndNot", opLen3(ssa.OpMaskedAndNotFloat32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float32x16.MaskedAndNot", opLen3(ssa.OpMaskedAndNotFloat32x16, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float64x2.MaskedAndNot", opLen3(ssa.OpMaskedAndNotFloat64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float64x4.MaskedAndNot", opLen3(ssa.OpMaskedAndNotFloat64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float64x8.MaskedAndNot", opLen3(ssa.OpMaskedAndNotFloat64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Int32x4.MaskedAndNot", opLen3(ssa.OpMaskedAndNotInt32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Int32x8.MaskedAndNot", opLen3(ssa.OpMaskedAndNotInt32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Int32x16.MaskedAndNot", opLen3(ssa.OpMaskedAndNotInt32x16, types.TypeVec512), sys.AMD64)
@ -823,12 +799,6 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
addF(simdPackage, "Uint64x2.MaskedNotEqual", opLen3(ssa.OpMaskedNotEqualUint64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Uint64x4.MaskedNotEqual", opLen3(ssa.OpMaskedNotEqualUint64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Uint64x8.MaskedNotEqual", opLen3(ssa.OpMaskedNotEqualUint64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float32x4.MaskedOr", opLen3(ssa.OpMaskedOrFloat32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float32x8.MaskedOr", opLen3(ssa.OpMaskedOrFloat32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float32x16.MaskedOr", opLen3(ssa.OpMaskedOrFloat32x16, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float64x2.MaskedOr", opLen3(ssa.OpMaskedOrFloat64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float64x4.MaskedOr", opLen3(ssa.OpMaskedOrFloat64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float64x8.MaskedOr", opLen3(ssa.OpMaskedOrFloat64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Int32x4.MaskedOr", opLen3(ssa.OpMaskedOrInt32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Int32x8.MaskedOr", opLen3(ssa.OpMaskedOrInt32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Int32x16.MaskedOr", opLen3(ssa.OpMaskedOrInt32x16, types.TypeVec512), sys.AMD64)
@ -1150,12 +1120,6 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
addF(simdPackage, "Uint32x4.MaskedUnsignedSignedQuadDotProdAccumulate", opLen4(ssa.OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Uint32x8.MaskedUnsignedSignedQuadDotProdAccumulate", opLen4(ssa.OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Uint32x16.MaskedUnsignedSignedQuadDotProdAccumulate", opLen4(ssa.OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x16, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float32x4.MaskedXor", opLen3(ssa.OpMaskedXorFloat32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float32x8.MaskedXor", opLen3(ssa.OpMaskedXorFloat32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float32x16.MaskedXor", opLen3(ssa.OpMaskedXorFloat32x16, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float64x2.MaskedXor", opLen3(ssa.OpMaskedXorFloat64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float64x4.MaskedXor", opLen3(ssa.OpMaskedXorFloat64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float64x8.MaskedXor", opLen3(ssa.OpMaskedXorFloat64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Int32x4.MaskedXor", opLen3(ssa.OpMaskedXorInt32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Int32x8.MaskedXor", opLen3(ssa.OpMaskedXorInt32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Int32x16.MaskedXor", opLen3(ssa.OpMaskedXorInt32x16, types.TypeVec512), sys.AMD64)
@ -1295,12 +1259,6 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
addF(simdPackage, "Uint64x2.NotEqual", opLen2(ssa.OpNotEqualUint64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Uint64x4.NotEqual", opLen2(ssa.OpNotEqualUint64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Uint64x8.NotEqual", opLen2(ssa.OpNotEqualUint64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float32x4.Or", opLen2(ssa.OpOrFloat32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float32x8.Or", opLen2(ssa.OpOrFloat32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float32x16.Or", opLen2(ssa.OpOrFloat32x16, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float64x2.Or", opLen2(ssa.OpOrFloat64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float64x4.Or", opLen2(ssa.OpOrFloat64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float64x8.Or", opLen2(ssa.OpOrFloat64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Int8x16.Or", opLen2(ssa.OpOrInt8x16, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Int8x32.Or", opLen2(ssa.OpOrInt8x32, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Int16x8.Or", opLen2(ssa.OpOrInt16x8, types.TypeVec128), sys.AMD64)
@ -1710,12 +1668,6 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
addF(simdPackage, "Uint32x4.UnsignedSignedQuadDotProdAccumulate", opLen3(ssa.OpUnsignedSignedQuadDotProdAccumulateUint32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Uint32x8.UnsignedSignedQuadDotProdAccumulate", opLen3(ssa.OpUnsignedSignedQuadDotProdAccumulateUint32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Uint32x16.UnsignedSignedQuadDotProdAccumulate", opLen3(ssa.OpUnsignedSignedQuadDotProdAccumulateUint32x16, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float32x4.Xor", opLen2(ssa.OpXorFloat32x4, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float32x8.Xor", opLen2(ssa.OpXorFloat32x8, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float32x16.Xor", opLen2(ssa.OpXorFloat32x16, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Float64x2.Xor", opLen2(ssa.OpXorFloat64x2, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Float64x4.Xor", opLen2(ssa.OpXorFloat64x4, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Float64x8.Xor", opLen2(ssa.OpXorFloat64x8, types.TypeVec512), sys.AMD64)
addF(simdPackage, "Int8x16.Xor", opLen2(ssa.OpXorInt8x16, types.TypeVec128), sys.AMD64)
addF(simdPackage, "Int8x32.Xor", opLen2(ssa.OpXorInt8x32, types.TypeVec256), sys.AMD64)
addF(simdPackage, "Int16x8.Xor", opLen2(ssa.OpXorInt16x8, types.TypeVec128), sys.AMD64)

96
src/simd/simd_wrapped_test.go
View file

@ -20,10 +20,6 @@ func testFloat32x4Binary(t *testing.T, v0 []float32, v1 []float32, want []float3
gotv = vec0.Add(vec1)
case "AddSub":
gotv = vec0.AddSub(vec1)
case "And":
gotv = vec0.And(vec1)
case "AndNot":
gotv = vec0.AndNot(vec1)
case "Div":
gotv = vec0.Div(vec1)
case "Max":
@ -34,16 +30,12 @@ func testFloat32x4Binary(t *testing.T, v0 []float32, v1 []float32, want []float3
gotv = vec0.Mul(vec1)
case "MulByPowOf2":
gotv = vec0.MulByPowOf2(vec1)
case "Or":
gotv = vec0.Or(vec1)
case "PairwiseAdd":
gotv = vec0.PairwiseAdd(vec1)
case "PairwiseSub":
gotv = vec0.PairwiseSub(vec1)
case "Sub":
gotv = vec0.Sub(vec1)
case "Xor":
gotv = vec0.Xor(vec1)
default:
t.Errorf("Unknown method: Float32x4.%s", which)
@ -66,10 +58,6 @@ func testFloat32x4BinaryMasked(t *testing.T, v0 []float32, v1 []float32, v2 []in
switch which {
case "MaskedAdd":
gotv = vec0.MaskedAdd(vec1, vec2.AsMask32x4())
case "MaskedAnd":
gotv = vec0.MaskedAnd(vec1, vec2.AsMask32x4())
case "MaskedAndNot":
gotv = vec0.MaskedAndNot(vec1, vec2.AsMask32x4())
case "MaskedDiv":
gotv = vec0.MaskedDiv(vec1, vec2.AsMask32x4())
case "MaskedMax":
@ -80,12 +68,8 @@ func testFloat32x4BinaryMasked(t *testing.T, v0 []float32, v1 []float32, v2 []in
gotv = vec0.MaskedMul(vec1, vec2.AsMask32x4())
case "MaskedMulByPowOf2":
gotv = vec0.MaskedMulByPowOf2(vec1, vec2.AsMask32x4())
case "MaskedOr":
gotv = vec0.MaskedOr(vec1, vec2.AsMask32x4())
case "MaskedSub":
gotv = vec0.MaskedSub(vec1, vec2.AsMask32x4())
case "MaskedXor":
gotv = vec0.MaskedXor(vec1, vec2.AsMask32x4())
default:
t.Errorf("Unknown method: Float32x4.%s", which)
@ -286,10 +270,6 @@ func testFloat32x8Binary(t *testing.T, v0 []float32, v1 []float32, want []float3
gotv = vec0.Add(vec1)
case "AddSub":
gotv = vec0.AddSub(vec1)
case "And":
gotv = vec0.And(vec1)
case "AndNot":
gotv = vec0.AndNot(vec1)
case "Div":
gotv = vec0.Div(vec1)
case "Max":
@ -300,16 +280,12 @@ func testFloat32x8Binary(t *testing.T, v0 []float32, v1 []float32, want []float3
gotv = vec0.Mul(vec1)
case "MulByPowOf2":
gotv = vec0.MulByPowOf2(vec1)
case "Or":
gotv = vec0.Or(vec1)
case "PairwiseAdd":
gotv = vec0.PairwiseAdd(vec1)
case "PairwiseSub":
gotv = vec0.PairwiseSub(vec1)
case "Sub":
gotv = vec0.Sub(vec1)
case "Xor":
gotv = vec0.Xor(vec1)
default:
t.Errorf("Unknown method: Float32x8.%s", which)
@ -332,10 +308,6 @@ func testFloat32x8BinaryMasked(t *testing.T, v0 []float32, v1 []float32, v2 []in
switch which {
case "MaskedAdd":
gotv = vec0.MaskedAdd(vec1, vec2.AsMask32x8())
case "MaskedAnd":
gotv = vec0.MaskedAnd(vec1, vec2.AsMask32x8())
case "MaskedAndNot":
gotv = vec0.MaskedAndNot(vec1, vec2.AsMask32x8())
case "MaskedDiv":
gotv = vec0.MaskedDiv(vec1, vec2.AsMask32x8())
case "MaskedMax":
@ -346,12 +318,8 @@ func testFloat32x8BinaryMasked(t *testing.T, v0 []float32, v1 []float32, v2 []in
gotv = vec0.MaskedMul(vec1, vec2.AsMask32x8())
case "MaskedMulByPowOf2":
gotv = vec0.MaskedMulByPowOf2(vec1, vec2.AsMask32x8())
case "MaskedOr":
gotv = vec0.MaskedOr(vec1, vec2.AsMask32x8())
case "MaskedSub":
gotv = vec0.MaskedSub(vec1, vec2.AsMask32x8())
case "MaskedXor":
gotv = vec0.MaskedXor(vec1, vec2.AsMask32x8())
default:
t.Errorf("Unknown method: Float32x8.%s", which)
@ -550,10 +518,6 @@ func testFloat32x16Binary(t *testing.T, v0 []float32, v1 []float32, want []float
switch which {
case "Add":
gotv = vec0.Add(vec1)
case "And":
gotv = vec0.And(vec1)
case "AndNot":
gotv = vec0.AndNot(vec1)
case "Div":
gotv = vec0.Div(vec1)
case "Max":
@ -564,12 +528,8 @@ func testFloat32x16Binary(t *testing.T, v0 []float32, v1 []float32, want []float
gotv = vec0.Mul(vec1)
case "MulByPowOf2":
gotv = vec0.MulByPowOf2(vec1)
case "Or":
gotv = vec0.Or(vec1)
case "Sub":
gotv = vec0.Sub(vec1)
case "Xor":
gotv = vec0.Xor(vec1)
default:
t.Errorf("Unknown method: Float32x16.%s", which)
@ -592,10 +552,6 @@ func testFloat32x16BinaryMasked(t *testing.T, v0 []float32, v1 []float32, v2 []i
switch which {
case "MaskedAdd":
gotv = vec0.MaskedAdd(vec1, vec2.AsMask32x16())
case "MaskedAnd":
gotv = vec0.MaskedAnd(vec1, vec2.AsMask32x16())
case "MaskedAndNot":
gotv = vec0.MaskedAndNot(vec1, vec2.AsMask32x16())
case "MaskedDiv":
gotv = vec0.MaskedDiv(vec1, vec2.AsMask32x16())
case "MaskedMax":
@ -606,12 +562,8 @@ func testFloat32x16BinaryMasked(t *testing.T, v0 []float32, v1 []float32, v2 []i
gotv = vec0.MaskedMul(vec1, vec2.AsMask32x16())
case "MaskedMulByPowOf2":
gotv = vec0.MaskedMulByPowOf2(vec1, vec2.AsMask32x16())
case "MaskedOr":
gotv = vec0.MaskedOr(vec1, vec2.AsMask32x16())
case "MaskedSub":
gotv = vec0.MaskedSub(vec1, vec2.AsMask32x16())
case "MaskedXor":
gotv = vec0.MaskedXor(vec1, vec2.AsMask32x16())
default:
t.Errorf("Unknown method: Float32x16.%s", which)
@ -804,10 +756,6 @@ func testFloat64x2Binary(t *testing.T, v0 []float64, v1 []float64, want []float6
gotv = vec0.Add(vec1)
case "AddSub":
gotv = vec0.AddSub(vec1)
case "And":
gotv = vec0.And(vec1)
case "AndNot":
gotv = vec0.AndNot(vec1)
case "Div":
gotv = vec0.Div(vec1)
case "DotProdBroadcast":
@ -820,16 +768,12 @@ func testFloat64x2Binary(t *testing.T, v0 []float64, v1 []float64, want []float6
gotv = vec0.Mul(vec1)
case "MulByPowOf2":
gotv = vec0.MulByPowOf2(vec1)
case "Or":
gotv = vec0.Or(vec1)
case "PairwiseAdd":
gotv = vec0.PairwiseAdd(vec1)
case "PairwiseSub":
gotv = vec0.PairwiseSub(vec1)
case "Sub":
gotv = vec0.Sub(vec1)
case "Xor":
gotv = vec0.Xor(vec1)
default:
t.Errorf("Unknown method: Float64x2.%s", which)
@ -852,10 +796,6 @@ func testFloat64x2BinaryMasked(t *testing.T, v0 []float64, v1 []float64, v2 []in
switch which {
case "MaskedAdd":
gotv = vec0.MaskedAdd(vec1, vec2.AsMask64x2())
case "MaskedAnd":
gotv = vec0.MaskedAnd(vec1, vec2.AsMask64x2())
case "MaskedAndNot":
gotv = vec0.MaskedAndNot(vec1, vec2.AsMask64x2())
case "MaskedDiv":
gotv = vec0.MaskedDiv(vec1, vec2.AsMask64x2())
case "MaskedMax":
@ -866,12 +806,8 @@ func testFloat64x2BinaryMasked(t *testing.T, v0 []float64, v1 []float64, v2 []in
gotv = vec0.MaskedMul(vec1, vec2.AsMask64x2())
case "MaskedMulByPowOf2":
gotv = vec0.MaskedMulByPowOf2(vec1, vec2.AsMask64x2())
case "MaskedOr":
gotv = vec0.MaskedOr(vec1, vec2.AsMask64x2())
case "MaskedSub":
gotv = vec0.MaskedSub(vec1, vec2.AsMask64x2())
case "MaskedXor":
gotv = vec0.MaskedXor(vec1, vec2.AsMask64x2())
default:
t.Errorf("Unknown method: Float64x2.%s", which)
@ -1072,10 +1008,6 @@ func testFloat64x4Binary(t *testing.T, v0 []float64, v1 []float64, want []float6
gotv = vec0.Add(vec1)
case "AddSub":
gotv = vec0.AddSub(vec1)
case "And":
gotv = vec0.And(vec1)
case "AndNot":
gotv = vec0.AndNot(vec1)
case "Div":
gotv = vec0.Div(vec1)
case "Max":
@ -1086,16 +1018,12 @@ func testFloat64x4Binary(t *testing.T, v0 []float64, v1 []float64, want []float6
gotv = vec0.Mul(vec1)
case "MulByPowOf2":
gotv = vec0.MulByPowOf2(vec1)
case "Or":
gotv = vec0.Or(vec1)
case "PairwiseAdd":
gotv = vec0.PairwiseAdd(vec1)
case "PairwiseSub":
gotv = vec0.PairwiseSub(vec1)
case "Sub":
gotv = vec0.Sub(vec1)
case "Xor":
gotv = vec0.Xor(vec1)
default:
t.Errorf("Unknown method: Float64x4.%s", which)
@ -1118,10 +1046,6 @@ func testFloat64x4BinaryMasked(t *testing.T, v0 []float64, v1 []float64, v2 []in
switch which {
case "MaskedAdd":
gotv = vec0.MaskedAdd(vec1, vec2.AsMask64x4())
case "MaskedAnd":
gotv = vec0.MaskedAnd(vec1, vec2.AsMask64x4())
case "MaskedAndNot":
gotv = vec0.MaskedAndNot(vec1, vec2.AsMask64x4())
case "MaskedDiv":
gotv = vec0.MaskedDiv(vec1, vec2.AsMask64x4())
case "MaskedMax":
@ -1132,12 +1056,8 @@ func testFloat64x4BinaryMasked(t *testing.T, v0 []float64, v1 []float64, v2 []in
gotv = vec0.MaskedMul(vec1, vec2.AsMask64x4())
case "MaskedMulByPowOf2":
gotv = vec0.MaskedMulByPowOf2(vec1, vec2.AsMask64x4())
case "MaskedOr":
gotv = vec0.MaskedOr(vec1, vec2.AsMask64x4())
case "MaskedSub":
gotv = vec0.MaskedSub(vec1, vec2.AsMask64x4())
case "MaskedXor":
gotv = vec0.MaskedXor(vec1, vec2.AsMask64x4())
default:
t.Errorf("Unknown method: Float64x4.%s", which)
@ -1336,10 +1256,6 @@ func testFloat64x8Binary(t *testing.T, v0 []float64, v1 []float64, want []float6
switch which {
case "Add":
gotv = vec0.Add(vec1)
case "And":
gotv = vec0.And(vec1)
case "AndNot":
gotv = vec0.AndNot(vec1)
case "Div":
gotv = vec0.Div(vec1)
case "Max":
@ -1350,12 +1266,8 @@ func testFloat64x8Binary(t *testing.T, v0 []float64, v1 []float64, want []float6
gotv = vec0.Mul(vec1)
case "MulByPowOf2":
gotv = vec0.MulByPowOf2(vec1)
case "Or":
gotv = vec0.Or(vec1)
case "Sub":
gotv = vec0.Sub(vec1)
case "Xor":
gotv = vec0.Xor(vec1)
default:
t.Errorf("Unknown method: Float64x8.%s", which)
@ -1378,10 +1290,6 @@ func testFloat64x8BinaryMasked(t *testing.T, v0 []float64, v1 []float64, v2 []in
switch which {
case "MaskedAdd":
gotv = vec0.MaskedAdd(vec1, vec2.AsMask64x8())
case "MaskedAnd":
gotv = vec0.MaskedAnd(vec1, vec2.AsMask64x8())
case "MaskedAndNot":
gotv = vec0.MaskedAndNot(vec1, vec2.AsMask64x8())
case "MaskedDiv":
gotv = vec0.MaskedDiv(vec1, vec2.AsMask64x8())
case "MaskedMax":
@ -1392,12 +1300,8 @@ func testFloat64x8BinaryMasked(t *testing.T, v0 []float64, v1 []float64, v2 []in
gotv = vec0.MaskedMul(vec1, vec2.AsMask64x8())
case "MaskedMulByPowOf2":
gotv = vec0.MaskedMulByPowOf2(vec1, vec2.AsMask64x8())
case "MaskedOr":
gotv = vec0.MaskedOr(vec1, vec2.AsMask64x8())
case "MaskedSub":
gotv = vec0.MaskedSub(vec1, vec2.AsMask64x8())
case "MaskedXor":
gotv = vec0.MaskedXor(vec1, vec2.AsMask64x8())
default:
t.Errorf("Unknown method: Float64x8.%s", which)

240
src/simd/stubs_amd64.go
View file

@ -242,36 +242,6 @@ func (x Float64x4) AddSub(y Float64x4) Float64x4
/* And */
// And performs a bitwise AND operation between two vectors.
//
// Asm: VANDPS, CPU Feature: AVX
func (x Float32x4) And(y Float32x4) Float32x4
// And performs a bitwise AND operation between two vectors.
//
// Asm: VANDPS, CPU Feature: AVX
func (x Float32x8) And(y Float32x8) Float32x8
// And performs a masked bitwise AND operation between two vectors.
//
// Asm: VANDPS, CPU Feature: AVX512EVEX
func (x Float32x16) And(y Float32x16) Float32x16
// And performs a bitwise AND operation between two vectors.
//
// Asm: VANDPD, CPU Feature: AVX
func (x Float64x2) And(y Float64x2) Float64x2
// And performs a bitwise AND operation between two vectors.
//
// Asm: VANDPD, CPU Feature: AVX
func (x Float64x4) And(y Float64x4) Float64x4
// And performs a masked bitwise AND operation between two vectors.
//
// Asm: VANDPD, CPU Feature: AVX512EVEX
func (x Float64x8) And(y Float64x8) Float64x8
// And performs a bitwise AND operation between two vectors.
//
// Asm: VPAND, CPU Feature: AVX
@ -374,36 +344,6 @@ func (x Uint64x8) And(y Uint64x8) Uint64x8
/* AndNot */
// AndNot performs a bitwise AND NOT operation between two vectors.
//
// Asm: VANDNPS, CPU Feature: AVX
func (x Float32x4) AndNot(y Float32x4) Float32x4
// AndNot performs a bitwise AND NOT operation between two vectors.
//
// Asm: VANDNPS, CPU Feature: AVX
func (x Float32x8) AndNot(y Float32x8) Float32x8
// AndNot performs a masked bitwise AND NOT operation between two vectors.
//
// Asm: VANDNPS, CPU Feature: AVX512EVEX
func (x Float32x16) AndNot(y Float32x16) Float32x16
// AndNot performs a bitwise AND NOT operation between two vectors.
//
// Asm: VANDNPD, CPU Feature: AVX
func (x Float64x2) AndNot(y Float64x2) Float64x2
// AndNot performs a bitwise AND NOT operation between two vectors.
//
// Asm: VANDNPD, CPU Feature: AVX
func (x Float64x4) AndNot(y Float64x4) Float64x4
// AndNot performs a masked bitwise AND NOT operation between two vectors.
//
// Asm: VANDNPD, CPU Feature: AVX512EVEX
func (x Float64x8) AndNot(y Float64x8) Float64x8
// AndNot performs a bitwise AND NOT operation between two vectors.
//
// Asm: VPANDN, CPU Feature: AVX
@ -2148,36 +2088,6 @@ func (x Uint64x8) MaskedAdd(y Uint64x8, z Mask64x8) Uint64x8
/* MaskedAnd */
// And performs a masked bitwise AND operation between two vectors.
//
// Asm: VANDPS, CPU Feature: AVX512EVEX
func (x Float32x4) MaskedAnd(y Float32x4, z Mask32x4) Float32x4
// And performs a masked bitwise AND operation between two vectors.
//
// Asm: VANDPS, CPU Feature: AVX512EVEX
func (x Float32x8) MaskedAnd(y Float32x8, z Mask32x8) Float32x8
// And performs a masked bitwise AND operation between two vectors.
//
// Asm: VANDPS, CPU Feature: AVX512EVEX
func (x Float32x16) MaskedAnd(y Float32x16, z Mask32x16) Float32x16
// And performs a masked bitwise AND operation between two vectors.
//
// Asm: VANDPD, CPU Feature: AVX512EVEX
func (x Float64x2) MaskedAnd(y Float64x2, z Mask64x2) Float64x2
// And performs a masked bitwise AND operation between two vectors.
//
// Asm: VANDPD, CPU Feature: AVX512EVEX
func (x Float64x4) MaskedAnd(y Float64x4, z Mask64x4) Float64x4
// And performs a masked bitwise AND operation between two vectors.
//
// Asm: VANDPD, CPU Feature: AVX512EVEX
func (x Float64x8) MaskedAnd(y Float64x8, z Mask64x8) Float64x8
// And performs a masked bitwise AND operation between two vectors.
//
// Asm: VPANDD, CPU Feature: AVX512EVEX
@ -2240,36 +2150,6 @@ func (x Uint64x8) MaskedAnd(y Uint64x8, z Mask64x8) Uint64x8
/* MaskedAndNot */
// AndNot performs a masked bitwise AND NOT operation between two vectors.
//
// Asm: VANDNPS, CPU Feature: AVX512EVEX
func (x Float32x4) MaskedAndNot(y Float32x4, z Mask32x4) Float32x4
// AndNot performs a masked bitwise AND NOT operation between two vectors.
//
// Asm: VANDNPS, CPU Feature: AVX512EVEX
func (x Float32x8) MaskedAndNot(y Float32x8, z Mask32x8) Float32x8
// AndNot performs a masked bitwise AND NOT operation between two vectors.
//
// Asm: VANDNPS, CPU Feature: AVX512EVEX
func (x Float32x16) MaskedAndNot(y Float32x16, z Mask32x16) Float32x16
// AndNot performs a masked bitwise AND NOT operation between two vectors.
//
// Asm: VANDNPD, CPU Feature: AVX512EVEX
func (x Float64x2) MaskedAndNot(y Float64x2, z Mask64x2) Float64x2
// AndNot performs a masked bitwise AND NOT operation between two vectors.
//
// Asm: VANDNPD, CPU Feature: AVX512EVEX
func (x Float64x4) MaskedAndNot(y Float64x4, z Mask64x4) Float64x4
// AndNot performs a masked bitwise AND NOT operation between two vectors.
//
// Asm: VANDNPD, CPU Feature: AVX512EVEX
func (x Float64x8) MaskedAndNot(y Float64x8, z Mask64x8) Float64x8
// AndNot performs a masked bitwise AND NOT operation between two vectors.
//
// Asm: VPANDND, CPU Feature: AVX512EVEX
@ -4252,36 +4132,6 @@ func (x Uint64x8) MaskedNotEqual(y Uint64x8, z Mask64x8) Mask64x8
/* MaskedOr */
// Or performs a masked bitwise OR operation between two vectors.
//
// Asm: VORPS, CPU Feature: AVX512EVEX
func (x Float32x4) MaskedOr(y Float32x4, z Mask32x4) Float32x4
// Or performs a masked bitwise OR operation between two vectors.
//
// Asm: VORPS, CPU Feature: AVX512EVEX
func (x Float32x8) MaskedOr(y Float32x8, z Mask32x8) Float32x8
// Or performs a masked bitwise OR operation between two vectors.
//
// Asm: VORPS, CPU Feature: AVX512EVEX
func (x Float32x16) MaskedOr(y Float32x16, z Mask32x16) Float32x16
// Or performs a masked bitwise OR operation between two vectors.
//
// Asm: VORPD, CPU Feature: AVX512EVEX
func (x Float64x2) MaskedOr(y Float64x2, z Mask64x2) Float64x2
// Or performs a masked bitwise OR operation between two vectors.
//
// Asm: VORPD, CPU Feature: AVX512EVEX
func (x Float64x4) MaskedOr(y Float64x4, z Mask64x4) Float64x4
// Or performs a masked bitwise OR operation between two vectors.
//
// Asm: VORPD, CPU Feature: AVX512EVEX
func (x Float64x8) MaskedOr(y Float64x8, z Mask64x8) Float64x8
// Or performs a masked bitwise OR operation between two vectors.
//
// Asm: VPORD, CPU Feature: AVX512EVEX
@ -6021,36 +5871,6 @@ func (x Uint32x16) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int8x
/* MaskedXor */
// Xor performs a masked bitwise XOR operation between two vectors.
//
// Asm: VXORPS, CPU Feature: AVX512EVEX
func (x Float32x4) MaskedXor(y Float32x4, z Mask32x4) Float32x4
// Xor performs a masked bitwise XOR operation between two vectors.
//
// Asm: VXORPS, CPU Feature: AVX512EVEX
func (x Float32x8) MaskedXor(y Float32x8, z Mask32x8) Float32x8
// Xor performs a masked bitwise XOR operation between two vectors.
//
// Asm: VXORPS, CPU Feature: AVX512EVEX
func (x Float32x16) MaskedXor(y Float32x16, z Mask32x16) Float32x16
// Xor performs a masked bitwise XOR operation between two vectors.
//
// Asm: VXORPD, CPU Feature: AVX512EVEX
func (x Float64x2) MaskedXor(y Float64x2, z Mask64x2) Float64x2
// Xor performs a masked bitwise XOR operation between two vectors.
//
// Asm: VXORPD, CPU Feature: AVX512EVEX
func (x Float64x4) MaskedXor(y Float64x4, z Mask64x4) Float64x4
// Xor performs a masked bitwise XOR operation between two vectors.
//
// Asm: VXORPD, CPU Feature: AVX512EVEX
func (x Float64x8) MaskedXor(y Float64x8, z Mask64x8) Float64x8
// Xor performs a masked bitwise XOR operation between two vectors.
//
// Asm: VPXORD, CPU Feature: AVX512EVEX
@ -6774,36 +6594,6 @@ func (x Uint64x8) NotEqual(y Uint64x8) Mask64x8
/* Or */
// Or performs a bitwise OR operation between two vectors.
//
// Asm: VORPS, CPU Feature: AVX
func (x Float32x4) Or(y Float32x4) Float32x4
// Or performs a bitwise OR operation between two vectors.
//
// Asm: VORPS, CPU Feature: AVX
func (x Float32x8) Or(y Float32x8) Float32x8
// Or performs a masked bitwise OR operation between two vectors.
//
// Asm: VORPS, CPU Feature: AVX512EVEX
func (x Float32x16) Or(y Float32x16) Float32x16
// Or performs a bitwise OR operation between two vectors.
//
// Asm: VORPD, CPU Feature: AVX
func (x Float64x2) Or(y Float64x2) Float64x2
// Or performs a bitwise OR operation between two vectors.
//
// Asm: VORPD, CPU Feature: AVX
func (x Float64x4) Or(y Float64x4) Float64x4
// Or performs a masked bitwise OR operation between two vectors.
//
// Asm: VORPD, CPU Feature: AVX512EVEX
func (x Float64x8) Or(y Float64x8) Float64x8
// Or performs a bitwise OR operation between two vectors.
//
// Asm: VPOR, CPU Feature: AVX
@ -9035,36 +8825,6 @@ func (x Uint32x16) UnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int8x64) Ui
/* Xor */
// Xor performs a bitwise XOR operation between two vectors.
//
// Asm: VXORPS, CPU Feature: AVX
func (x Float32x4) Xor(y Float32x4) Float32x4
// Xor performs a bitwise XOR operation between two vectors.
//
// Asm: VXORPS, CPU Feature: AVX
func (x Float32x8) Xor(y Float32x8) Float32x8
// Xor performs a masked bitwise XOR operation between two vectors.
//
// Asm: VXORPS, CPU Feature: AVX512EVEX
func (x Float32x16) Xor(y Float32x16) Float32x16
// Xor performs a bitwise XOR operation between two vectors.
//
// Asm: VXORPD, CPU Feature: AVX
func (x Float64x2) Xor(y Float64x2) Float64x2
// Xor performs a bitwise XOR operation between two vectors.
//
// Asm: VXORPD, CPU Feature: AVX
func (x Float64x4) Xor(y Float64x4) Float64x4
// Xor performs a masked bitwise XOR operation between two vectors.
//
// Asm: VXORPD, CPU Feature: AVX512EVEX
func (x Float64x8) Xor(y Float64x8) Float64x8
// Xor performs a bitwise XOR operation between two vectors.
//
// Asm: VPXOR, CPU Feature: AVX