mirror of
https://github.com/golang/go.git
synced 2026-06-27 19:30:52 +00:00
cmd/asm, cmd/internal/obj: add zvbb/zvbc for riscv64
Add support for instructions from the Vector Basic Bit-manipulation (Zvbb) and Vector Carryless Multiplication (Zvbc) RISC-V extensions. Updates #77328 Change-Id: I483efdda7cf2740e808682eb039b133a822ebaf5 Reviewed-on: https://go-review.googlesource.com/c/go/+/663778 Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
This commit is contained in:
Meng Zhuo
parent
aa3c8ed492
commit
58efaf3859
7 changed files with 188 additions and 6 deletions
44
src/cmd/asm/internal/asm/testdata/riscv64.s
vendored
44
src/cmd/asm/internal/asm/testdata/riscv64.s
vendored
|
|
@ -1996,6 +1996,50 @@ start:
|
|||
VMV4RV V8, V4 // 57b2819e
|
||||
VMV8RV V8, V0 // 57b0839e
|
||||
|
||||
// 32.2.1: Vector Basic Bit-manipulation
|
||||
VANDNVV V1, V2, V3 // d7812006
|
||||
VANDNVV V1, V2, V0, V3 // d7812004
|
||||
VANDNVX X10, V2, V3 // d7412506
|
||||
VANDNVX X10, V2, V0, V3 // d7412504
|
||||
VBREVV V2, V3 // d721254a
|
||||
VBREVV V2, V0, V3 // d7212548
|
||||
VBREV8V V2, V3 // d721244a
|
||||
VBREV8V V2, V0, V3 // d7212448
|
||||
VREV8V V2, V3 // d7a1244a
|
||||
VREV8V V2, V0, V3 // d7a12448
|
||||
VCLZV V2, V3 // d721264a
|
||||
VCLZV V2, V0, V3 // d7212648
|
||||
VCTZV V2, V3 // d7a1264a
|
||||
VCTZV V2, V0, V3 // d7a12648
|
||||
VCPOPV V2, V3 // d721274a
|
||||
VCPOPV V2, V0, V3 // d7212748
|
||||
VROLVV V1, V2, V3 // d7812056
|
||||
VROLVV V1, V2, V0, V3 // d7812054
|
||||
VROLVX X10, V2, V3 // d7412556
|
||||
VROLVX X10, V2, V0, V3 // d7412554
|
||||
VRORVV V1, V2, V3 // d7812052
|
||||
VRORVV V1, V2, V0, V3 // d7812050
|
||||
VRORVX X10, V2, V3 // d7412552
|
||||
VRORVX X10, V2, V0, V3 // d7412550
|
||||
VRORVI $16, V2, V3 // d7312852
|
||||
VRORVI $16, V2, V0, V3 // d7312850
|
||||
VWSLLVV V1, V2, V3 // d78120d6
|
||||
VWSLLVV V1, V2, V0, V3 // d78120d4
|
||||
VWSLLVX X10, V2, V3 // d74125d6
|
||||
VWSLLVX X10, V2, V0, V3 // d74125d4
|
||||
VWSLLVI $16, V2, V3 // d73128d6
|
||||
VWSLLVI $16, V2, V0, V3 // d73128d4
|
||||
|
||||
// 32.2.2: Vector Carryless Multiplication
|
||||
VCLMULVV V1, V2, V3 // d7a12032
|
||||
VCLMULVV V1, V2, V0, V3 // d7a12030
|
||||
VCLMULVX X10, V2, V3 // d7612532
|
||||
VCLMULVX X10, V2, V0, V3 // d7612530
|
||||
VCLMULHVV V1, V2, V3 // d7a12036
|
||||
VCLMULHVV V1, V2, V0, V3 // d7a12034
|
||||
VCLMULHVX X10, V2, V3 // d7612536
|
||||
VCLMULHVX X10, V2, V0, V3 // d7612534
|
||||
|
||||
//
|
||||
// Privileged ISA
|
||||
//
|
||||
|
|
|
|||
20
src/cmd/asm/internal/asm/testdata/riscv64error.s
vendored
20
src/cmd/asm/internal/asm/testdata/riscv64error.s
vendored
|
|
@ -436,5 +436,25 @@ TEXT errors(SB),$0
|
|||
VRGATHEREI16VV V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VRGATHERVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VRGATHERVI $16, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VANDNVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VANDNVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VBREVV V2, V3, V4 // ERROR "invalid vector mask register"
|
||||
VBREV8V V2, V3, V4 // ERROR "invalid vector mask register"
|
||||
VREV8V V2, V3, V4 // ERROR "invalid vector mask register"
|
||||
VCLZV V2, V3, V4 // ERROR "invalid vector mask register"
|
||||
VCTZV V2, V3, V4 // ERROR "invalid vector mask register"
|
||||
VCPOPV V2, V3, V4 // ERROR "invalid vector mask register"
|
||||
VROLVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VROLVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VRORVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VRORVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VRORVI $16, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VWSLLVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VWSLLVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VWSLLVI $16, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VCLMULVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VCLMULVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VCLMULHVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
VCLMULHVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
|
||||
|
||||
RET
|
||||
|
|
|
|||
|
|
@ -597,5 +597,9 @@ TEXT validation(SB),$0
|
|||
VMV2RV X10, V10 // ERROR "expected vector register in vs2 position"
|
||||
VMV4RV X10, V4 // ERROR "expected vector register in vs2 position"
|
||||
VMV8RV X10, V0 // ERROR "expected vector register in vs2 position"
|
||||
VRORVI $32, V2, V4 // ERROR "unsigned immediate 32 must be in range [0, 31]"
|
||||
VRORVI $-1, V2, V4 // ERROR "unsigned immediate -1 must be in range [0, 31]"
|
||||
VWSLLVI $32, V2, V4 // ERROR "unsigned immediate 32 must be in range [0, 31]"
|
||||
VWSLLVI $-1, V2, V4 // ERROR "unsigned immediate -1 must be in range [0, 31]"
|
||||
|
||||
RET
|
||||
|
|
|
|||
|
|
@ -901,6 +901,26 @@ var Anames = []string{
|
|||
"VMV2RV",
|
||||
"VMV4RV",
|
||||
"VMV8RV",
|
||||
"VANDNVV",
|
||||
"VANDNVX",
|
||||
"VBREVV",
|
||||
"VBREV8V",
|
||||
"VREV8V",
|
||||
"VCLZV",
|
||||
"VCTZV",
|
||||
"VCPOPV",
|
||||
"VROLVV",
|
||||
"VROLVX",
|
||||
"VRORVV",
|
||||
"VRORVX",
|
||||
"VRORVI",
|
||||
"VWSLLVV",
|
||||
"VWSLLVX",
|
||||
"VWSLLVI",
|
||||
"VCLMULVV",
|
||||
"VCLMULVX",
|
||||
"VCLMULHVV",
|
||||
"VCLMULHVX",
|
||||
"ECALL",
|
||||
"SCALL",
|
||||
"EBREAK",
|
||||
|
|
|
|||
|
|
@ -1454,6 +1454,30 @@ const (
|
|||
AVMV4RV
|
||||
AVMV8RV
|
||||
|
||||
// 32.2.1: Vector Basic Bit-manipulation (Zvbb)
|
||||
AVANDNVV
|
||||
AVANDNVX
|
||||
AVBREVV
|
||||
AVBREV8V
|
||||
AVREV8V
|
||||
AVCLZV
|
||||
AVCTZV
|
||||
AVCPOPV
|
||||
AVROLVV
|
||||
AVROLVX
|
||||
AVRORVV
|
||||
AVRORVX
|
||||
AVRORVI
|
||||
AVWSLLVV
|
||||
AVWSLLVX
|
||||
AVWSLLVI
|
||||
|
||||
// 32.2.2: Vector Carryless Multiplication (Zvbc)
|
||||
AVCLMULVV
|
||||
AVCLMULVX
|
||||
AVCLMULHVV
|
||||
AVCLMULHVX
|
||||
|
||||
//
|
||||
// Privileged ISA (version 20240411)
|
||||
//
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
// Code generated by make inst.go EXTENSIONS="rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbc rv_zbs rv_zicond rv_zicsr"; DO NOT EDIT.
|
||||
// Code generated by make inst.go EXTENSIONS="rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbc rv_zbs rv_zicond rv_zicsr rv_zvbb rv_zvbc"; DO NOT EDIT.
|
||||
package riscv
|
||||
|
||||
import "cmd/internal/obj"
|
||||
|
|
@ -576,6 +576,10 @@ func encode(a obj.As) *inst {
|
|||
return &inst{0x57, 0x0, 0x0, 0x0, 576, 0x12}
|
||||
case AVANDVX:
|
||||
return &inst{0x57, 0x4, 0x0, 0x0, 576, 0x12}
|
||||
case AVANDNVV:
|
||||
return &inst{0x57, 0x0, 0x0, 0x0, 64, 0x2}
|
||||
case AVANDNVX:
|
||||
return &inst{0x57, 0x4, 0x0, 0x0, 64, 0x2}
|
||||
case AVASUBVV:
|
||||
return &inst{0x57, 0x2, 0x0, 0x0, 704, 0x16}
|
||||
case AVASUBVX:
|
||||
|
|
@ -584,10 +588,28 @@ func encode(a obj.As) *inst {
|
|||
return &inst{0x57, 0x2, 0x0, 0x0, 640, 0x14}
|
||||
case AVASUBUVX:
|
||||
return &inst{0x57, 0x6, 0x0, 0x0, 640, 0x14}
|
||||
case AVBREV8V:
|
||||
return &inst{0x57, 0x2, 0x8, 0x0, 1152, 0x24}
|
||||
case AVBREVV:
|
||||
return &inst{0x57, 0x2, 0xa, 0x0, 1152, 0x24}
|
||||
case AVCLMULVV:
|
||||
return &inst{0x57, 0x2, 0x0, 0x0, 768, 0x18}
|
||||
case AVCLMULVX:
|
||||
return &inst{0x57, 0x6, 0x0, 0x0, 768, 0x18}
|
||||
case AVCLMULHVV:
|
||||
return &inst{0x57, 0x2, 0x0, 0x0, 832, 0x1a}
|
||||
case AVCLMULHVX:
|
||||
return &inst{0x57, 0x6, 0x0, 0x0, 832, 0x1a}
|
||||
case AVCLZV:
|
||||
return &inst{0x57, 0x2, 0xc, 0x0, 1152, 0x24}
|
||||
case AVCOMPRESSVM:
|
||||
return &inst{0x57, 0x2, 0x0, 0x0, 1504, 0x2f}
|
||||
case AVCPOPM:
|
||||
return &inst{0x57, 0x2, 0x10, 0x0, 1024, 0x20}
|
||||
case AVCPOPV:
|
||||
return &inst{0x57, 0x2, 0xe, 0x0, 1152, 0x24}
|
||||
case AVCTZV:
|
||||
return &inst{0x57, 0x2, 0xd, 0x0, 1152, 0x24}
|
||||
case AVDIVVV:
|
||||
return &inst{0x57, 0x2, 0x0, 0x0, -1984, 0x42}
|
||||
case AVDIVVX:
|
||||
|
|
@ -1366,6 +1388,8 @@ func encode(a obj.As) *inst {
|
|||
return &inst{0x57, 0x2, 0x0, 0x0, -1920, 0x44}
|
||||
case AVREMUVX:
|
||||
return &inst{0x57, 0x6, 0x0, 0x0, -1920, 0x44}
|
||||
case AVREV8V:
|
||||
return &inst{0x57, 0x2, 0x9, 0x0, 1152, 0x24}
|
||||
case AVRGATHERVI:
|
||||
return &inst{0x57, 0x3, 0x0, 0x0, 768, 0x18}
|
||||
case AVRGATHERVV:
|
||||
|
|
@ -1374,6 +1398,16 @@ func encode(a obj.As) *inst {
|
|||
return &inst{0x57, 0x4, 0x0, 0x0, 768, 0x18}
|
||||
case AVRGATHEREI16VV:
|
||||
return &inst{0x57, 0x0, 0x0, 0x0, 896, 0x1c}
|
||||
case AVROLVV:
|
||||
return &inst{0x57, 0x0, 0x0, 0x0, 1344, 0x2a}
|
||||
case AVROLVX:
|
||||
return &inst{0x57, 0x4, 0x0, 0x0, 1344, 0x2a}
|
||||
case AVRORVI:
|
||||
return &inst{0x57, 0x3, 0x0, 0x0, 1280, 0x28}
|
||||
case AVRORVV:
|
||||
return &inst{0x57, 0x0, 0x0, 0x0, 1280, 0x28}
|
||||
case AVRORVX:
|
||||
return &inst{0x57, 0x4, 0x0, 0x0, 1280, 0x28}
|
||||
case AVRSUBVI:
|
||||
return &inst{0x57, 0x3, 0x0, 0x0, 192, 0x6}
|
||||
case AVRSUBVX:
|
||||
|
|
@ -1776,6 +1810,12 @@ func encode(a obj.As) *inst {
|
|||
return &inst{0x57, 0x0, 0x0, 0x0, -960, 0x62}
|
||||
case AVWREDSUMUVS:
|
||||
return &inst{0x57, 0x0, 0x0, 0x0, -1024, 0x60}
|
||||
case AVWSLLVI:
|
||||
return &inst{0x57, 0x3, 0x0, 0x0, -704, 0x6a}
|
||||
case AVWSLLVV:
|
||||
return &inst{0x57, 0x0, 0x0, 0x0, -704, 0x6a}
|
||||
case AVWSLLVX:
|
||||
return &inst{0x57, 0x4, 0x0, 0x0, -704, 0x6a}
|
||||
case AVWSUBVV:
|
||||
return &inst{0x57, 0x2, 0x0, 0x0, -832, 0x66}
|
||||
case AVWSUBVX:
|
||||
|
|
|
|||
|
|
@ -3410,6 +3410,30 @@ var instructions = [ALAST & obj.AMask]instructionData{
|
|||
AVMV4RV & obj.AMask: {enc: rVVEncoding},
|
||||
AVMV8RV & obj.AMask: {enc: rVVEncoding},
|
||||
|
||||
// 32.2.1: Vector Basic Bit-manipulation
|
||||
AVANDNVV & obj.AMask: {enc: rVVVEncoding},
|
||||
AVANDNVX & obj.AMask: {enc: rVIVEncoding},
|
||||
AVBREVV & obj.AMask: {enc: rVVEncoding},
|
||||
AVBREV8V & obj.AMask: {enc: rVVEncoding},
|
||||
AVREV8V & obj.AMask: {enc: rVVEncoding},
|
||||
AVCLZV & obj.AMask: {enc: rVVEncoding},
|
||||
AVCTZV & obj.AMask: {enc: rVVEncoding},
|
||||
AVCPOPV & obj.AMask: {enc: rVVEncoding},
|
||||
AVROLVV & obj.AMask: {enc: rVVVEncoding},
|
||||
AVROLVX & obj.AMask: {enc: rVIVEncoding},
|
||||
AVRORVV & obj.AMask: {enc: rVVVEncoding},
|
||||
AVRORVX & obj.AMask: {enc: rVIVEncoding},
|
||||
AVRORVI & obj.AMask: {enc: rVVuEncoding},
|
||||
AVWSLLVV & obj.AMask: {enc: rVVVEncoding},
|
||||
AVWSLLVX & obj.AMask: {enc: rVIVEncoding},
|
||||
AVWSLLVI & obj.AMask: {enc: rVVuEncoding},
|
||||
|
||||
// 32.2.2: Vector Carryless Multiplication
|
||||
AVCLMULVV & obj.AMask: {enc: rVVVEncoding},
|
||||
AVCLMULVX & obj.AMask: {enc: rVIVEncoding},
|
||||
AVCLMULHVV & obj.AMask: {enc: rVVVEncoding},
|
||||
AVCLMULHVX & obj.AMask: {enc: rVIVEncoding},
|
||||
|
||||
//
|
||||
// Privileged ISA
|
||||
//
|
||||
|
|
@ -4756,7 +4780,9 @@ func instructionsForProg(p *obj.Prog, compress bool) []*instruction {
|
|||
AVREDSUMVS, AVREDMAXUVS, AVREDMAXVS, AVREDMINUVS, AVREDMINVS, AVREDANDVS, AVREDORVS, AVREDXORVS,
|
||||
AVWREDSUMUVS, AVWREDSUMVS, AVFREDOSUMVS, AVFREDUSUMVS, AVFREDMAXVS, AVFREDMINVS, AVFWREDOSUMVS, AVFWREDUSUMVS,
|
||||
AVSLIDEUPVX, AVSLIDEDOWNVX, AVSLIDE1UPVX, AVFSLIDE1UPVF, AVSLIDE1DOWNVX, AVFSLIDE1DOWNVF,
|
||||
AVRGATHERVV, AVRGATHEREI16VV, AVRGATHERVX:
|
||||
AVRGATHERVV, AVRGATHEREI16VV, AVRGATHERVX,
|
||||
AVANDNVV, AVANDNVX, AVROLVV, AVROLVX, AVRORVV, AVRORVX,
|
||||
AVWSLLVV, AVWSLLVX, AVCLMULVV, AVCLMULVX, AVCLMULHVV, AVCLMULHVX:
|
||||
// Set mask bit
|
||||
switch {
|
||||
case ins.rs3 == obj.REG_NONE:
|
||||
|
|
@ -4780,7 +4806,8 @@ func instructionsForProg(p *obj.Prog, compress bool) []*instruction {
|
|||
ins.rd, ins.rs1, ins.rs2, ins.rs3 = uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), obj.REG_NONE
|
||||
|
||||
case AVADDVI, AVRSUBVI, AVANDVI, AVORVI, AVXORVI, AVMSEQVI, AVMSNEVI, AVMSLEUVI, AVMSLEVI, AVMSGTUVI, AVMSGTVI,
|
||||
AVSLLVI, AVSRLVI, AVSRAVI, AVNSRLWI, AVNSRAWI, AVRGATHERVI, AVSLIDEUPVI, AVSLIDEDOWNVI:
|
||||
AVSLLVI, AVSRLVI, AVSRAVI, AVNSRLWI, AVNSRAWI, AVRGATHERVI, AVSLIDEUPVI, AVSLIDEDOWNVI,
|
||||
AVRORVI, AVWSLLVI:
|
||||
// Set mask bit
|
||||
switch {
|
||||
case ins.rs3 == obj.REG_NONE:
|
||||
|
|
@ -4790,10 +4817,13 @@ func instructionsForProg(p *obj.Prog, compress bool) []*instruction {
|
|||
}
|
||||
ins.rd, ins.rs1, ins.rs2, ins.rs3 = uint32(p.To.Reg), obj.REG_NONE, uint32(p.Reg), obj.REG_NONE
|
||||
|
||||
case AVZEXTVF2, AVSEXTVF2, AVZEXTVF4, AVSEXTVF4, AVZEXTVF8, AVSEXTVF8, AVFSQRTV, AVFRSQRT7V, AVFREC7V, AVFCLASSV,
|
||||
case AVZEXTVF2, AVSEXTVF2, AVZEXTVF4, AVSEXTVF4, AVZEXTVF8, AVSEXTVF8,
|
||||
AVFSQRTV, AVFRSQRT7V, AVFREC7V, AVFCLASSV,
|
||||
AVFCVTXUFV, AVFCVTXFV, AVFCVTRTZXUFV, AVFCVTRTZXFV, AVFCVTFXUV, AVFCVTFXV,
|
||||
AVFWCVTXUFV, AVFWCVTXFV, AVFWCVTRTZXUFV, AVFWCVTRTZXFV, AVFWCVTFXUV, AVFWCVTFXV, AVFWCVTFFV,
|
||||
AVFNCVTXUFW, AVFNCVTXFW, AVFNCVTRTZXUFW, AVFNCVTRTZXFW, AVFNCVTFXUW, AVFNCVTFXW, AVFNCVTFFW, AVFNCVTRODFFW:
|
||||
AVFWCVTXUFV, AVFWCVTXFV, AVFWCVTRTZXUFV, AVFWCVTRTZXFV, AVFWCVTFXUV, AVFWCVTFXV,
|
||||
AVFWCVTFFV, AVFNCVTXUFW, AVFNCVTXFW, AVFNCVTRTZXUFW, AVFNCVTRTZXFW, AVFNCVTFXUW,
|
||||
AVFNCVTFXW, AVFNCVTFFW, AVFNCVTRODFFW,
|
||||
AVBREVV, AVBREV8V, AVREV8V, AVCLZV, AVCTZV, AVCPOPV:
|
||||
// Set mask bit
|
||||
switch {
|
||||
case ins.rs1 == obj.REG_NONE:
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue