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cmd/internal/obj/loong64: add support of VMOVQ and XVMOVQ

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This CL refers to the implementation of ARM64 and adds support for the following
types of SIMD instructions:
1. Move general-purpose register to a vector element, e.g.:
      VMOVQ  Rj, <Vd>.<T>[index]
      <T> can have the following values:
       B, H, W, V
2. Move vector element to general-purpose register, e.g.:
      VMOVQ     <Vj>.<T>[index], Rd
      <T> can have the following values:
       B, BU, H, HU, W, WU, VU
3. Duplicate general-purpose register to vector, e.g.:
      VMOVQ    Rj, <Vd>.<T>
      <T> can have the following values:
       B16, H8, W4, V2, B32, H16, W8, V4
4. Move vector, e.g.:
      XVMOVQ    Xj, <Xd>.<T>
      <T> can have the following values:
       B16, H8, W4, V2, Q1
5. Move vector element to scalar, e.g.:
      XVMOVQ  Xj, <Xd>.<T>[index]
      XVMOVQ  Xj.<T>[index], Xd
      <T> can have the following values:
       W, V
6. Move vector element to vector register, e.g.:
       VMOVQ     <Vn>.<T>[index], Vn.<T>
      <T> can have the following values:
       B, H, W, V

This CL only adds syntax and doesn't break any assembly that already exists.

Change-Id: I7656efac6def54da6c5ae182f39c2a21bfdf92bb
Reviewed-on: https://go-review.googlesource.com/c/go/+/616258
Reviewed-by: David Chase <drchase@google.com>
Reviewed-by: Meidan Li <limeidan@loongson.cn>
Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
Reviewed-by: Cherry Mui <cherryyz@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
This commit is contained in:
Guoqi Chen 2024-11-04 18:14:00 +08:00 • committed by abner chenc
parent 0ff1d42507
commit 65ba6f94b3
10 changed files with 666 additions and 44 deletions
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8
src/cmd/internal/obj/link.go
View file

@ -180,14 +180,16 @@ import (
// offset = ((reg&31) << 16) | (exttype << 13) | (amount<<10)
//
// reg.<T>
// Register arrangement for ARM64 SIMD register
// e.g.: V1.S4, V2.S2, V7.D2, V2.H4, V6.B16
// Register arrangement for ARM64 and Loong64 SIMD register
// e.g.:
// On ARM64: V1.S4, V2.S2, V7.D2, V2.H4, V6.B16
// On Loong64: X1.B32, X1.H16, X1.W8, X2.V4, X1.Q1, V1.B16, V1.H8, V1.W4, V1.V2
// Encoding:
// type = TYPE_REG
// reg = REG_ARNG + register + arrangement
//
// reg.<T>[index]
// Register element for ARM64
// Register element for ARM64 and Loong64
// Encoding:
// type = TYPE_REG
// reg = REG_ELEM + register + arrangement