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cmd/compile: modify regalloc/stackalloc to use the cmd line debug args
Change the existing flags from compile time consts to be configurable from the command line. Change-Id: I4aab4bf3dfcbdd8e2b5a2ff51af95c2543967769 Reviewed-on: https://go-review.googlesource.com/20560 Reviewed-by: Keith Randall <khr@golang.org> Run-TryBot: Todd Neal <todd@tneal.org> TryBot-Result: Gobot Gobot <gobot@golang.org>
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31d13f479a
commit
6b3d4a5353
3 changed files with 33 additions and 31 deletions
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@ -99,8 +99,11 @@ import (
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"unsafe"
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)
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const regDebug = false // TODO: compiler flag
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const logSpills = false
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const (
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logSpills = iota
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regDebug
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stackDebug
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)
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// distance is a measure of how far into the future values are used.
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// distance is measured in units of instructions.
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@ -292,7 +295,7 @@ func (s *regAllocState) freeReg(r register) {
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}
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// Mark r as unused.
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if regDebug {
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if s.f.pass.debug > regDebug {
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fmt.Printf("freeReg %s (dump %s/%s)\n", registers[r].Name(), v, s.regs[r].c)
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}
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s.regs[r] = regState{}
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@ -322,7 +325,7 @@ func (s *regAllocState) setOrig(c *Value, v *Value) {
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// assignReg assigns register r to hold c, a copy of v.
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// r must be unused.
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func (s *regAllocState) assignReg(r register, v *Value, c *Value) {
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if regDebug {
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if s.f.pass.debug > regDebug {
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fmt.Printf("assignReg %s %s/%s\n", registers[r].Name(), v, c)
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}
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if s.regs[r].v != nil {
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@ -446,7 +449,7 @@ func (s *regAllocState) allocValToReg(v *Value, mask regMask, nospill bool, line
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switch {
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// Load v from its spill location.
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case vi.spill != nil:
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if logSpills {
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if s.f.pass.debug > logSpills {
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fmt.Println("regalloc: load spill")
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}
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c = s.curBlock.NewValue1(line, OpLoadReg, v.Type, vi.spill)
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@ -613,7 +616,7 @@ func (s *regAllocState) regalloc(f *Func) {
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liveSet.add(a.ID)
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}
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}
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if regDebug {
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if s.f.pass.debug > regDebug {
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fmt.Printf("uses for %s:%s\n", s.f.Name, b)
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for i := range s.values {
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vi := &s.values[i]
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@ -679,7 +682,7 @@ func (s *regAllocState) regalloc(f *Func) {
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p := b.Preds[idx]
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s.setState(s.endRegs[p.ID])
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if regDebug {
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if s.f.pass.debug > regDebug {
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fmt.Printf("starting merge block %s with end state of %s:\n", b, p)
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for _, x := range s.endRegs[p.ID] {
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fmt.Printf(" %s: orig:%s cache:%s\n", registers[x.r].Name(), x.v, x.c)
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@ -778,7 +781,7 @@ func (s *regAllocState) regalloc(f *Func) {
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}
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s.startRegs[b.ID] = regList
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if regDebug {
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if s.f.pass.debug > regDebug {
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fmt.Printf("after phis\n")
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for _, x := range s.startRegs[b.ID] {
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fmt.Printf(" %s: v%d\n", registers[x.r].Name(), x.vid)
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@ -854,7 +857,7 @@ func (s *regAllocState) regalloc(f *Func) {
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// Process all the non-phi values.
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for _, v := range oldSched {
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if regDebug {
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if s.f.pass.debug > regDebug {
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fmt.Printf(" processing %s\n", v.LongString())
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}
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if v.Op == OpPhi {
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@ -958,7 +961,7 @@ func (s *regAllocState) regalloc(f *Func) {
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// Load control value into reg.
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if v := b.Control; v != nil && s.values[v.ID].needReg {
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if regDebug {
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if s.f.pass.debug > regDebug {
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fmt.Printf(" processing control %s\n", v.LongString())
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}
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// TODO: regspec for block control values, instead of using
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@ -1098,7 +1101,7 @@ func (s *regAllocState) regalloc(f *Func) {
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for i := range s.values {
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vi := s.values[i]
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if vi.spillUsed {
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if logSpills {
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if s.f.pass.debug > logSpills {
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fmt.Println("regalloc: spilled value")
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}
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continue
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@ -1138,7 +1141,7 @@ func (s *regAllocState) shuffle(stacklive [][]ID) {
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e.s = s
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e.cache = map[ID][]*Value{}
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e.contents = map[Location]contentRecord{}
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if regDebug {
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if s.f.pass.debug > regDebug {
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fmt.Printf("shuffle %s\n", s.f.Name)
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fmt.Println(s.f.String())
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}
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@ -1190,7 +1193,7 @@ type dstRecord struct {
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// setup initializes the edge state for shuffling.
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func (e *edgeState) setup(idx int, srcReg []endReg, dstReg []startReg, stacklive []ID) {
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if regDebug {
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if e.s.f.pass.debug > regDebug {
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fmt.Printf("edge %s->%s\n", e.p, e.b)
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}
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@ -1235,7 +1238,7 @@ func (e *edgeState) setup(idx int, srcReg []endReg, dstReg []startReg, stacklive
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}
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e.destinations = dsts
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if regDebug {
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if e.s.f.pass.debug > regDebug {
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for _, vid := range e.cachedVals {
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a := e.cache[vid]
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for _, c := range a {
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@ -1298,7 +1301,7 @@ func (e *edgeState) process() {
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vid := e.contents[loc].vid
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c := e.contents[loc].c
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r := e.findRegFor(c.Type)
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if regDebug {
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if e.s.f.pass.debug > regDebug {
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fmt.Printf("breaking cycle with v%d in %s:%s\n", vid, loc.Name(), c)
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}
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if _, isReg := loc.(*Register); isReg {
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@ -1337,13 +1340,13 @@ func (e *edgeState) processDest(loc Location, vid ID, splice **Value) bool {
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v := e.s.orig[vid]
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var c *Value
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var src Location
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if regDebug {
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if e.s.f.pass.debug > regDebug {
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fmt.Printf("moving v%d to %s\n", vid, loc.Name())
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fmt.Printf("sources of v%d:", vid)
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}
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for _, w := range e.cache[vid] {
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h := e.s.f.getHome(w.ID)
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if regDebug {
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if e.s.f.pass.debug > regDebug {
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fmt.Printf(" %s:%s", h.Name(), w)
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}
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_, isreg := h.(*Register)
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@ -1352,7 +1355,7 @@ func (e *edgeState) processDest(loc Location, vid ID, splice **Value) bool {
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src = h
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}
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}
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if regDebug {
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if e.s.f.pass.debug > regDebug {
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if src != nil {
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fmt.Printf(" [use %s]\n", src.Name())
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} else {
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@ -1445,7 +1448,7 @@ func (e *edgeState) set(loc Location, vid ID, c *Value, final bool) {
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}
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}
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}
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if regDebug {
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if e.s.f.pass.debug > regDebug {
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fmt.Printf("%s\n", c.LongString())
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fmt.Printf("v%d now available in %s:%s\n", vid, loc.Name(), c)
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}
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@ -1470,7 +1473,7 @@ func (e *edgeState) erase(loc Location) {
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a := e.cache[vid]
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for i, c := range a {
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if e.s.f.getHome(c.ID) == loc {
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if regDebug {
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if e.s.f.pass.debug > regDebug {
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fmt.Printf("v%d no longer available in %s:%s\n", vid, loc.Name(), c)
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}
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a[i], a = a[len(a)-1], a[:len(a)-1]
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@ -1534,7 +1537,7 @@ func (e *edgeState) findRegFor(typ Type) Location {
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if r, ok := e.s.f.getHome(c.ID).(*Register); ok && m>>uint(r.Num)&1 != 0 {
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x := e.p.NewValue1(c.Line, OpStoreReg, c.Type, c)
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e.set(t, vid, x, false)
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if regDebug {
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if e.s.f.pass.debug > regDebug {
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fmt.Printf(" SPILL %s->%s %s\n", r.Name(), t.Name(), x.LongString())
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}
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// r will now be overwritten by the caller. At some point
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@ -1703,7 +1706,7 @@ func (s *regAllocState) computeLive() {
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break
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}
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}
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if regDebug {
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if f.pass.debug > regDebug {
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fmt.Println("live values at end of each block")
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for _, b := range f.Blocks {
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fmt.Printf(" %s:", b)
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