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cmd/compile,cmd/internal/obj/riscv: move g register on riscv64

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The original riscv64 port used the thread pointer (TP aka X4) register for
the g pointer, however this register is also used when TLS support is
required, resulting in a conflict (for example, when a signal is received
we have no way of readily knowing if X4 contains a pointer to the TCB or
a pointer to a g).

In order to support cgo, free up the X4 register by moving g to X27.
This unfortunately means that the X4 register is unused in non-cgo mode,
however the alternative is to not support cgo on this platform.

Update #36641

Change-Id: Idcaf3e8ccbe42972a1b8943aeefde7149d9c960a
Reviewed-on: https://go-review.googlesource.com/c/go/+/263477
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
This commit is contained in:
Joel Sing 2020-05-19 18:55:31 +10:00
parent 214136b741
commit 6f45b39e4d
4 changed files with 219 additions and 218 deletions
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7
src/cmd/compile/internal/ssa/gen/RISCV64Ops.go
View file

@ -24,10 +24,11 @@ import (
// L = 64 bit int, used when the opcode starts with F
const (
riscv64REG_G = 4
riscv64REG_G = 27
riscv64REG_CTXT = 20
riscv64REG_LR = 1
riscv64REG_SP = 2
riscv64REG_TP = 4
riscv64REG_TMP = 31
riscv64REG_ZERO = 0
)
@ -78,8 +79,8 @@ func init() {
// Add general purpose registers to gpMask.
switch r {
// ZERO, and TMP are not in any gp mask.
case riscv64REG_ZERO, riscv64REG_TMP:
// ZERO, TP and TMP are not in any gp mask.
case riscv64REG_ZERO, riscv64REG_TP, riscv64REG_TMP:
case riscv64REG_G:
gpgMask |= mask
gpspsbgMask |= mask