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cmd/compile,cmd/internal/obj/riscv: move g register on riscv64

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The original riscv64 port used the thread pointer (TP aka X4) register for
the g pointer, however this register is also used when TLS support is
required, resulting in a conflict (for example, when a signal is received
we have no way of readily knowing if X4 contains a pointer to the TCB or
a pointer to a g).

In order to support cgo, free up the X4 register by moving g to X27.
This unfortunately means that the X4 register is unused in non-cgo mode,
however the alternative is to not support cgo on this platform.

Update #36641

Change-Id: Idcaf3e8ccbe42972a1b8943aeefde7149d9c960a
Reviewed-on: https://go-review.googlesource.com/c/go/+/263477
Trust: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
This commit is contained in:
Joel Sing 2020-05-19 18:55:31 +10:00
parent 214136b741
commit 6f45b39e4d
4 changed files with 219 additions and 218 deletions
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7
src/cmd/compile/internal/ssa/gen/RISCV64Ops.go
View file

@ -24,10 +24,11 @@ import (
// L = 64 bit int, used when the opcode starts with F // L = 64 bit int, used when the opcode starts with F
const ( const (
riscv64REG_G = 4 riscv64REG_G = 27
riscv64REG_CTXT = 20 riscv64REG_CTXT = 20
riscv64REG_LR = 1 riscv64REG_LR = 1
riscv64REG_SP = 2 riscv64REG_SP = 2
riscv64REG_TP = 4
riscv64REG_TMP = 31 riscv64REG_TMP = 31
riscv64REG_ZERO = 0 riscv64REG_ZERO = 0
) )
@ -78,8 +79,8 @@ func init() {
// Add general purpose registers to gpMask. // Add general purpose registers to gpMask.
switch r { switch r {
// ZERO, and TMP are not in any gp mask. // ZERO, TP and TMP are not in any gp mask.
case riscv64REG_ZERO, riscv64REG_TMP: case riscv64REG_ZERO, riscv64REG_TP, riscv64REG_TMP:
case riscv64REG_G: case riscv64REG_G:
gpgMask |= mask gpgMask |= mask
gpspsbgMask |= mask gpspsbgMask |= mask

406
src/cmd/compile/internal/ssa/opGen.go
View file

File diff suppressed because it is too large Load diff

6
src/cmd/internal/obj/riscv/cpu.go
View file

@ -109,7 +109,7 @@ const (
REG_RA = REG_X1 // aka REG_LR REG_RA = REG_X1 // aka REG_LR
REG_SP = REG_X2 REG_SP = REG_X2
REG_GP = REG_X3 // aka REG_SB REG_GP = REG_X3 // aka REG_SB
REG_TP = REG_X4 // aka REG_G REG_TP = REG_X4
REG_T0 = REG_X5 REG_T0 = REG_X5
REG_T1 = REG_X6 REG_T1 = REG_X6
REG_T2 = REG_X7 REG_T2 = REG_X7
@ -132,14 +132,14 @@ const (
REG_S8 = REG_X24 REG_S8 = REG_X24
REG_S9 = REG_X25 REG_S9 = REG_X25
REG_S10 = REG_X26 REG_S10 = REG_X26
REG_S11 = REG_X27 REG_S11 = REG_X27 // aka REG_G
REG_T3 = REG_X28 REG_T3 = REG_X28
REG_T4 = REG_X29 REG_T4 = REG_X29
REG_T5 = REG_X30 REG_T5 = REG_X30
REG_T6 = REG_X31 // aka REG_TMP REG_T6 = REG_X31 // aka REG_TMP
// Go runtime register names. // Go runtime register names.
REG_G = REG_TP // G pointer. REG_G = REG_S11 // G pointer.
REG_CTXT = REG_S4 // Context for closures. REG_CTXT = REG_S4 // Context for closures.
REG_LR = REG_RA // Link register. REG_LR = REG_RA // Link register.
REG_TMP = REG_T6 // Reserved for assembler use. REG_TMP = REG_T6 // Reserved for assembler use.

12
src/runtime/asm_riscv64.s
View file

@ -519,12 +519,12 @@ flush:
MOV T1, 16(X2) // Also second argument to wbBufFlush MOV T1, 16(X2) // Also second argument to wbBufFlush
// TODO: Optimise // TODO: Optimise
// R3 is g. // X5 already saved (T0)
// R4 already saved (T0) // X6 already saved (T1)
// R5 already saved (T1) // X10 already saved (A0)
// R9 already saved (A0) // X11 already saved (A1)
// R10 already saved (A1) // X27 is g.
// R30 is tmp register. // X31 is tmp register.
MOV X0, 24(X2) MOV X0, 24(X2)
MOV X1, 32(X2) MOV X1, 32(X2)
MOV X2, 40(X2) MOV X2, 40(X2)