mirror of
https://github.com/golang/go.git
synced 2025-12-08 06:10:04 +00:00
[dev.simd] simd, cmd/compile: add float -> int conversions
This CL also fixed some documentation errors in existing APIs. Go defaults MXCSR to mask exceptions, the documentation is based on this fact. Change-Id: I745083b82b4bef93126a4b4e41f8698956963704 Reviewed-on: https://go-review.googlesource.com/c/go/+/724320 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Junyang Shao
parent
1265ebfe27
commit
86cd9b5c90
13 changed files with 3519 additions and 323 deletions
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@ -45,9 +45,25 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VCVTTPS2DQ128,
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ssa.OpAMD64VCVTTPS2DQ256,
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ssa.OpAMD64VCVTTPS2DQ512,
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ssa.OpAMD64VCVTPS2UDQ128,
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ssa.OpAMD64VCVTPS2UDQ256,
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ssa.OpAMD64VCVTPS2UDQ512,
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ssa.OpAMD64VCVTTPD2DQX128,
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ssa.OpAMD64VCVTTPD2DQY128,
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ssa.OpAMD64VCVTTPD2DQ256,
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ssa.OpAMD64VCVTTPS2QQ256,
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ssa.OpAMD64VCVTTPS2QQ512,
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ssa.OpAMD64VCVTTPD2QQ128,
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ssa.OpAMD64VCVTTPD2QQ256,
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ssa.OpAMD64VCVTTPD2QQ512,
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ssa.OpAMD64VCVTTPS2UDQ128,
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ssa.OpAMD64VCVTTPS2UDQ256,
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ssa.OpAMD64VCVTTPS2UDQ512,
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ssa.OpAMD64VCVTTPD2UDQX128,
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ssa.OpAMD64VCVTTPD2UDQY128,
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ssa.OpAMD64VCVTTPD2UDQ256,
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ssa.OpAMD64VCVTTPS2UQQ256,
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ssa.OpAMD64VCVTTPS2UQQ512,
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ssa.OpAMD64VCVTTPD2UQQ128,
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ssa.OpAMD64VCVTTPD2UQQ256,
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ssa.OpAMD64VCVTTPD2UQQ512,
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ssa.OpAMD64VPMOVSXBQ128,
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ssa.OpAMD64VPMOVSXWQ128,
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ssa.OpAMD64VPMOVSXDQ128,
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@ -819,9 +835,25 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VCVTTPS2DQMasked128,
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ssa.OpAMD64VCVTTPS2DQMasked256,
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ssa.OpAMD64VCVTTPS2DQMasked512,
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ssa.OpAMD64VCVTPS2UDQMasked128,
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ssa.OpAMD64VCVTPS2UDQMasked256,
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ssa.OpAMD64VCVTPS2UDQMasked512,
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ssa.OpAMD64VCVTTPD2DQXMasked128,
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ssa.OpAMD64VCVTTPD2DQYMasked128,
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ssa.OpAMD64VCVTTPD2DQMasked256,
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ssa.OpAMD64VCVTTPS2QQMasked256,
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ssa.OpAMD64VCVTTPS2QQMasked512,
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ssa.OpAMD64VCVTTPD2QQMasked128,
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ssa.OpAMD64VCVTTPD2QQMasked256,
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ssa.OpAMD64VCVTTPD2QQMasked512,
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ssa.OpAMD64VCVTTPS2UDQMasked128,
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ssa.OpAMD64VCVTTPS2UDQMasked256,
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ssa.OpAMD64VCVTTPS2UDQMasked512,
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ssa.OpAMD64VCVTTPD2UDQXMasked128,
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ssa.OpAMD64VCVTTPD2UDQYMasked128,
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ssa.OpAMD64VCVTTPD2UDQMasked256,
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ssa.OpAMD64VCVTTPS2UQQMasked256,
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ssa.OpAMD64VCVTTPS2UQQMasked512,
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ssa.OpAMD64VCVTTPD2UQQMasked128,
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ssa.OpAMD64VCVTTPD2UQQMasked256,
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ssa.OpAMD64VCVTTPD2UQQMasked512,
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ssa.OpAMD64VEXPANDPSMasked128,
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ssa.OpAMD64VEXPANDPSMasked256,
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ssa.OpAMD64VEXPANDPSMasked512,
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@ -1691,9 +1723,25 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VCVTTPS2DQMasked128load,
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ssa.OpAMD64VCVTTPS2DQMasked256load,
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ssa.OpAMD64VCVTTPS2DQMasked512load,
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ssa.OpAMD64VCVTPS2UDQMasked128load,
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ssa.OpAMD64VCVTPS2UDQMasked256load,
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ssa.OpAMD64VCVTPS2UDQMasked512load,
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ssa.OpAMD64VCVTTPD2DQXMasked128load,
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ssa.OpAMD64VCVTTPD2DQYMasked128load,
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ssa.OpAMD64VCVTTPD2DQMasked256load,
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ssa.OpAMD64VCVTTPS2QQMasked256load,
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ssa.OpAMD64VCVTTPS2QQMasked512load,
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ssa.OpAMD64VCVTTPD2QQMasked128load,
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ssa.OpAMD64VCVTTPD2QQMasked256load,
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ssa.OpAMD64VCVTTPD2QQMasked512load,
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ssa.OpAMD64VCVTTPS2UDQMasked128load,
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ssa.OpAMD64VCVTTPS2UDQMasked256load,
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ssa.OpAMD64VCVTTPS2UDQMasked512load,
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ssa.OpAMD64VCVTTPD2UDQXMasked128load,
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ssa.OpAMD64VCVTTPD2UDQYMasked128load,
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ssa.OpAMD64VCVTTPD2UDQMasked256load,
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ssa.OpAMD64VCVTTPS2UQQMasked256load,
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ssa.OpAMD64VCVTTPS2UQQMasked512load,
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ssa.OpAMD64VCVTTPD2UQQMasked128load,
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ssa.OpAMD64VCVTTPD2UQQMasked256load,
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ssa.OpAMD64VCVTTPD2UQQMasked512load,
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ssa.OpAMD64VPLZCNTDMasked128load,
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ssa.OpAMD64VPLZCNTDMasked256load,
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ssa.OpAMD64VPLZCNTDMasked512load,
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@ -2077,9 +2125,23 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPABSQ256load,
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ssa.OpAMD64VPABSQ512load,
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ssa.OpAMD64VCVTTPS2DQ512load,
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ssa.OpAMD64VCVTPS2UDQ128load,
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ssa.OpAMD64VCVTPS2UDQ256load,
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ssa.OpAMD64VCVTPS2UDQ512load,
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ssa.OpAMD64VCVTTPD2DQ256load,
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ssa.OpAMD64VCVTTPS2QQ256load,
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ssa.OpAMD64VCVTTPS2QQ512load,
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ssa.OpAMD64VCVTTPD2QQ128load,
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ssa.OpAMD64VCVTTPD2QQ256load,
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ssa.OpAMD64VCVTTPD2QQ512load,
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ssa.OpAMD64VCVTTPS2UDQ128load,
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ssa.OpAMD64VCVTTPS2UDQ256load,
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ssa.OpAMD64VCVTTPS2UDQ512load,
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ssa.OpAMD64VCVTTPD2UDQX128load,
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ssa.OpAMD64VCVTTPD2UDQY128load,
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ssa.OpAMD64VCVTTPD2UDQ256load,
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ssa.OpAMD64VCVTTPS2UQQ256load,
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ssa.OpAMD64VCVTTPS2UQQ512load,
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ssa.OpAMD64VCVTTPD2UQQ128load,
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ssa.OpAMD64VCVTTPD2UQQ256load,
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ssa.OpAMD64VCVTTPD2UQQ512load,
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ssa.OpAMD64VPLZCNTD128load,
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ssa.OpAMD64VPLZCNTD256load,
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ssa.OpAMD64VPLZCNTD512load,
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@ -2329,9 +2391,25 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VCVTTPS2DQMasked128Merging,
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ssa.OpAMD64VCVTTPS2DQMasked256Merging,
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ssa.OpAMD64VCVTTPS2DQMasked512Merging,
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ssa.OpAMD64VCVTPS2UDQMasked128Merging,
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ssa.OpAMD64VCVTPS2UDQMasked256Merging,
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ssa.OpAMD64VCVTPS2UDQMasked512Merging,
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ssa.OpAMD64VCVTTPD2DQXMasked128Merging,
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ssa.OpAMD64VCVTTPD2DQYMasked128Merging,
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ssa.OpAMD64VCVTTPD2DQMasked256Merging,
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ssa.OpAMD64VCVTTPS2QQMasked256Merging,
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ssa.OpAMD64VCVTTPS2QQMasked512Merging,
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ssa.OpAMD64VCVTTPD2QQMasked128Merging,
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ssa.OpAMD64VCVTTPD2QQMasked256Merging,
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ssa.OpAMD64VCVTTPD2QQMasked512Merging,
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ssa.OpAMD64VCVTTPS2UDQMasked128Merging,
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ssa.OpAMD64VCVTTPS2UDQMasked256Merging,
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ssa.OpAMD64VCVTTPS2UDQMasked512Merging,
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ssa.OpAMD64VCVTTPD2UDQXMasked128Merging,
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ssa.OpAMD64VCVTTPD2UDQYMasked128Merging,
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ssa.OpAMD64VCVTTPD2UDQMasked256Merging,
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ssa.OpAMD64VCVTTPS2UQQMasked256Merging,
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ssa.OpAMD64VCVTTPS2UQQMasked512Merging,
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ssa.OpAMD64VCVTTPD2UQQMasked128Merging,
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ssa.OpAMD64VCVTTPD2UQQMasked256Merging,
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ssa.OpAMD64VCVTTPD2UQQMasked512Merging,
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ssa.OpAMD64VPMOVSXBQMasked128Merging,
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ssa.OpAMD64VPMOVSXWQMasked128Merging,
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ssa.OpAMD64VPMOVSXDQMasked128Merging,
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@ -2701,12 +2779,44 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VCVTTPS2DQMasked256load,
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ssa.OpAMD64VCVTTPS2DQMasked512,
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ssa.OpAMD64VCVTTPS2DQMasked512load,
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ssa.OpAMD64VCVTPS2UDQMasked128,
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ssa.OpAMD64VCVTPS2UDQMasked128load,
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ssa.OpAMD64VCVTPS2UDQMasked256,
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ssa.OpAMD64VCVTPS2UDQMasked256load,
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ssa.OpAMD64VCVTPS2UDQMasked512,
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ssa.OpAMD64VCVTPS2UDQMasked512load,
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ssa.OpAMD64VCVTTPD2DQXMasked128,
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ssa.OpAMD64VCVTTPD2DQXMasked128load,
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ssa.OpAMD64VCVTTPD2DQYMasked128,
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ssa.OpAMD64VCVTTPD2DQYMasked128load,
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ssa.OpAMD64VCVTTPD2DQMasked256,
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ssa.OpAMD64VCVTTPD2DQMasked256load,
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ssa.OpAMD64VCVTTPS2QQMasked256,
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ssa.OpAMD64VCVTTPS2QQMasked256load,
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ssa.OpAMD64VCVTTPS2QQMasked512,
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ssa.OpAMD64VCVTTPS2QQMasked512load,
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ssa.OpAMD64VCVTTPD2QQMasked128,
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ssa.OpAMD64VCVTTPD2QQMasked128load,
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ssa.OpAMD64VCVTTPD2QQMasked256,
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ssa.OpAMD64VCVTTPD2QQMasked256load,
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ssa.OpAMD64VCVTTPD2QQMasked512,
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ssa.OpAMD64VCVTTPD2QQMasked512load,
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ssa.OpAMD64VCVTTPS2UDQMasked128,
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ssa.OpAMD64VCVTTPS2UDQMasked128load,
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ssa.OpAMD64VCVTTPS2UDQMasked256,
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ssa.OpAMD64VCVTTPS2UDQMasked256load,
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ssa.OpAMD64VCVTTPS2UDQMasked512,
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ssa.OpAMD64VCVTTPS2UDQMasked512load,
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ssa.OpAMD64VCVTTPD2UDQXMasked128,
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ssa.OpAMD64VCVTTPD2UDQXMasked128load,
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ssa.OpAMD64VCVTTPD2UDQYMasked128,
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ssa.OpAMD64VCVTTPD2UDQYMasked128load,
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ssa.OpAMD64VCVTTPD2UDQMasked256,
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ssa.OpAMD64VCVTTPD2UDQMasked256load,
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ssa.OpAMD64VCVTTPS2UQQMasked256,
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ssa.OpAMD64VCVTTPS2UQQMasked256load,
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ssa.OpAMD64VCVTTPS2UQQMasked512,
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ssa.OpAMD64VCVTTPS2UQQMasked512load,
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ssa.OpAMD64VCVTTPD2UQQMasked128,
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ssa.OpAMD64VCVTTPD2UQQMasked128load,
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ssa.OpAMD64VCVTTPD2UQQMasked256,
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ssa.OpAMD64VCVTTPD2UQQMasked256load,
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ssa.OpAMD64VCVTTPD2UQQMasked512,
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ssa.OpAMD64VCVTTPD2UQQMasked512load,
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ssa.OpAMD64VDIVPSMasked128,
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ssa.OpAMD64VDIVPSMasked128load,
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ssa.OpAMD64VDIVPSMasked256,
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@ -252,9 +252,25 @@
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(ConvertToInt32Float32x4 ...) => (VCVTTPS2DQ128 ...)
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(ConvertToInt32Float32x8 ...) => (VCVTTPS2DQ256 ...)
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(ConvertToInt32Float32x16 ...) => (VCVTTPS2DQ512 ...)
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(ConvertToUint32Float32x4 ...) => (VCVTPS2UDQ128 ...)
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(ConvertToUint32Float32x8 ...) => (VCVTPS2UDQ256 ...)
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(ConvertToUint32Float32x16 ...) => (VCVTPS2UDQ512 ...)
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(ConvertToInt32Float64x2 ...) => (VCVTTPD2DQX128 ...)
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(ConvertToInt32Float64x4 ...) => (VCVTTPD2DQY128 ...)
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(ConvertToInt32Float64x8 ...) => (VCVTTPD2DQ256 ...)
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(ConvertToInt64Float32x4 ...) => (VCVTTPS2QQ256 ...)
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(ConvertToInt64Float32x8 ...) => (VCVTTPS2QQ512 ...)
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(ConvertToInt64Float64x2 ...) => (VCVTTPD2QQ128 ...)
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(ConvertToInt64Float64x4 ...) => (VCVTTPD2QQ256 ...)
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(ConvertToInt64Float64x8 ...) => (VCVTTPD2QQ512 ...)
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(ConvertToUint32Float32x4 ...) => (VCVTTPS2UDQ128 ...)
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(ConvertToUint32Float32x8 ...) => (VCVTTPS2UDQ256 ...)
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(ConvertToUint32Float32x16 ...) => (VCVTTPS2UDQ512 ...)
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(ConvertToUint32Float64x2 ...) => (VCVTTPD2UDQX128 ...)
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(ConvertToUint32Float64x4 ...) => (VCVTTPD2UDQY128 ...)
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(ConvertToUint32Float64x8 ...) => (VCVTTPD2UDQ256 ...)
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(ConvertToUint64Float32x4 ...) => (VCVTTPS2UQQ256 ...)
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(ConvertToUint64Float32x8 ...) => (VCVTTPS2UQQ512 ...)
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(ConvertToUint64Float64x2 ...) => (VCVTTPD2UQQ128 ...)
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(ConvertToUint64Float64x4 ...) => (VCVTTPD2UQQ256 ...)
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(ConvertToUint64Float64x8 ...) => (VCVTTPD2UQQ512 ...)
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(CopySignInt8x16 ...) => (VPSIGNB128 ...)
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(CopySignInt8x32 ...) => (VPSIGNB256 ...)
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(CopySignInt16x8 ...) => (VPSIGNW128 ...)
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@ -1443,9 +1459,25 @@
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(VMOVDQU32Masked128 (VCVTTPS2DQ128 x) mask) => (VCVTTPS2DQMasked128 x mask)
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(VMOVDQU32Masked256 (VCVTTPS2DQ256 x) mask) => (VCVTTPS2DQMasked256 x mask)
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(VMOVDQU32Masked512 (VCVTTPS2DQ512 x) mask) => (VCVTTPS2DQMasked512 x mask)
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(VMOVDQU32Masked128 (VCVTPS2UDQ128 x) mask) => (VCVTPS2UDQMasked128 x mask)
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(VMOVDQU32Masked256 (VCVTPS2UDQ256 x) mask) => (VCVTPS2UDQMasked256 x mask)
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(VMOVDQU32Masked512 (VCVTPS2UDQ512 x) mask) => (VCVTPS2UDQMasked512 x mask)
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(VMOVDQU64Masked128 (VCVTTPD2DQX128 x) mask) => (VCVTTPD2DQXMasked128 x mask)
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(VMOVDQU64Masked128 (VCVTTPD2DQY128 x) mask) => (VCVTTPD2DQYMasked128 x mask)
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(VMOVDQU64Masked256 (VCVTTPD2DQ256 x) mask) => (VCVTTPD2DQMasked256 x mask)
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(VMOVDQU32Masked256 (VCVTTPS2QQ256 x) mask) => (VCVTTPS2QQMasked256 x mask)
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(VMOVDQU32Masked512 (VCVTTPS2QQ512 x) mask) => (VCVTTPS2QQMasked512 x mask)
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(VMOVDQU64Masked128 (VCVTTPD2QQ128 x) mask) => (VCVTTPD2QQMasked128 x mask)
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(VMOVDQU64Masked256 (VCVTTPD2QQ256 x) mask) => (VCVTTPD2QQMasked256 x mask)
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(VMOVDQU64Masked512 (VCVTTPD2QQ512 x) mask) => (VCVTTPD2QQMasked512 x mask)
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(VMOVDQU32Masked128 (VCVTTPS2UDQ128 x) mask) => (VCVTTPS2UDQMasked128 x mask)
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(VMOVDQU32Masked256 (VCVTTPS2UDQ256 x) mask) => (VCVTTPS2UDQMasked256 x mask)
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(VMOVDQU32Masked512 (VCVTTPS2UDQ512 x) mask) => (VCVTTPS2UDQMasked512 x mask)
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(VMOVDQU64Masked128 (VCVTTPD2UDQX128 x) mask) => (VCVTTPD2UDQXMasked128 x mask)
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(VMOVDQU64Masked128 (VCVTTPD2UDQY128 x) mask) => (VCVTTPD2UDQYMasked128 x mask)
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(VMOVDQU64Masked256 (VCVTTPD2UDQ256 x) mask) => (VCVTTPD2UDQMasked256 x mask)
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(VMOVDQU32Masked256 (VCVTTPS2UQQ256 x) mask) => (VCVTTPS2UQQMasked256 x mask)
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(VMOVDQU32Masked512 (VCVTTPS2UQQ512 x) mask) => (VCVTTPS2UQQMasked512 x mask)
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(VMOVDQU64Masked128 (VCVTTPD2UQQ128 x) mask) => (VCVTTPD2UQQMasked128 x mask)
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(VMOVDQU64Masked256 (VCVTTPD2UQQ256 x) mask) => (VCVTTPD2UQQMasked256 x mask)
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(VMOVDQU64Masked512 (VCVTTPD2UQQ512 x) mask) => (VCVTTPD2UQQMasked512 x mask)
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(VMOVDQU32Masked128 (VDIVPS128 x y) mask) => (VDIVPSMasked128 x y mask)
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(VMOVDQU32Masked256 (VDIVPS256 x y) mask) => (VDIVPSMasked256 x y mask)
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(VMOVDQU32Masked512 (VDIVPS512 x y) mask) => (VDIVPSMasked512 x y mask)
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@ -1907,8 +1939,8 @@
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(VPBLENDMBMasked512 dst (VPSUBSB512 x y) mask) => (VPSUBSBMasked512Merging dst x y mask)
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(VPBLENDMBMasked512 dst (VPSUBUSB512 x y) mask) => (VPSUBUSBMasked512Merging dst x y mask)
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(VPBLENDMDMasked512 dst (VADDPS512 x y) mask) => (VADDPSMasked512Merging dst x y mask)
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(VPBLENDMDMasked512 dst (VCVTPS2UDQ512 x) mask) => (VCVTPS2UDQMasked512Merging dst x mask)
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(VPBLENDMDMasked512 dst (VCVTTPS2DQ512 x) mask) => (VCVTTPS2DQMasked512Merging dst x mask)
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(VPBLENDMDMasked512 dst (VCVTTPS2UDQ512 x) mask) => (VCVTTPS2UDQMasked512Merging dst x mask)
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(VPBLENDMDMasked512 dst (VDIVPS512 x y) mask) => (VDIVPSMasked512Merging dst x y mask)
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(VPBLENDMDMasked512 dst (VMAXPS512 x y) mask) => (VMAXPSMasked512Merging dst x y mask)
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(VPBLENDMDMasked512 dst (VMINPS512 x y) mask) => (VMINPSMasked512Merging dst x y mask)
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@ -1953,6 +1985,10 @@
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(VPBLENDMDMasked512 dst (VSQRTPS512 x) mask) => (VSQRTPSMasked512Merging dst x mask)
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(VPBLENDMDMasked512 dst (VSUBPS512 x y) mask) => (VSUBPSMasked512Merging dst x y mask)
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(VPBLENDMQMasked512 dst (VADDPD512 x y) mask) => (VADDPDMasked512Merging dst x y mask)
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(VPBLENDMQMasked512 dst (VCVTTPD2DQ256 x) mask) => (VCVTTPD2DQMasked256Merging dst x mask)
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(VPBLENDMQMasked512 dst (VCVTTPD2QQ512 x) mask) => (VCVTTPD2QQMasked512Merging dst x mask)
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(VPBLENDMQMasked512 dst (VCVTTPD2UDQ256 x) mask) => (VCVTTPD2UDQMasked256Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTTPD2UQQ512 x) mask) => (VCVTTPD2UQQMasked512Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VDIVPD512 x y) mask) => (VDIVPDMasked512Merging dst x y mask)
|
||||
(VPBLENDMQMasked512 dst (VMAXPD512 x y) mask) => (VMAXPDMasked512Merging dst x y mask)
|
||||
(VPBLENDMQMasked512 dst (VMINPD512 x y) mask) => (VMINPDMasked512Merging dst x y mask)
|
||||
|
|
@ -2033,8 +2069,14 @@
|
|||
(VPBLENDVB128 dst (VBROADCASTSS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VBROADCASTSS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VBROADCASTSS512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked512Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTPS2UDQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPS2UDQMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPD2DQX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2DQXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPD2QQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2QQMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPD2UDQX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UDQXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPD2UQQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UQQMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPS2DQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2DQMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPS2QQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2QQMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPS2UDQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UDQMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPS2UQQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UQQMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VDIVPD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPDMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VDIVPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VGF2P8MULB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VGF2P8MULBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
|
||||
|
|
@ -2202,8 +2244,14 @@
|
|||
(VPBLENDVB128 dst (VSUBPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSUBPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VADDPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VADDPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTPS2UDQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTPS2UDQMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPD2DQY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2DQYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPD2QQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2QQMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPD2UDQY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UDQYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPD2UQQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UQQMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPS2DQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2DQMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPS2QQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2QQMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPS2UDQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UDQMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPS2UQQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UQQMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VDIVPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VDIVPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VGF2P8MULB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VGF2P8MULBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
|
||||
|
|
@ -2428,15 +2476,45 @@
|
|||
(VPERMI2PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PDMasked512load {sym} [off] x y ptr mask mem)
|
||||
(VPERMI2QMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked512load {sym} [off] x y ptr mask mem)
|
||||
(VCVTTPS2DQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ512load {sym} [off] ptr mem)
|
||||
(VCVTTPD2DQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPS2DQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2DQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2DQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTPS2UDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQ128load {sym} [off] ptr mem)
|
||||
(VCVTPS2UDQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQ256load {sym} [off] ptr mem)
|
||||
(VCVTPS2UDQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQ512load {sym} [off] ptr mem)
|
||||
(VCVTPS2UDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTPS2UDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTPS2UDQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTPS2UDQMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2DQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQXMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2DQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQYMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2DQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2QQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPS2QQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQ512load {sym} [off] ptr mem)
|
||||
(VCVTTPD2QQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQ128load {sym} [off] ptr mem)
|
||||
(VCVTTPD2QQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPD2QQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQ512load {sym} [off] ptr mem)
|
||||
(VCVTTPS2QQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2QQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2QQMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2QQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2QQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2QQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2QQMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2UDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQ128load {sym} [off] ptr mem)
|
||||
(VCVTTPS2UDQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPS2UDQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQ512load {sym} [off] ptr mem)
|
||||
(VCVTTPD2UDQX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQX128load {sym} [off] ptr mem)
|
||||
(VCVTTPD2UDQY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQY128load {sym} [off] ptr mem)
|
||||
(VCVTTPD2UDQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPS2UDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2UDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2UDQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UDQMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2UDQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQXMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2UDQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQYMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2UDQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UDQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2UQQ256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPS2UQQ512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQ512load {sym} [off] ptr mem)
|
||||
(VCVTTPD2UQQ128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQ128load {sym} [off] ptr mem)
|
||||
(VCVTTPD2UQQ256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPD2UQQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQ512load {sym} [off] ptr mem)
|
||||
(VCVTTPS2UQQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2UQQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2UQQMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2UQQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2UQQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTTPD2UQQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2UQQMasked512load {sym} [off] ptr mask mem)
|
||||
(VDIVPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPS512load {sym} [off] x ptr mem)
|
||||
(VDIVPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VDIVPD512load {sym} [off] x ptr mem)
|
||||
(VDIVPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VDIVPSMasked128load {sym} [off] x ptr mask mem)
|
||||
|
|
|
|||
|
|
@ -56,18 +56,50 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
|||
{name: "VCOMPRESSPSMasked128", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCOMPRESSPSMasked256", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCOMPRESSPSMasked512", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQ128", argLength: 1, reg: w11, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQ256", argLength: 1, reg: w11, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQ512", argLength: 1, reg: w11, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQMasked128", argLength: 2, reg: wkw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQMasked256", argLength: 2, reg: wkw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQMasked512", argLength: 2, reg: wkw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQ256", argLength: 1, reg: w11, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQX128", argLength: 1, reg: v11, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQXMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQY128", argLength: 1, reg: v11, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQYMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQ128", argLength: 1, reg: w11, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQ256", argLength: 1, reg: w11, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQ512", argLength: 1, reg: w11, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQ256", argLength: 1, reg: w11, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQX128", argLength: 1, reg: w11, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQXMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQY128", argLength: 1, reg: w11, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQYMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQ128", argLength: 1, reg: w11, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQ256", argLength: 1, reg: w11, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQ512", argLength: 1, reg: w11, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQ128", argLength: 1, reg: v11, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQ256", argLength: 1, reg: v11, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQ512", argLength: 1, reg: w11, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQ256", argLength: 1, reg: w11, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQ512", argLength: 1, reg: w11, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQ128", argLength: 1, reg: w11, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQ256", argLength: 1, reg: w11, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQ512", argLength: 1, reg: w11, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQMasked128", argLength: 2, reg: wkw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQ256", argLength: 1, reg: w11, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQ512", argLength: 1, reg: w11, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VDIVPD128", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VDIVPD256", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VDIVPD512", argLength: 2, reg: w21, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
|
|
@ -1405,16 +1437,46 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
|||
{name: "VADDPSMasked128load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VADDPSMasked256load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VADDPSMasked512load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQ128load", argLength: 2, reg: w11load, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQ256load", argLength: 2, reg: w11load, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQ512load", argLength: 2, reg: w11load, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTPS2UDQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQ128load", argLength: 2, reg: w11load, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQ512load", argLength: 2, reg: w11load, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2QQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQX128load", argLength: 2, reg: w11load, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQY128load", argLength: 2, reg: w11load, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UDQYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQ128load", argLength: 2, reg: w11load, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQ512load", argLength: 2, reg: w11load, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2UQQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2DQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQ256load", argLength: 2, reg: w11load, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2QQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQ128load", argLength: 2, reg: w11load, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQ256load", argLength: 2, reg: w11load, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UDQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQ256load", argLength: 2, reg: w11load, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VDIVPD512load", argLength: 3, reg: w21load, asm: "VDIVPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VDIVPDMasked128load", argLength: 4, reg: w2kwload, asm: "VDIVPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VDIVPDMasked256load", argLength: 4, reg: w2kwload, asm: "VDIVPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
|
|
@ -1962,12 +2024,28 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
|||
{name: "VBROADCASTSSMasked128Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VBROADCASTSSMasked256Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VBROADCASTSSMasked512Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTPS2UDQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTPS2UDQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTPS2UDQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTTPD2DQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPD2DQXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2DQYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2QQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2QQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPD2QQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2QQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTTPD2UDQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UDQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPD2UDQXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UDQX", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2UDQYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UDQY", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2UQQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2UQQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPD2UQQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2UQQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTTPS2DQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPS2DQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPS2DQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2DQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTTPS2QQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPS2QQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2QQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTTPS2UDQMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPS2UDQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPS2UDQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTTPS2UQQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPS2UQQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VDIVPDMasked128Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VDIVPDMasked256Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VDIVPDMasked512Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
|
|
|
|||
|
|
@ -240,9 +240,25 @@ func simdGenericOps() []opData {
|
|||
{name: "ConvertToInt32Float32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float32x16", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt64Float32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt64Float32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt64Float64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt64Float64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt64Float64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint32Float32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint32Float32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint32Float32x16", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint32Float64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint32Float64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint32Float64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint64Float32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint64Float32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint64Float64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint64Float64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToUint64Float64x8", argLength: 1, commutative: false},
|
||||
{name: "CopySignInt8x16", argLength: 2, commutative: false},
|
||||
{name: "CopySignInt8x32", argLength: 2, commutative: false},
|
||||
{name: "CopySignInt16x8", argLength: 2, commutative: false},
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -264,9 +264,25 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Float32x4.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float64x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float64x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float32x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float32x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.ConvertToInt64", opLen1(ssa.OpConvertToInt64Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float64x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.ConvertToUint32", opLen1(ssa.OpConvertToUint32Float64x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float32x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float32x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.ConvertToUint64", opLen1(ssa.OpConvertToUint64Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Int8x16.CopySign", opLen2(ssa.OpCopySignInt8x16, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Int8x32.CopySign", opLen2(ssa.OpCopySignInt8x32, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Int16x8.CopySign", opLen2(ssa.OpCopySignInt16x8, types.TypeVec128), sys.AMD64)
|
||||
|
|
|
|||
|
|
@ -322,7 +322,7 @@ func writeSIMDRules(ops []Operation) *bytes.Buffer {
|
|||
rule := fmt.Sprintf("(VPBLENDVB%d dst (%s %s) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (%sMerging dst %s (VPMOVVec%dx%dToM <types.TypeMask> mask))\n",
|
||||
*maskElem.Bits, noMaskName, data.Args, data.Asm, data.Args, *maskElem.ElemBits, *maskElem.Lanes)
|
||||
if ok && ruleExisting != rule {
|
||||
panic("multiple masked merge rules for one op")
|
||||
panic(fmt.Sprintf("multiple masked merge rules for one op:\n%s\n%s\n", ruleExisting, rule))
|
||||
} else {
|
||||
maskedMergeOpts[noMaskName] = rule
|
||||
}
|
||||
|
|
@ -333,7 +333,7 @@ func writeSIMDRules(ops []Operation) *bytes.Buffer {
|
|||
rule := fmt.Sprintf("(VPBLENDM%sMasked%d dst (%s %s) mask) => (%sMerging dst %s mask)\n",
|
||||
s2n[*maskElem.ElemBits], *maskElem.Bits, noMaskName, data.Args, data.Asm, data.Args)
|
||||
if ok && ruleExisting != rule {
|
||||
panic("multiple masked merge rules for one op")
|
||||
panic(fmt.Sprintf("multiple masked merge rules for one op:\n%s\n%s\n", ruleExisting, rule))
|
||||
} else {
|
||||
maskedMergeOpts[noMaskName] = rule
|
||||
}
|
||||
|
|
|
|||
|
|
@ -335,6 +335,18 @@ func (op *Operation) sortOperand() {
|
|||
})
|
||||
}
|
||||
|
||||
// adjustAsm adjusts the asm to make it align with Go's assembler.
|
||||
func (op *Operation) adjustAsm() {
|
||||
if op.Asm == "VCVTTPD2DQ" || op.Asm == "VCVTTPD2UDQ" {
|
||||
switch *op.In[0].Bits {
|
||||
case 128:
|
||||
op.Asm += "X"
|
||||
case 256:
|
||||
op.Asm += "Y"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// goNormalType returns the Go type name for the result of an Op that
|
||||
// does not return a vector, i.e., that returns a result in a general
|
||||
// register. Currently there's only one family of Ops in Go's simd library
|
||||
|
|
|
|||
|
|
@ -381,6 +381,7 @@ func writeGoDefs(path string, cl unify.Closure) error {
|
|||
}
|
||||
// TODO: verify that this is safe.
|
||||
op.sortOperand()
|
||||
op.adjustAsm()
|
||||
ops = append(ops, op)
|
||||
}
|
||||
slices.SortFunc(ops, compareOperations)
|
||||
|
|
@ -399,9 +400,6 @@ func writeGoDefs(path string, cl unify.Closure) error {
|
|||
if *Verbose {
|
||||
log.Printf("dedup len: %d\n", len(deduped))
|
||||
}
|
||||
if *Verbose {
|
||||
log.Printf("dedup len: %d\n", len(deduped))
|
||||
}
|
||||
if !*FlagNoDedup {
|
||||
// TODO: This can hide mistakes in the API definitions, especially when
|
||||
// multiple patterns result in the same API unintentionally. Make it stricter.
|
||||
|
|
|
|||
|
|
@ -1,6 +1,35 @@
|
|||
!sum
|
||||
# Non-truncating conversions
|
||||
# int<->int or uint<->uint widening, float<->int|uint conversions or trucating conversions.
|
||||
# Float <-> Int conversions
|
||||
- go: "ConvertToInt32"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
- go: "ConvertToUint32"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
- go: "ConvertToInt64"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int64, the indefinite value is returned.
|
||||
- go: "ConvertToUint64"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
|
||||
|
||||
# Int <-> Int conversions
|
||||
- go: "(Extend|Saturate|Truncate)?ToInt8"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
|
|
@ -11,7 +40,7 @@
|
|||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to int16.
|
||||
- go: "(Extend|Saturate|Truncate)?(Convert)?ToInt32"
|
||||
- go: "(Extend|Saturate|Truncate)?ToInt32"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
|
|
@ -31,7 +60,7 @@
|
|||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to uint16.
|
||||
- go: "(Extend|Saturate|Truncate)?(Convert)?ToUint32"
|
||||
- go: "(Extend|Saturate|Truncate)?ToUint32"
|
||||
regexpTag: "convert"
|
||||
commutative: false
|
||||
documentation: !string |-
|
||||
|
|
@ -41,9 +70,7 @@
|
|||
commutative: false
|
||||
documentation: !string |-
|
||||
// NAME converts element values to uint64.
|
||||
|
||||
# low-part only conversions
|
||||
# int<->int or uint<->uint widening conversions.
|
||||
# low-part only Int <-> Int conversions
|
||||
- go: ExtendLo8ToUint16x8
|
||||
commutative: false
|
||||
documentation: !string |-
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
# float32 -> int32
|
||||
- go: ConvertToInt32
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTTPS2DQ"
|
||||
asm: "VCVTTP[SD]2DQ"
|
||||
in:
|
||||
- &fp
|
||||
go: $t
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
# float32 -> uint32
|
||||
- go: ConvertToUint32
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTPS2UDQ"
|
||||
asm: "VCVTTP[SD]2UDQ"
|
||||
in:
|
||||
- *fp
|
||||
out:
|
||||
|
|
@ -24,6 +24,49 @@
|
|||
go: $u
|
||||
base: uint
|
||||
elemBits: 32
|
||||
# float32|float64 -> int64
|
||||
- go: ConvertToInt64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTTPD2QQ"
|
||||
in:
|
||||
- *fp
|
||||
out:
|
||||
- &i64
|
||||
go: $u
|
||||
base: int
|
||||
elemBits: 64
|
||||
- go: ConvertToInt64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTTPS2QQ"
|
||||
in:
|
||||
- *fp
|
||||
out:
|
||||
- go: $u
|
||||
base: int
|
||||
elemBits: 64
|
||||
bits: 256|512
|
||||
# float32|float64 -> uint64
|
||||
- go: ConvertToUint64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTTPD2UQQ"
|
||||
in:
|
||||
- *fp
|
||||
out:
|
||||
- &u64
|
||||
go: $u
|
||||
base: uint
|
||||
elemBits: 64
|
||||
- go: ConvertToUint64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTTPS2UQQ"
|
||||
in:
|
||||
- *fp
|
||||
out:
|
||||
- go: $u
|
||||
base: uint
|
||||
elemBits: 64
|
||||
bits: 256|512
|
||||
|
||||
# Widening integer conversions.
|
||||
# uint8 -> uint16
|
||||
- go: ExtendToUint16
|
||||
|
|
|
|||
|
|
@ -1547,37 +1547,165 @@ func (x Uint8x64) ConcatShiftBytesRightGrouped(constant uint8, y Uint8x64) Uint8
|
|||
/* ConvertToInt32 */
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2DQ, CPU Feature: AVX
|
||||
func (x Float32x4) ConvertToInt32() Int32x4
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2DQ, CPU Feature: AVX
|
||||
func (x Float32x8) ConvertToInt32() Int32x8
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2DQ, CPU Feature: AVX512
|
||||
func (x Float32x16) ConvertToInt32() Int32x16
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2DQX, CPU Feature: AVX
|
||||
func (x Float64x2) ConvertToInt32() Int32x4
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2DQY, CPU Feature: AVX
|
||||
func (x Float64x4) ConvertToInt32() Int32x4
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2DQ, CPU Feature: AVX512
|
||||
func (x Float64x8) ConvertToInt32() Int32x8
|
||||
|
||||
/* ConvertToInt64 */
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int64, the indefinite value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2QQ, CPU Feature: AVX512
|
||||
func (x Float32x4) ConvertToInt64() Int64x4
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int64, the indefinite value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2QQ, CPU Feature: AVX512
|
||||
func (x Float32x8) ConvertToInt64() Int64x8
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int64, the indefinite value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2QQ, CPU Feature: AVX512
|
||||
func (x Float64x2) ConvertToInt64() Int64x2
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int64, the indefinite value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2QQ, CPU Feature: AVX512
|
||||
func (x Float64x4) ConvertToInt64() Int64x4
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int64, the indefinite value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2QQ, CPU Feature: AVX512
|
||||
func (x Float64x8) ConvertToInt64() Int64x8
|
||||
|
||||
/* ConvertToUint32 */
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
//
|
||||
// Asm: VCVTPS2UDQ, CPU Feature: AVX512
|
||||
// Asm: VCVTTPS2UDQ, CPU Feature: AVX512
|
||||
func (x Float32x4) ConvertToUint32() Uint32x4
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
//
|
||||
// Asm: VCVTPS2UDQ, CPU Feature: AVX512
|
||||
// Asm: VCVTTPS2UDQ, CPU Feature: AVX512
|
||||
func (x Float32x8) ConvertToUint32() Uint32x8
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
//
|
||||
// Asm: VCVTPS2UDQ, CPU Feature: AVX512
|
||||
// Asm: VCVTTPS2UDQ, CPU Feature: AVX512
|
||||
func (x Float32x16) ConvertToUint32() Uint32x16
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UDQX, CPU Feature: AVX512
|
||||
func (x Float64x2) ConvertToUint32() Uint32x4
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UDQY, CPU Feature: AVX512
|
||||
func (x Float64x4) ConvertToUint32() Uint32x4
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UDQ, CPU Feature: AVX512
|
||||
func (x Float64x8) ConvertToUint32() Uint32x8
|
||||
|
||||
/* ConvertToUint64 */
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2UQQ, CPU Feature: AVX512
|
||||
func (x Float32x4) ConvertToUint64() Uint64x4
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2UQQ, CPU Feature: AVX512
|
||||
func (x Float32x8) ConvertToUint64() Uint64x8
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UQQ, CPU Feature: AVX512
|
||||
func (x Float64x2) ConvertToUint64() Uint64x2
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UQQ, CPU Feature: AVX512
|
||||
func (x Float64x4) ConvertToUint64() Uint64x4
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UQQ, CPU Feature: AVX512
|
||||
func (x Float64x8) ConvertToUint64() Uint64x8
|
||||
|
||||
/* CopySign */
|
||||
|
||||
// CopySign returns the product of the first operand with -1, 0, or 1,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue