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cmd/internal/obj/riscv: add encoding for compressed riscv64 instructions
Regenerate instruction encodings for riscv64, including rv64_c, rv_c and rv_c_d. Updates #71105 Change-Id: I004cc00290bf018ebb848592d84d924481f03851 Reviewed-on: https://go-review.googlesource.com/c/go/+/523476 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
This commit is contained in:
Joel Sing
parent
320df537cc
commit
924fe98902
3 changed files with 178 additions and 4 deletions
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@ -192,6 +192,47 @@ var Anames = []string{
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"FLEQ",
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"FLTQ",
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"FCLASSQ",
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"CLWSP",
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"CFLWSP",
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"CLDSP",
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"CFLDSP",
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"CSWSP",
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"CSDSP",
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"CFSWSP",
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"CFSDSP",
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"CLW",
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"CLD",
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"CFLW",
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"CFLD",
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"CSW",
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"CSD",
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"CFSW",
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"CFSD",
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"CJ",
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"CJR",
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"CJALR",
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"CBEQZ",
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"CBNEZ",
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"CLI",
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"CLUI",
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"CADDI",
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"CADDIW",
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"CADDI16SP",
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"CADDI4SPN",
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"CSLLI",
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"CSRLI",
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"CSRAI",
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"CANDI",
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"CMV",
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"CADD",
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"CAND",
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"COR",
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"CXOR",
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"CSUB",
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"CADDW",
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"CSUBW",
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"CNOP",
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"CEBREAK",
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"ADDUW",
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"SH1ADD",
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"SH1ADDUW",
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@ -551,7 +551,7 @@ const (
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AFNMADDQ
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AFNMSUBQ
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// 22.3 Quad-Precision Convert and Move Instructions
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// 22.3: Quad-Precision Convert and Move Instructions
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AFCVTWQ
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AFCVTLQ
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AFCVTSQ
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@ -568,14 +568,73 @@ const (
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AFSGNJNQ
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AFSGNJXQ
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// 22.4 Quad-Precision Floating-Point Compare Instructions
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// 22.4: Quad-Precision Floating-Point Compare Instructions
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AFEQQ
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AFLEQ
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AFLTQ
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// 22.5 Quad-Precision Floating-Point Classify Instruction
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// 22.5: Quad-Precision Floating-Point Classify Instruction
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AFCLASSQ
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//
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// "C" Extension for Compressed Instructions
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//
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// 26.3.1: Compressed Stack-Pointer-Based Loads and Stores
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ACLWSP
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ACFLWSP
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ACLDSP
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ACFLDSP
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ACSWSP
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ACSDSP
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ACFSWSP
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ACFSDSP
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// 26.3.2: Compressed Register-Based Loads and Stores
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ACLW
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ACLD
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ACFLW
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ACFLD
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ACSW
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ACSD
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ACFSW
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ACFSD
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// 26.4: Compressed Control Transfer Instructions
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ACJ
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ACJR
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ACJALR
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ACBEQZ
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ACBNEZ
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// 26.5.1: Compressed Integer Constant-Generation Instructions
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ACLI
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ACLUI
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ACADDI
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ACADDIW
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ACADDI16SP
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ACADDI4SPN
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ACSLLI
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ACSRLI
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ACSRAI
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ACANDI
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// 26.5.3: Compressed Integer Register-Register Operations
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ACMV
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ACADD
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ACAND
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ACOR
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ACXOR
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ACSUB
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ACADDW
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ACSUBW
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// 26.5.5: Compressed NOP Instruction
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ACNOP
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// 26.5.6: Compressed Breakpoint Instruction
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ACEBREAK
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//
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// "B" Extension for Bit Manipulation, Version 1.0.0
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//
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@ -1,4 +1,4 @@
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// Code generated by ./parse.py -go rv64_a rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbs rv_zicsr; DO NOT EDIT.
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// Code generated by ./parse.py -go rv64_a rv64_c rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_c rv_c_d rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_v rv_zba rv_zbb rv_zbs rv_zicsr; DO NOT EDIT.
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package riscv
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import "cmd/internal/obj"
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@ -96,6 +96,80 @@ func encode(a obj.As) *inst {
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return &inst{0x33, 0x1, 0x0, 0x0, 640, 0x14}
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case ABSETI:
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return &inst{0x13, 0x1, 0x0, 0x0, 640, 0x14}
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case ACADD:
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return &inst{0x2, 0x1, 0x1, 0x0, 0, 0x0}
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case ACADDI:
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return &inst{0x1, 0x0, 0x0, 0x0, 0, 0x0}
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case ACADDI16SP:
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return &inst{0x1, 0x6, 0x0, 0x0, 0, 0x0}
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case ACADDI4SPN:
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return &inst{0x0, 0x0, 0x0, 0x0, 0, 0x0}
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case ACADDIW:
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return &inst{0x1, 0x2, 0x0, 0x0, 0, 0x0}
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case ACADDW:
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return &inst{0x21, 0x1, 0x1, 0x0, 0, 0x0}
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case ACAND:
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return &inst{0x61, 0x0, 0x1, 0x0, 0, 0x0}
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case ACANDI:
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return &inst{0x1, 0x0, 0x1, 0x0, 0, 0x0}
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case ACBEQZ:
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return &inst{0x1, 0x4, 0x1, 0x0, 0, 0x0}
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case ACBNEZ:
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return &inst{0x1, 0x6, 0x1, 0x0, 0, 0x0}
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case ACEBREAK:
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return &inst{0x2, 0x1, 0x1, 0x0, 0, 0x0}
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case ACFLD:
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return &inst{0x0, 0x2, 0x0, 0x0, 0, 0x0}
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case ACFLDSP:
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return &inst{0x2, 0x2, 0x0, 0x0, 0, 0x0}
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case ACFSD:
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return &inst{0x0, 0x2, 0x1, 0x0, 0, 0x0}
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case ACFSDSP:
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return &inst{0x2, 0x2, 0x1, 0x0, 0, 0x0}
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case ACJ:
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return &inst{0x1, 0x2, 0x1, 0x0, 0, 0x0}
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case ACJALR:
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return &inst{0x2, 0x1, 0x1, 0x0, 0, 0x0}
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case ACJR:
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return &inst{0x2, 0x0, 0x1, 0x0, 0, 0x0}
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case ACLD:
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return &inst{0x0, 0x6, 0x0, 0x0, 0, 0x0}
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case ACLDSP:
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return &inst{0x2, 0x6, 0x0, 0x0, 0, 0x0}
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case ACLI:
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return &inst{0x1, 0x4, 0x0, 0x0, 0, 0x0}
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case ACLUI:
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return &inst{0x1, 0x6, 0x0, 0x0, 0, 0x0}
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case ACLW:
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return &inst{0x0, 0x4, 0x0, 0x0, 0, 0x0}
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case ACLWSP:
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return &inst{0x2, 0x4, 0x0, 0x0, 0, 0x0}
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case ACMV:
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return &inst{0x2, 0x0, 0x1, 0x0, 0, 0x0}
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case ACNOP:
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return &inst{0x1, 0x0, 0x0, 0x0, 0, 0x0}
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case ACOR:
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return &inst{0x41, 0x0, 0x1, 0x0, 0, 0x0}
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case ACSD:
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return &inst{0x0, 0x6, 0x1, 0x0, 0, 0x0}
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case ACSDSP:
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return &inst{0x2, 0x6, 0x1, 0x0, 0, 0x0}
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case ACSLLI:
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return &inst{0x2, 0x0, 0x0, 0x0, 0, 0x0}
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case ACSRAI:
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return &inst{0x1, 0x0, 0x1, 0x0, 0, 0x0}
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case ACSRLI:
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return &inst{0x1, 0x0, 0x1, 0x0, 0, 0x0}
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case ACSUB:
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return &inst{0x1, 0x0, 0x1, 0x0, 0, 0x0}
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case ACSUBW:
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return &inst{0x1, 0x1, 0x1, 0x0, 0, 0x0}
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case ACSW:
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return &inst{0x0, 0x4, 0x1, 0x0, 0, 0x0}
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case ACSWSP:
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return &inst{0x2, 0x4, 0x1, 0x0, 0, 0x0}
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case ACXOR:
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return &inst{0x21, 0x0, 0x1, 0x0, 0, 0x0}
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case ACLZ:
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return &inst{0x13, 0x1, 0x0, 0x0, 1536, 0x30}
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case ACLZW:
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