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[dev.simd] runtime: save AVX2 and AVX-512 state on asynchronous preemption
Based on CL 669415 by shaojunyang@google.com. Change-Id: I574f15c3b18a7179a1573aaf567caf18d8602ef1 Reviewed-on: https://go-review.googlesource.com/c/go/+/680900 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Auto-Submit: Austin Clements <austin@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
This commit is contained in:
Austin Clements
Gopher Robot
parent
426cf36b4d
commit
9eeb1e7a9a
4 changed files with 229 additions and 56 deletions
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@ -13,6 +13,7 @@ import (
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const (
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offsetX86HasAVX = unsafe.Offsetof(cpu.X86.HasAVX)
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offsetX86HasAVX2 = unsafe.Offsetof(cpu.X86.HasAVX2)
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offsetX86HasAVX512 = unsafe.Offsetof(cpu.X86.HasAVX512) // F+CD+BW+DQ+VL
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offsetX86HasERMS = unsafe.Offsetof(cpu.X86.HasERMS)
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offsetX86HasRDTSCP = unsafe.Offsetof(cpu.X86.HasRDTSCP)
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@ -285,7 +285,7 @@ func gen386(g *gen) {
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func genAMD64(g *gen) {
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const xReg = "AX" // *xRegState
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p := g.p
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p, label := g.p, g.label
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// Assign stack offsets.
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var l = layout{sp: "SP"}
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@ -297,15 +297,33 @@ func genAMD64(g *gen) {
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l.add("MOVQ", reg, 8)
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}
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}
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lXRegs := layout{sp: xReg} // Non-GP registers
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for _, reg := range regNamesAMD64 {
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if strings.HasPrefix(reg, "X") {
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lXRegs.add("MOVUPS", reg, 16)
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// Create layouts for X, Y, and Z registers.
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const (
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numXRegs = 16
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numZRegs = 16 // TODO: If we start using upper registers, change to 32
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numKRegs = 8
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)
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lZRegs := layout{sp: xReg} // Non-GP registers
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lXRegs, lYRegs := lZRegs, lZRegs
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for i := range numZRegs {
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lZRegs.add("VMOVDQU64", fmt.Sprintf("Z%d", i), 512/8)
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if i < numXRegs {
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// Use SSE-only instructions for X registers.
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lXRegs.add("MOVUPS", fmt.Sprintf("X%d", i), 128/8)
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lYRegs.add("VMOVDQU", fmt.Sprintf("Y%d", i), 256/8)
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}
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}
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writeXRegs(g.goarch, &lXRegs)
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// TODO: MXCSR register?
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for i := range numKRegs {
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lZRegs.add("KMOVQ", fmt.Sprintf("K%d", i), 8)
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}
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// The Z layout is the most general, so we line up the others with that one.
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// We don't have to do this, but it results in a nice Go type. If we split
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// this into multiple types, we probably should stop doing this.
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for i := range lXRegs.regs {
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lXRegs.regs[i].pos = lZRegs.regs[i].pos
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lYRegs.regs[i].pos = lZRegs.regs[i].pos
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}
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writeXRegs(g.goarch, &lZRegs)
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p("PUSHQ BP")
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p("MOVQ SP, BP")
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@ -333,16 +351,56 @@ func genAMD64(g *gen) {
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p("MOVQ g_m(R14), %s", xReg)
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p("MOVQ m_p(%s), %s", xReg, xReg)
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p("LEAQ (p_xRegs+xRegPerP_scratch)(%s), %s", xReg, xReg)
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lXRegs.save(g)
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// Which registers do we need to save?
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p("#ifdef GOEXPERIMENT_simd")
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p("CMPB internal∕cpu·X86+const_offsetX86HasAVX512(SB), $1")
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p("JE saveAVX512")
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p("CMPB internal∕cpu·X86+const_offsetX86HasAVX2(SB), $1")
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p("JE saveAVX2")
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p("#endif")
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// No features. Assume only SSE.
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label("saveSSE:")
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lXRegs.save(g)
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p("JMP preempt")
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label("saveAVX2:")
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lYRegs.save(g)
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p("JMP preempt")
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label("saveAVX512:")
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lZRegs.save(g)
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p("JMP preempt")
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label("preempt:")
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p("CALL ·asyncPreempt2(SB)")
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p("// Restore non-GPs from *p.xRegs.cache")
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p("MOVQ g_m(R14), %s", xReg)
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p("MOVQ m_p(%s), %s", xReg, xReg)
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p("MOVQ (p_xRegs+xRegPerP_cache)(%s), %s", xReg, xReg)
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lXRegs.restore(g)
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p("#ifdef GOEXPERIMENT_simd")
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p("CMPB internal∕cpu·X86+const_offsetX86HasAVX512(SB), $1")
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p("JE restoreAVX512")
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p("CMPB internal∕cpu·X86+const_offsetX86HasAVX2(SB), $1")
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p("JE restoreAVX2")
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p("#endif")
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label("restoreSSE:")
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lXRegs.restore(g)
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p("JMP restoreGPs")
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label("restoreAVX2:")
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lYRegs.restore(g)
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p("JMP restoreGPs")
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label("restoreAVX512:")
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lZRegs.restore(g)
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p("JMP restoreGPs")
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label("restoreGPs:")
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p("// Restore GPs")
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l.restore(g)
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p("ADJSP $%d", -l.stack)
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@ -3,20 +3,28 @@
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package runtime
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type xRegState struct {
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X0 [16]byte
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X1 [16]byte
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X2 [16]byte
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X3 [16]byte
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X4 [16]byte
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X5 [16]byte
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X6 [16]byte
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X7 [16]byte
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X8 [16]byte
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X9 [16]byte
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X10 [16]byte
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X11 [16]byte
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X12 [16]byte
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X13 [16]byte
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X14 [16]byte
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X15 [16]byte
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Z0 [64]byte
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Z1 [64]byte
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Z2 [64]byte
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Z3 [64]byte
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Z4 [64]byte
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Z5 [64]byte
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Z6 [64]byte
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Z7 [64]byte
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Z8 [64]byte
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Z9 [64]byte
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Z10 [64]byte
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Z11 [64]byte
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Z12 [64]byte
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Z13 [64]byte
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Z14 [64]byte
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Z15 [64]byte
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K0 uint64
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K1 uint64
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K2 uint64
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K3 uint64
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K4 uint64
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K5 uint64
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K6 uint64
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K7 uint64
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}
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@ -36,43 +36,149 @@ TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0
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MOVQ g_m(R14), AX
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MOVQ m_p(AX), AX
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LEAQ (p_xRegs+xRegPerP_scratch)(AX), AX
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#ifdef GOEXPERIMENT_simd
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CMPB internal∕cpu·X86+const_offsetX86HasAVX512(SB), $1
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JE saveAVX512
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CMPB internal∕cpu·X86+const_offsetX86HasAVX2(SB), $1
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JE saveAVX2
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#endif
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saveSSE:
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MOVUPS X0, 0(AX)
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MOVUPS X1, 16(AX)
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MOVUPS X2, 32(AX)
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MOVUPS X3, 48(AX)
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MOVUPS X4, 64(AX)
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MOVUPS X5, 80(AX)
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MOVUPS X6, 96(AX)
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MOVUPS X7, 112(AX)
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MOVUPS X8, 128(AX)
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MOVUPS X9, 144(AX)
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MOVUPS X10, 160(AX)
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MOVUPS X11, 176(AX)
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MOVUPS X12, 192(AX)
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MOVUPS X13, 208(AX)
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MOVUPS X14, 224(AX)
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MOVUPS X15, 240(AX)
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MOVUPS X1, 64(AX)
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MOVUPS X2, 128(AX)
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MOVUPS X3, 192(AX)
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MOVUPS X4, 256(AX)
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MOVUPS X5, 320(AX)
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MOVUPS X6, 384(AX)
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MOVUPS X7, 448(AX)
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MOVUPS X8, 512(AX)
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MOVUPS X9, 576(AX)
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MOVUPS X10, 640(AX)
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MOVUPS X11, 704(AX)
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MOVUPS X12, 768(AX)
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MOVUPS X13, 832(AX)
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MOVUPS X14, 896(AX)
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MOVUPS X15, 960(AX)
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JMP preempt
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saveAVX2:
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VMOVDQU Y0, 0(AX)
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VMOVDQU Y1, 64(AX)
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VMOVDQU Y2, 128(AX)
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VMOVDQU Y3, 192(AX)
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VMOVDQU Y4, 256(AX)
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VMOVDQU Y5, 320(AX)
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VMOVDQU Y6, 384(AX)
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VMOVDQU Y7, 448(AX)
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VMOVDQU Y8, 512(AX)
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VMOVDQU Y9, 576(AX)
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VMOVDQU Y10, 640(AX)
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VMOVDQU Y11, 704(AX)
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VMOVDQU Y12, 768(AX)
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VMOVDQU Y13, 832(AX)
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VMOVDQU Y14, 896(AX)
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VMOVDQU Y15, 960(AX)
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JMP preempt
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saveAVX512:
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VMOVDQU64 Z0, 0(AX)
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VMOVDQU64 Z1, 64(AX)
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VMOVDQU64 Z2, 128(AX)
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VMOVDQU64 Z3, 192(AX)
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VMOVDQU64 Z4, 256(AX)
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VMOVDQU64 Z5, 320(AX)
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VMOVDQU64 Z6, 384(AX)
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VMOVDQU64 Z7, 448(AX)
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VMOVDQU64 Z8, 512(AX)
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VMOVDQU64 Z9, 576(AX)
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VMOVDQU64 Z10, 640(AX)
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VMOVDQU64 Z11, 704(AX)
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VMOVDQU64 Z12, 768(AX)
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VMOVDQU64 Z13, 832(AX)
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VMOVDQU64 Z14, 896(AX)
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VMOVDQU64 Z15, 960(AX)
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KMOVQ K0, 1024(AX)
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KMOVQ K1, 1032(AX)
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KMOVQ K2, 1040(AX)
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KMOVQ K3, 1048(AX)
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KMOVQ K4, 1056(AX)
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KMOVQ K5, 1064(AX)
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KMOVQ K6, 1072(AX)
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KMOVQ K7, 1080(AX)
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JMP preempt
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preempt:
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CALL ·asyncPreempt2(SB)
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// Restore non-GPs from *p.xRegs.cache
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MOVQ g_m(R14), AX
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MOVQ m_p(AX), AX
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MOVQ (p_xRegs+xRegPerP_cache)(AX), AX
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MOVUPS 240(AX), X15
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MOVUPS 224(AX), X14
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MOVUPS 208(AX), X13
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MOVUPS 192(AX), X12
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MOVUPS 176(AX), X11
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MOVUPS 160(AX), X10
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MOVUPS 144(AX), X9
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MOVUPS 128(AX), X8
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MOVUPS 112(AX), X7
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MOVUPS 96(AX), X6
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MOVUPS 80(AX), X5
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MOVUPS 64(AX), X4
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MOVUPS 48(AX), X3
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MOVUPS 32(AX), X2
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MOVUPS 16(AX), X1
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#ifdef GOEXPERIMENT_simd
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CMPB internal∕cpu·X86+const_offsetX86HasAVX512(SB), $1
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JE restoreAVX512
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CMPB internal∕cpu·X86+const_offsetX86HasAVX2(SB), $1
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JE restoreAVX2
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#endif
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restoreSSE:
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MOVUPS 960(AX), X15
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MOVUPS 896(AX), X14
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MOVUPS 832(AX), X13
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MOVUPS 768(AX), X12
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MOVUPS 704(AX), X11
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MOVUPS 640(AX), X10
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MOVUPS 576(AX), X9
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MOVUPS 512(AX), X8
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MOVUPS 448(AX), X7
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MOVUPS 384(AX), X6
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MOVUPS 320(AX), X5
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MOVUPS 256(AX), X4
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MOVUPS 192(AX), X3
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MOVUPS 128(AX), X2
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MOVUPS 64(AX), X1
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MOVUPS 0(AX), X0
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JMP restoreGPs
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restoreAVX2:
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VMOVDQU 960(AX), Y15
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VMOVDQU 896(AX), Y14
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VMOVDQU 832(AX), Y13
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VMOVDQU 768(AX), Y12
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VMOVDQU 704(AX), Y11
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VMOVDQU 640(AX), Y10
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VMOVDQU 576(AX), Y9
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VMOVDQU 512(AX), Y8
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VMOVDQU 448(AX), Y7
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VMOVDQU 384(AX), Y6
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VMOVDQU 320(AX), Y5
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VMOVDQU 256(AX), Y4
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VMOVDQU 192(AX), Y3
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VMOVDQU 128(AX), Y2
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VMOVDQU 64(AX), Y1
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VMOVDQU 0(AX), Y0
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JMP restoreGPs
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restoreAVX512:
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KMOVQ 1080(AX), K7
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KMOVQ 1072(AX), K6
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KMOVQ 1064(AX), K5
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KMOVQ 1056(AX), K4
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KMOVQ 1048(AX), K3
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KMOVQ 1040(AX), K2
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KMOVQ 1032(AX), K1
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KMOVQ 1024(AX), K0
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VMOVDQU64 960(AX), Z15
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VMOVDQU64 896(AX), Z14
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VMOVDQU64 832(AX), Z13
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VMOVDQU64 768(AX), Z12
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VMOVDQU64 704(AX), Z11
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VMOVDQU64 640(AX), Z10
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VMOVDQU64 576(AX), Z9
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VMOVDQU64 512(AX), Z8
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VMOVDQU64 448(AX), Z7
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VMOVDQU64 384(AX), Z6
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VMOVDQU64 320(AX), Z5
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VMOVDQU64 256(AX), Z4
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VMOVDQU64 192(AX), Z3
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VMOVDQU64 128(AX), Z2
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VMOVDQU64 64(AX), Z1
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VMOVDQU64 0(AX), Z0
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JMP restoreGPs
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restoreGPs:
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// Restore GPs
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MOVQ 104(SP), R15
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MOVQ 96(SP), R14
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