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[dev.simd] cmd/compile: fix maskreg/simdreg chaos

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This CL fixes some errors left by CL 685895.

Change-Id: I35ee36287fc964a82fd3c88764b688bd4491be65
Reviewed-on: https://go-review.googlesource.com/c/go/+/687095
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
This commit is contained in:
Junyang Shao 2025-07-09 22:33:25 +00:00
parent 47b07a87a6
commit ab7f839280
1 changed files with 14 additions and 5 deletions
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19
src/cmd/compile/internal/amd64/ssa.go
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@ -1043,8 +1043,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
x := v.Args[0].Reg() x := v.Args[0].Reg()
y := v.Reg() y := v.Reg()
if v.Type.IsSIMD() { if v.Type.IsSIMD() {
x = simdReg(v.Args[0]) x = simdOrMaskReg(v.Args[0])
y = simdReg(v) y = simdOrMaskReg(v)
} }
if x != y { if x != y {
opregreg(s, moveByType(v.Type), y, x) opregreg(s, moveByType(v.Type), y, x)
@ -1059,7 +1059,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
p.To.Type = obj.TYPE_REG p.To.Type = obj.TYPE_REG
r := v.Reg() r := v.Reg()
if v.Type.IsSIMD() { if v.Type.IsSIMD() {
r = simdReg(v) r = simdOrMaskReg(v)
} }
p.To.Reg = r p.To.Reg = r
@ -1070,7 +1070,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
} }
r := v.Args[0].Reg() r := v.Args[0].Reg()
if v.Type.IsSIMD() { if v.Type.IsSIMD() {
r = simdReg(v.Args[0]) r = simdOrMaskReg(v.Args[0])
} }
p := s.Prog(storeByType(v.Type)) p := s.Prog(storeByType(v.Type))
p.From.Type = obj.TYPE_REG p.From.Type = obj.TYPE_REG
@ -1906,7 +1906,7 @@ func simdReg(v *ssa.Value) int16 {
func maskReg(v *ssa.Value) int16 { func maskReg(v *ssa.Value) int16 {
t := v.Type t := v.Type
if !t.IsSIMD() { if !t.IsSIMD() {
base.Fatalf("simdReg: not a simd type; v=%s, b=b%d, f=%s", v.LongString(), v.Block.ID, v.Block.Func.Name) base.Fatalf("maskReg: not a simd type; v=%s, b=b%d, f=%s", v.LongString(), v.Block.ID, v.Block.Func.Name)
} }
switch t.Size() { switch t.Size() {
case 8: case 8:
@ -1915,6 +1915,15 @@ func maskReg(v *ssa.Value) int16 {
panic("unreachable") panic("unreachable")
} }
// XXX k mask + vec
func simdOrMaskReg(v *ssa.Value) int16 {
t := v.Type
if t.Size() <= 8 {
return maskReg(v)
}
return simdReg(v)
}
// XXX this is used for shift operations only. // XXX this is used for shift operations only.
// regalloc will issue OpCopy with incorrect type, but the assigned // regalloc will issue OpCopy with incorrect type, but the assigned
// register should be correct, and this function is merely checking // register should be correct, and this function is merely checking