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cmd/compile: forward-looking desired register biasing
Improve forward-looking desired register calculations. It is now inter-block and handles a bunch more cases. Fixes #14504 Fixes #14828 Fixes #15254 Change-Id: Ic240fa0ec6a779d80f577f55c8a6c4ac8c1a940a Reviewed-on: https://go-review.googlesource.com/22160 Run-TryBot: Keith Randall <khr@golang.org> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Keith Randall
parent
30c278dbe9
commit
b57ac33331
1 changed files with 426 additions and 123 deletions
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@ -189,11 +189,9 @@ type valState struct {
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uses *use // list of uses in this block
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spill *Value // spilled copy of the Value
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spillUsed bool
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spillUsedShuffle bool // true if used in shuffling, after ordinary uses
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needReg bool // cached value of !v.Type.IsMemory() && !v.Type.IsVoid() && !.v.Type.IsFlags()
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rematerializeable bool // cached value of v.rematerializeable()
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desired register // register we want value to be in, if any
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avoid regMask // registers to avoid if we can
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spillUsedShuffle bool // true if used in shuffling, after ordinary uses
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needReg bool // cached value of !v.Type.IsMemory() && !v.Type.IsVoid() && !.v.Type.IsFlags()
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rematerializeable bool // cached value of v.rematerializeable()
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}
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type regState struct {
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@ -205,10 +203,11 @@ type regState struct {
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type regAllocState struct {
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f *Func
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registers []Register
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numRegs register
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SPReg register
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SBReg register
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registers []Register
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numRegs register
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SPReg register
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SBReg register
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allocatable regMask
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// for each block, its primary predecessor.
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// A predecessor of b is primary if it is the closest
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@ -220,6 +219,11 @@ type regAllocState struct {
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// which are live at the end of b, together with a count of how many instructions
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// forward to the next use.
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live [][]liveInfo
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// desired register assignments at the end of each block.
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// Note that this is a static map computed before allocation occurs. Dynamic
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// register desires (from partially completed allocations) will trump
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// this information.
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desired []desiredState
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// current state of each (preregalloc) Value
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values []valState
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@ -333,6 +337,7 @@ func (s *regAllocState) assignReg(r register, v *Value, c *Value) {
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// If there is no unused register, a Value will be kicked out of
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// a register to make room.
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func (s *regAllocState) allocReg(v *Value, mask regMask) register {
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mask &= s.allocatable
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mask &^= s.nospill
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if mask == 0 {
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s.f.Fatalf("no register available")
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@ -340,20 +345,7 @@ func (s *regAllocState) allocReg(v *Value, mask regMask) register {
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// Pick an unused register if one is available.
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if mask&^s.used != 0 {
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mask &^= s.used
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// Use desired register if we can.
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d := s.values[v.ID].desired
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if d != noRegister && mask>>d&1 != 0 {
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mask = regMask(1) << d
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}
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// Avoid avoidable registers if we can.
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if mask&^s.values[v.ID].avoid != 0 {
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mask &^= s.values[v.ID].avoid
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}
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return pickReg(mask)
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return pickReg(mask &^ s.used)
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}
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// Pick a value to spill. Spill the value with the
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@ -363,10 +355,6 @@ func (s *regAllocState) allocReg(v *Value, mask regMask) register {
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// TODO: if a single value is in multiple registers, spill one of them
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// before spilling a value in just a single register.
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// SP and SB are allocated specially. No regular value should
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// be allocated to them.
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mask &^= 1<<s.SPReg | 1<<s.SBReg
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// Find a register to spill. We spill the register containing the value
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// whose next use is as far in the future as possible.
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// https://en.wikipedia.org/wiki/Page_replacement_algorithm#The_theoretically_optimal_page_replacement_algorithm
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@ -412,14 +400,6 @@ func (s *regAllocState) allocValToReg(v *Value, mask regMask, nospill bool, line
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return s.regs[r].c
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}
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if v.Op != OpSP {
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mask &^= 1 << s.SPReg // dont' spill SP
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}
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if v.Op != OpSB {
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mask &^= 1 << s.SBReg // don't spill SB
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}
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mask &^= s.reserved()
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// Allocate a register.
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r := s.allocReg(v, mask)
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@ -457,6 +437,7 @@ func (s *regAllocState) allocValToReg(v *Value, mask regMask, nospill bool, line
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}
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func (s *regAllocState) init(f *Func) {
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s.f = f
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s.registers = f.Config.registers
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s.numRegs = register(len(s.registers))
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if s.numRegs > noRegister || s.numRegs > register(unsafe.Sizeof(regMask(0))*8) {
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@ -471,7 +452,17 @@ func (s *regAllocState) init(f *Func) {
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}
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}
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s.f = f
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// Figure out which registers we're allowed to use.
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s.allocatable = regMask(1)<<s.numRegs - 1
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s.allocatable &^= 1 << s.SPReg
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s.allocatable &^= 1 << s.SBReg
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if obj.Framepointer_enabled != 0 {
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s.allocatable &^= 1 << 5 // BP
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}
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if s.f.Config.ctxt.Flag_dynlink {
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s.allocatable &^= 1 << 15 // R15
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}
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s.regs = make([]regState, s.numRegs)
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s.values = make([]valState, f.NumValues())
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s.orig = make([]*Value, f.NumValues())
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@ -480,7 +471,6 @@ func (s *regAllocState) init(f *Func) {
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if !v.Type.IsMemory() && !v.Type.IsVoid() && !v.Type.IsFlags() {
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s.values[v.ID].needReg = true
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s.values[v.ID].rematerializeable = v.rematerializeable()
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s.values[v.ID].desired = noRegister
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s.orig[v.ID] = v
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}
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}
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@ -576,9 +566,9 @@ func (s *regAllocState) compatRegs(t Type) regMask {
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if t.IsFloat() || t == TypeInt128 {
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m = 0xffff << 16 // X0-X15
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} else {
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m = 0xffef << 0 // AX-R15, except SP
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m = 0xffff << 0 // AX-R15
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}
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return m &^ s.reserved()
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return m & s.allocatable
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}
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// loopForBlock returns the loop containing block b,
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@ -613,6 +603,16 @@ func (s *regAllocState) regalloc(f *Func) {
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var nSpillsSunkUnused int // # of spills not sunk because they were removed completely
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var nSpillsNotSunkLateUse int // # of spills not sunk because of very late use (in shuffle)
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// Data structure used for computing desired registers.
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var desired desiredState
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// Desired registers for inputs & outputs for each instruction in the block.
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type dentry struct {
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out [4]register // desired output registers
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in [3][4]register // desired input registers (for inputs 0,1, and 2)
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}
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var dinfo []dentry
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if f.Entry != f.Blocks[0] {
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f.Fatalf("entry block must be first")
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}
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@ -845,26 +845,27 @@ func (s *regAllocState) regalloc(f *Func) {
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}
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}
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// Compute preferred registers for each value using a backwards pass.
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// Allocate space to record the desired registers for each value.
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dinfo = dinfo[:0]
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for i := 0; i < len(oldSched); i++ {
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dinfo = append(dinfo, dentry{})
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}
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// Load static desired register info at the end of the block.
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desired.copy(&s.desired[b.ID])
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// Check actual assigned registers at the start of the next block(s).
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// Dynamically assigned registers will trump the static
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// desired registers computed during liveness analysis.
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// Note that we do this phase after startRegs is set above, so that
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// we get the right behavior for a block which branches to itself.
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for _, succ := range b.Succs {
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// TODO: prioritize likely successor.
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// TODO: prioritize likely successor?
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for _, x := range s.startRegs[succ.ID] {
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v := s.orig[x.vid]
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s.values[v.ID].desired = x.r
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}
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// Process phi ops in succ
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i := -1
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for j, p := range succ.Preds {
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if p == b {
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i = j
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break
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}
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}
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if i == -1 {
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s.f.Fatalf("can't find predecssor %s of %s\n", b, succ)
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desired.add(x.vid, x.r)
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}
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// Process phi ops in succ.
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pidx := predIdx(succ, b)
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for _, v := range succ.Values {
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if v.Op != OpPhi {
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break
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@ -872,47 +873,44 @@ func (s *regAllocState) regalloc(f *Func) {
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if !s.values[v.ID].needReg {
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continue
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}
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r, ok := s.f.getHome(v.ID).(*Register)
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rp, ok := s.f.getHome(v.ID).(*Register)
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if !ok {
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continue
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}
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a := s.orig[v.Args[i].ID]
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s.values[a.ID].desired = register(r.Num)
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desired.add(v.Args[pidx].ID, register(rp.Num))
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}
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}
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// Set avoid fields to help desired register availability.
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liveSet.clear()
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for _, e := range s.live[b.ID] {
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liveSet.add(e.ID)
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}
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if v := b.Control; v != nil && s.values[v.ID].needReg {
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liveSet.add(v.ID)
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}
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// Walk values backwards computing desired register info.
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// See computeLive for more comments.
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for i := len(oldSched) - 1; i >= 0; i-- {
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v := oldSched[i]
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liveSet.remove(v.ID)
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r := s.values[v.ID].desired
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if r != noRegister {
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m := regMask(1) << r
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// All live values should avoid this register so
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// it will be available at this point.
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for _, w := range liveSet.contents() {
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s.values[w].avoid |= m
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}
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}
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for _, a := range v.Args {
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if !s.values[a.ID].needReg {
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prefs := desired.remove(v.ID)
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desired.clobber(opcodeTable[v.Op].reg.clobbers)
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for _, j := range opcodeTable[v.Op].reg.inputs {
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if countRegs(j.regs) != 1 {
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continue
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}
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liveSet.add(a.ID)
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desired.clobber(j.regs)
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desired.add(v.Args[j.idx].ID, pickReg(j.regs))
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}
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if opcodeTable[v.Op].resultInArg0 {
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if opcodeTable[v.Op].commutative {
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desired.addList(v.Args[1].ID, prefs)
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}
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desired.addList(v.Args[0].ID, prefs)
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}
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// Save desired registers for this value.
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dinfo[i].out = prefs
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for j, a := range v.Args {
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if j >= len(dinfo[i].in) {
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break
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}
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dinfo[i].in[j] = desired.get(a.ID)
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}
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}
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// Process all the non-phi values.
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for _, v := range oldSched {
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for idx, v := range oldSched {
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if s.f.pass.debug > regDebug {
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fmt.Printf(" processing %s\n", v.LongString())
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}
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@ -960,36 +958,132 @@ func (s *regAllocState) regalloc(f *Func) {
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continue
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}
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if s.f.pass.debug > regDebug {
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fmt.Printf("value %s\n", v.LongString())
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fmt.Printf(" out:")
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for _, r := range dinfo[idx].out {
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if r != noRegister {
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fmt.Printf(" %s", s.registers[r].Name())
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}
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}
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fmt.Println()
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for i := 0; i < len(v.Args) && i < 3; i++ {
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fmt.Printf(" in%d:", i)
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for _, r := range dinfo[idx].in[i] {
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if r != noRegister {
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fmt.Printf(" %s", s.registers[r].Name())
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}
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}
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fmt.Println()
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}
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}
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// Move arguments to registers. Process in an ordering defined
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// by the register specification (most constrained first).
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args = append(args[:0], v.Args...)
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for _, i := range regspec.inputs {
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if i.regs == flagRegMask {
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mask := i.regs
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if mask == flagRegMask {
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// TODO: remove flag input from regspec.inputs.
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continue
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}
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args[i.idx] = s.allocValToReg(v.Args[i.idx], i.regs, true, v.Line)
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if mask&s.values[args[i.idx].ID].regs == 0 {
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// Need a new register for the input.
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mask &= s.allocatable
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mask &^= s.nospill
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// Used desired register if available.
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if i.idx < 3 {
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for _, r := range dinfo[idx].in[i.idx] {
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if r != noRegister && (mask&^s.used)>>r&1 != 0 {
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// Desired register is allowed and unused.
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mask = regMask(1) << r
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break
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}
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}
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}
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// Avoid registers we're saving for other values.
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if mask&^desired.avoid != 0 {
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mask &^= desired.avoid
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}
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}
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args[i.idx] = s.allocValToReg(args[i.idx], mask, true, v.Line)
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}
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// If the output clobbers the input register, and the input register is
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// live beyond the instruction, make another copy of the input register so
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// we don't have to reload the value from the spill location.
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if opcodeTable[v.Op].resultInArg0 &&
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s.liveAfterCurrentInstruction(v.Args[0]) &&
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countRegs(s.values[v.Args[0].ID].regs) == 1 {
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if opcodeTable[v.Op].commutative &&
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(!s.liveAfterCurrentInstruction(v.Args[1]) ||
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countRegs(s.values[v.Args[1].ID].regs) > 1) {
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// Input #1 is dead after the instruction, or we have
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// more than one copy of it in a register. Either way,
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// use that input as the one that is clobbered.
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args[0], args[1] = args[1], args[0]
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} else {
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m := s.compatRegs(v.Args[0].Type)
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m &^= s.values[v.Args[0].ID].regs // a register not already holding v.Args[0]
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s.allocValToReg(v.Args[0], m, true, v.Line)
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// If the output clobbers the input register, make sure we have
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// at least two copies of the input register so we don't
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// have to reload the value from the spill location.
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if opcodeTable[v.Op].resultInArg0 {
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var m regMask
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if !s.liveAfterCurrentInstruction(v.Args[0]) {
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// arg0 is dead. We can clobber its register.
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goto ok
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}
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if countRegs(s.values[v.Args[0].ID].regs) >= 2 {
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// we have at least 2 copies of arg0. We can afford to clobber one.
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goto ok
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}
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if opcodeTable[v.Op].commutative {
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if !s.liveAfterCurrentInstruction(v.Args[1]) {
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args[0], args[1] = args[1], args[0]
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goto ok
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}
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if countRegs(s.values[v.Args[1].ID].regs) >= 2 {
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args[0], args[1] = args[1], args[0]
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goto ok
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}
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}
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// We can't overwrite arg0 (or arg1, if commutative). So we
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// need to make a copy of an input so we have a register we can modify.
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// Possible new registers to copy into.
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m = s.compatRegs(v.Args[0].Type) &^ s.used
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if m == 0 {
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// No free registers. In this case we'll just clobber
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// an input and future uses of that input must use a restore.
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// TODO(khr): We should really do this like allocReg does it,
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// spilling the value with the most distant next use.
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goto ok
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}
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// Try to move an input to the desired output.
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for _, r := range dinfo[idx].out {
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if r != noRegister && m>>r&1 != 0 {
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m = regMask(1) << r
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args[0] = s.allocValToReg(v.Args[0], m, true, v.Line)
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// Note: we update args[0] so the instruction will
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// use the register copy we just made.
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goto ok
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}
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}
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// Try to copy input to its desired location & use its old
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// location as the result register.
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for _, r := range dinfo[idx].in[0] {
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if r != noRegister && m>>r&1 != 0 {
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m = regMask(1) << r
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s.allocValToReg(v.Args[0], m, true, v.Line)
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// Note: no update to args[0] so the instruction will
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// use the original copy.
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goto ok
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}
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}
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if opcodeTable[v.Op].commutative {
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for _, r := range dinfo[idx].in[1] {
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if r != noRegister && m>>r&1 != 0 {
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m = regMask(1) << r
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s.allocValToReg(v.Args[1], m, true, v.Line)
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args[0], args[1] = args[1], args[0]
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goto ok
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}
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}
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}
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// Avoid future fixed uses if we can.
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if m&^desired.avoid != 0 {
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m &^= desired.avoid
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}
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// Save input 0 to a new register so we can clobber it.
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s.allocValToReg(v.Args[0], m, true, v.Line)
|
||||
ok:
|
||||
}
|
||||
|
||||
// Now that all args are in regs, we're ready to issue the value itself.
|
||||
|
|
@ -1004,14 +1098,44 @@ func (s *regAllocState) regalloc(f *Func) {
|
|||
|
||||
// Pick register for output.
|
||||
if s.values[v.ID].needReg {
|
||||
mask := regspec.outputs[0] &^ s.reserved()
|
||||
if mask>>33&1 != 0 {
|
||||
s.f.Fatalf("bad mask %s\n", v.LongString())
|
||||
}
|
||||
mask := regspec.outputs[0] & s.allocatable
|
||||
if opcodeTable[v.Op].resultInArg0 {
|
||||
// Output must use the same register as input 0.
|
||||
r := register(s.f.getHome(args[0].ID).(*Register).Num)
|
||||
mask = regMask(1) << r
|
||||
if !opcodeTable[v.Op].commutative {
|
||||
// Output must use the same register as input 0.
|
||||
r := register(s.f.getHome(args[0].ID).(*Register).Num)
|
||||
mask = regMask(1) << r
|
||||
} else {
|
||||
// Output must use the same register as input 0 or 1.
|
||||
r0 := register(s.f.getHome(args[0].ID).(*Register).Num)
|
||||
r1 := register(s.f.getHome(args[1].ID).(*Register).Num)
|
||||
// Check r0 and r1 for desired output register.
|
||||
found := false
|
||||
for _, r := range dinfo[idx].out {
|
||||
if (r == r0 || r == r1) && (mask&^s.used)>>r&1 != 0 {
|
||||
mask = regMask(1) << r
|
||||
found = true
|
||||
if r == r1 {
|
||||
args[0], args[1] = args[1], args[0]
|
||||
}
|
||||
break
|
||||
}
|
||||
}
|
||||
if !found {
|
||||
// Neither are desired, pick r0.
|
||||
mask = regMask(1) << r0
|
||||
}
|
||||
}
|
||||
}
|
||||
for _, r := range dinfo[idx].out {
|
||||
if r != noRegister && (mask&^s.used)>>r&1 != 0 {
|
||||
// Desired register is allowed and unused.
|
||||
mask = regMask(1) << r
|
||||
break
|
||||
}
|
||||
}
|
||||
// Avoid registers we're saving for other values.
|
||||
if mask&^desired.avoid != 0 {
|
||||
mask &^= desired.avoid
|
||||
}
|
||||
r := s.allocReg(v, mask)
|
||||
s.assignReg(r, v, v)
|
||||
|
|
@ -1089,6 +1213,9 @@ func (s *regAllocState) regalloc(f *Func) {
|
|||
}
|
||||
v := s.orig[vid]
|
||||
m := s.compatRegs(v.Type) &^ s.used
|
||||
if m&^desired.avoid != 0 {
|
||||
m &^= desired.avoid
|
||||
}
|
||||
if m != 0 {
|
||||
s.allocValToReg(v, m, false, b.Line)
|
||||
}
|
||||
|
|
@ -1875,24 +2002,36 @@ func (v *Value) rematerializeable() bool {
|
|||
}
|
||||
|
||||
type liveInfo struct {
|
||||
ID ID // ID of variable
|
||||
ID ID // ID of value
|
||||
dist int32 // # of instructions before next use
|
||||
}
|
||||
|
||||
// dblock contains information about desired & avoid registers at the end of a block.
|
||||
type dblock struct {
|
||||
prefers []desiredStateEntry
|
||||
avoid regMask
|
||||
}
|
||||
|
||||
// computeLive computes a map from block ID to a list of value IDs live at the end
|
||||
// of that block. Together with the value ID is a count of how many instructions
|
||||
// to the next use of that value. The resulting map is stored at s.live.
|
||||
// to the next use of that value. The resulting map is stored in s.live.
|
||||
// computeLive also computes the desired register information at the end of each block.
|
||||
// This desired register information is stored in s.desired.
|
||||
// TODO: this could be quadratic if lots of variables are live across lots of
|
||||
// basic blocks. Figure out a way to make this function (or, more precisely, the user
|
||||
// of this function) require only linear size & time.
|
||||
func (s *regAllocState) computeLive() {
|
||||
f := s.f
|
||||
s.live = make([][]liveInfo, f.NumBlocks())
|
||||
s.desired = make([]desiredState, f.NumBlocks())
|
||||
var phis []*Value
|
||||
|
||||
live := newSparseMap(f.NumValues())
|
||||
t := newSparseMap(f.NumValues())
|
||||
|
||||
// Keep track of which value we want in each register.
|
||||
var desired desiredState
|
||||
|
||||
// Instead of iterating over f.Blocks, iterate over their postordering.
|
||||
// Liveness information flows backward, so starting at the end
|
||||
// increases the probability that we will stabilize quickly.
|
||||
|
|
@ -1915,7 +2054,7 @@ func (s *regAllocState) computeLive() {
|
|||
d := int32(len(b.Values))
|
||||
if b.Kind == BlockCall || b.Kind == BlockDefer {
|
||||
// Because we keep no values in registers across a call,
|
||||
// make every use past a call very far away.
|
||||
// make every use past a call appear very far away.
|
||||
d += unlikelyDistance
|
||||
}
|
||||
for _, e := range s.live[b.ID] {
|
||||
|
|
@ -1944,6 +2083,35 @@ func (s *regAllocState) computeLive() {
|
|||
}
|
||||
}
|
||||
}
|
||||
// Propagate desired registers backwards.
|
||||
desired.copy(&s.desired[b.ID])
|
||||
for i := len(b.Values) - 1; i >= 0; i-- {
|
||||
v := b.Values[i]
|
||||
prefs := desired.remove(v.ID)
|
||||
if v.Op == OpPhi {
|
||||
// TODO: if v is a phi, save desired register for phi inputs.
|
||||
// For now, we just drop it and don't propagate
|
||||
// desired registers back though phi nodes.
|
||||
continue
|
||||
}
|
||||
// Cancel desired registers if they get clobbered.
|
||||
desired.clobber(opcodeTable[v.Op].reg.clobbers)
|
||||
// Update desired registers if there are any fixed register inputs.
|
||||
for _, j := range opcodeTable[v.Op].reg.inputs {
|
||||
if countRegs(j.regs) != 1 {
|
||||
continue
|
||||
}
|
||||
desired.clobber(j.regs)
|
||||
desired.add(v.Args[j.idx].ID, pickReg(j.regs))
|
||||
}
|
||||
// Set desired register of input 0 if this is a 2-operand instruction.
|
||||
if opcodeTable[v.Op].resultInArg0 {
|
||||
if opcodeTable[v.Op].commutative {
|
||||
desired.addList(v.Args[1].ID, prefs)
|
||||
}
|
||||
desired.addList(v.Args[0].ID, prefs)
|
||||
}
|
||||
}
|
||||
|
||||
// For each predecessor of b, expand its list of live-at-end values.
|
||||
// invariant: live contains the values live at the start of b (excluding phi inputs)
|
||||
|
|
@ -1963,6 +2131,9 @@ func (s *regAllocState) computeLive() {
|
|||
}
|
||||
}
|
||||
|
||||
// Update any desired registers at the end of p.
|
||||
s.desired[p.ID].merge(&desired)
|
||||
|
||||
// Start t off with the previously known live values at the end of p.
|
||||
t.clear()
|
||||
for _, e := range s.live[p.ID] {
|
||||
|
|
@ -1983,7 +2154,7 @@ func (s *regAllocState) computeLive() {
|
|||
// simultaneously happening at the start of the block).
|
||||
for _, v := range phis {
|
||||
id := v.Args[i].ID
|
||||
if s.values[id].needReg && !t.contains(id) || delta < t.get(id) {
|
||||
if s.values[id].needReg && (!t.contains(id) || delta < t.get(id)) {
|
||||
update = true
|
||||
t.set(id, delta)
|
||||
}
|
||||
|
|
@ -2015,20 +2186,152 @@ func (s *regAllocState) computeLive() {
|
|||
fmt.Printf(" %s:", b)
|
||||
for _, x := range s.live[b.ID] {
|
||||
fmt.Printf(" v%d", x.ID)
|
||||
for _, e := range s.desired[b.ID].entries {
|
||||
if e.ID != x.ID {
|
||||
continue
|
||||
}
|
||||
fmt.Printf("[")
|
||||
first := true
|
||||
for _, r := range e.regs {
|
||||
if r == noRegister {
|
||||
continue
|
||||
}
|
||||
if !first {
|
||||
fmt.Printf(",")
|
||||
}
|
||||
fmt.Print(s.registers[r].Name())
|
||||
first = false
|
||||
}
|
||||
fmt.Printf("]")
|
||||
}
|
||||
}
|
||||
fmt.Printf(" avoid=%x", int64(s.desired[b.ID].avoid))
|
||||
fmt.Println()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// reserved returns a mask of reserved registers.
|
||||
func (s *regAllocState) reserved() regMask {
|
||||
var m regMask
|
||||
if obj.Framepointer_enabled != 0 {
|
||||
m |= 1 << 5 // BP
|
||||
}
|
||||
if s.f.Config.ctxt.Flag_dynlink {
|
||||
m |= 1 << 15 // R15
|
||||
}
|
||||
return m
|
||||
// A desiredState represents desired register assignments.
|
||||
type desiredState struct {
|
||||
// Desired assignments will be small, so we just use a list
|
||||
// of valueID+registers entries.
|
||||
entries []desiredStateEntry
|
||||
// Registers that other values want to be in. This value will
|
||||
// contain at least the union of the regs fields of entries, but
|
||||
// may contain additional entries for values that were once in
|
||||
// this data structure but are no longer.
|
||||
avoid regMask
|
||||
}
|
||||
type desiredStateEntry struct {
|
||||
// (pre-regalloc) value
|
||||
ID ID
|
||||
// Registers it would like to be in, in priority order.
|
||||
// Unused slots are filled with noRegister.
|
||||
regs [4]register
|
||||
}
|
||||
|
||||
func (d *desiredState) clear() {
|
||||
d.entries = d.entries[:0]
|
||||
d.avoid = 0
|
||||
}
|
||||
|
||||
// get returns a list of desired registers for value vid.
|
||||
func (d *desiredState) get(vid ID) [4]register {
|
||||
for _, e := range d.entries {
|
||||
if e.ID == vid {
|
||||
return e.regs
|
||||
}
|
||||
}
|
||||
return [4]register{noRegister, noRegister, noRegister, noRegister}
|
||||
}
|
||||
|
||||
// add records that we'd like value vid to be in register r.
|
||||
func (d *desiredState) add(vid ID, r register) {
|
||||
d.avoid |= regMask(1) << r
|
||||
for i := range d.entries {
|
||||
e := &d.entries[i]
|
||||
if e.ID != vid {
|
||||
continue
|
||||
}
|
||||
if e.regs[0] == r {
|
||||
// Already known and highest priority
|
||||
return
|
||||
}
|
||||
for j := 1; j < len(e.regs); j++ {
|
||||
if e.regs[j] == r {
|
||||
// Move from lower priority to top priority
|
||||
copy(e.regs[1:], e.regs[:j])
|
||||
e.regs[0] = r
|
||||
return
|
||||
}
|
||||
}
|
||||
copy(e.regs[1:], e.regs[:])
|
||||
e.regs[0] = r
|
||||
return
|
||||
}
|
||||
d.entries = append(d.entries, desiredStateEntry{vid, [4]register{r, noRegister, noRegister, noRegister}})
|
||||
}
|
||||
|
||||
func (d *desiredState) addList(vid ID, regs [4]register) {
|
||||
// regs is in priority order, so iterate in reverse order.
|
||||
for i := len(regs) - 1; i >= 0; i-- {
|
||||
r := regs[i]
|
||||
if r != noRegister {
|
||||
d.add(vid, r)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// clobber erases any desired registers in the set m.
|
||||
func (d *desiredState) clobber(m regMask) {
|
||||
for i := 0; i < len(d.entries); {
|
||||
e := &d.entries[i]
|
||||
j := 0
|
||||
for _, r := range e.regs {
|
||||
if r != noRegister && m>>r&1 == 0 {
|
||||
e.regs[j] = r
|
||||
j++
|
||||
}
|
||||
}
|
||||
if j == 0 {
|
||||
// No more desired registers for this value.
|
||||
d.entries[i] = d.entries[len(d.entries)-1]
|
||||
d.entries = d.entries[:len(d.entries)-1]
|
||||
continue
|
||||
}
|
||||
for ; j < len(e.regs); j++ {
|
||||
e.regs[j] = noRegister
|
||||
}
|
||||
i++
|
||||
}
|
||||
d.avoid &^= m
|
||||
}
|
||||
|
||||
// copy copies a desired state from another desiredState x.
|
||||
func (d *desiredState) copy(x *desiredState) {
|
||||
d.entries = append(d.entries[:0], x.entries...)
|
||||
d.avoid = x.avoid
|
||||
}
|
||||
|
||||
// remove removes the desired registers for vid and returns them.
|
||||
func (d *desiredState) remove(vid ID) [4]register {
|
||||
for i := range d.entries {
|
||||
if d.entries[i].ID == vid {
|
||||
regs := d.entries[i].regs
|
||||
d.entries[i] = d.entries[len(d.entries)-1]
|
||||
d.entries = d.entries[:len(d.entries)-1]
|
||||
return regs
|
||||
}
|
||||
}
|
||||
return [4]register{noRegister, noRegister, noRegister, noRegister}
|
||||
}
|
||||
|
||||
// merge merges another desired state x into d.
|
||||
func (d *desiredState) merge(x *desiredState) {
|
||||
d.avoid |= x.avoid
|
||||
// There should only be a few desired registers, so
|
||||
// linear insert is ok.
|
||||
for _, e := range x.entries {
|
||||
d.addList(e.ID, e.regs)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue