mirror of
https://github.com/golang/go.git
synced 2025-12-08 06:10:04 +00:00
[dev.simd] cmd/compile, simd: adjust Shift.* operations
This CL does: 1. Removes ShiftRightSignExtended, default signed vectors to shift arithmetic, and unsigned to shift logical. 2. Add the missing Shifts which were left out by YAML error in the generator. This CL is generated by CL 687595. Change-Id: I663115498adb91c82e89a8476e6748794e997cfa Reviewed-on: https://go-review.googlesource.com/c/go/+/687596 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
This commit is contained in:
Junyang Shao
parent
4993a91ae1
commit
b69622b83e
9 changed files with 2021 additions and 1846 deletions
|
|
@ -273,15 +273,6 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
|||
ssa.OpAMD64VPSLLVQ128,
|
||||
ssa.OpAMD64VPSLLVQ256,
|
||||
ssa.OpAMD64VPSLLVQ512,
|
||||
ssa.OpAMD64VPSRLVW128,
|
||||
ssa.OpAMD64VPSRLVW256,
|
||||
ssa.OpAMD64VPSRLVW512,
|
||||
ssa.OpAMD64VPSRLVD128,
|
||||
ssa.OpAMD64VPSRLVD256,
|
||||
ssa.OpAMD64VPSRLVD512,
|
||||
ssa.OpAMD64VPSRLVQ128,
|
||||
ssa.OpAMD64VPSRLVQ256,
|
||||
ssa.OpAMD64VPSRLVQ512,
|
||||
ssa.OpAMD64VPSRAVW128,
|
||||
ssa.OpAMD64VPSRAVW256,
|
||||
ssa.OpAMD64VPSRAVW512,
|
||||
|
|
@ -291,6 +282,15 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
|||
ssa.OpAMD64VPSRAVQ128,
|
||||
ssa.OpAMD64VPSRAVQ256,
|
||||
ssa.OpAMD64VPSRAVQ512,
|
||||
ssa.OpAMD64VPSRLVW128,
|
||||
ssa.OpAMD64VPSRLVW256,
|
||||
ssa.OpAMD64VPSRLVW512,
|
||||
ssa.OpAMD64VPSRLVD128,
|
||||
ssa.OpAMD64VPSRLVD256,
|
||||
ssa.OpAMD64VPSRLVD512,
|
||||
ssa.OpAMD64VPSRLVQ128,
|
||||
ssa.OpAMD64VPSRLVQ256,
|
||||
ssa.OpAMD64VPSRLVQ512,
|
||||
ssa.OpAMD64VPSIGNB128,
|
||||
ssa.OpAMD64VPSIGNB256,
|
||||
ssa.OpAMD64VPSIGNW128,
|
||||
|
|
@ -504,15 +504,6 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
|||
ssa.OpAMD64VPSLLVQMasked128,
|
||||
ssa.OpAMD64VPSLLVQMasked256,
|
||||
ssa.OpAMD64VPSLLVQMasked512,
|
||||
ssa.OpAMD64VPSRLVWMasked128,
|
||||
ssa.OpAMD64VPSRLVWMasked256,
|
||||
ssa.OpAMD64VPSRLVWMasked512,
|
||||
ssa.OpAMD64VPSRLVDMasked128,
|
||||
ssa.OpAMD64VPSRLVDMasked256,
|
||||
ssa.OpAMD64VPSRLVDMasked512,
|
||||
ssa.OpAMD64VPSRLVQMasked128,
|
||||
ssa.OpAMD64VPSRLVQMasked256,
|
||||
ssa.OpAMD64VPSRLVQMasked512,
|
||||
ssa.OpAMD64VPSRAVWMasked128,
|
||||
ssa.OpAMD64VPSRAVWMasked256,
|
||||
ssa.OpAMD64VPSRAVWMasked512,
|
||||
|
|
@ -522,6 +513,15 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
|||
ssa.OpAMD64VPSRAVQMasked128,
|
||||
ssa.OpAMD64VPSRAVQMasked256,
|
||||
ssa.OpAMD64VPSRAVQMasked512,
|
||||
ssa.OpAMD64VPSRLVWMasked128,
|
||||
ssa.OpAMD64VPSRLVWMasked256,
|
||||
ssa.OpAMD64VPSRLVWMasked512,
|
||||
ssa.OpAMD64VPSRLVDMasked128,
|
||||
ssa.OpAMD64VPSRLVDMasked256,
|
||||
ssa.OpAMD64VPSRLVDMasked512,
|
||||
ssa.OpAMD64VPSRLVQMasked128,
|
||||
ssa.OpAMD64VPSRLVQMasked256,
|
||||
ssa.OpAMD64VPSRLVQMasked512,
|
||||
ssa.OpAMD64VSUBPSMasked128,
|
||||
ssa.OpAMD64VSUBPSMasked256,
|
||||
ssa.OpAMD64VSUBPSMasked512,
|
||||
|
|
@ -845,36 +845,60 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
|||
|
||||
case ssa.OpAMD64VPSLLW128,
|
||||
ssa.OpAMD64VPSLLW256,
|
||||
ssa.OpAMD64VPSLLW512,
|
||||
ssa.OpAMD64VPSLLD128,
|
||||
ssa.OpAMD64VPSLLD256,
|
||||
ssa.OpAMD64VPSLLD512,
|
||||
ssa.OpAMD64VPSLLQ128,
|
||||
ssa.OpAMD64VPSLLQ256,
|
||||
ssa.OpAMD64VPSLLQ512,
|
||||
ssa.OpAMD64VPSRLW128,
|
||||
ssa.OpAMD64VPSRLW256,
|
||||
ssa.OpAMD64VPSRLD128,
|
||||
ssa.OpAMD64VPSRLD256,
|
||||
ssa.OpAMD64VPSRLQ128,
|
||||
ssa.OpAMD64VPSRLQ256,
|
||||
ssa.OpAMD64VPSRLQ512,
|
||||
ssa.OpAMD64VPSRAW128,
|
||||
ssa.OpAMD64VPSRAW256,
|
||||
ssa.OpAMD64VPSRAW512,
|
||||
ssa.OpAMD64VPSRAD128,
|
||||
ssa.OpAMD64VPSRAD256,
|
||||
ssa.OpAMD64VPSRAD512,
|
||||
ssa.OpAMD64VPSRAQ128,
|
||||
ssa.OpAMD64VPSRAQ256,
|
||||
ssa.OpAMD64VPSRAQ512:
|
||||
ssa.OpAMD64VPSRAQ512,
|
||||
ssa.OpAMD64VPSRLW128,
|
||||
ssa.OpAMD64VPSRLW256,
|
||||
ssa.OpAMD64VPSRLW512,
|
||||
ssa.OpAMD64VPSRLD128,
|
||||
ssa.OpAMD64VPSRLD256,
|
||||
ssa.OpAMD64VPSRLD512,
|
||||
ssa.OpAMD64VPSRLQ128,
|
||||
ssa.OpAMD64VPSRLQ256,
|
||||
ssa.OpAMD64VPSRLQ512:
|
||||
p = simdVfpv(s, v)
|
||||
|
||||
case ssa.OpAMD64VPSLLQMasked128,
|
||||
case ssa.OpAMD64VPSLLWMasked128,
|
||||
ssa.OpAMD64VPSLLWMasked256,
|
||||
ssa.OpAMD64VPSLLWMasked512,
|
||||
ssa.OpAMD64VPSLLDMasked128,
|
||||
ssa.OpAMD64VPSLLDMasked256,
|
||||
ssa.OpAMD64VPSLLDMasked512,
|
||||
ssa.OpAMD64VPSLLQMasked128,
|
||||
ssa.OpAMD64VPSLLQMasked256,
|
||||
ssa.OpAMD64VPSLLQMasked512,
|
||||
ssa.OpAMD64VPSRLQMasked128,
|
||||
ssa.OpAMD64VPSRLQMasked256,
|
||||
ssa.OpAMD64VPSRLQMasked512,
|
||||
ssa.OpAMD64VPSRAWMasked128,
|
||||
ssa.OpAMD64VPSRAWMasked256,
|
||||
ssa.OpAMD64VPSRAWMasked512,
|
||||
ssa.OpAMD64VPSRADMasked128,
|
||||
ssa.OpAMD64VPSRADMasked256,
|
||||
ssa.OpAMD64VPSRADMasked512,
|
||||
ssa.OpAMD64VPSRAQMasked128,
|
||||
ssa.OpAMD64VPSRAQMasked256,
|
||||
ssa.OpAMD64VPSRAQMasked512:
|
||||
ssa.OpAMD64VPSRAQMasked512,
|
||||
ssa.OpAMD64VPSRLWMasked128,
|
||||
ssa.OpAMD64VPSRLWMasked256,
|
||||
ssa.OpAMD64VPSRLWMasked512,
|
||||
ssa.OpAMD64VPSRLDMasked128,
|
||||
ssa.OpAMD64VPSRLDMasked256,
|
||||
ssa.OpAMD64VPSRLDMasked512,
|
||||
ssa.OpAMD64VPSRLQMasked128,
|
||||
ssa.OpAMD64VPSRLQMasked256,
|
||||
ssa.OpAMD64VPSRLQMasked512:
|
||||
p = simdVfpkv(s, v)
|
||||
|
||||
case ssa.OpAMD64VPINSRB128,
|
||||
|
|
@ -1198,6 +1222,12 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
|||
ssa.OpAMD64VPSHLDQMasked128,
|
||||
ssa.OpAMD64VPSHLDQMasked256,
|
||||
ssa.OpAMD64VPSHLDQMasked512,
|
||||
ssa.OpAMD64VPSLLWMasked128,
|
||||
ssa.OpAMD64VPSLLWMasked256,
|
||||
ssa.OpAMD64VPSLLWMasked512,
|
||||
ssa.OpAMD64VPSLLDMasked128,
|
||||
ssa.OpAMD64VPSLLDMasked256,
|
||||
ssa.OpAMD64VPSLLDMasked512,
|
||||
ssa.OpAMD64VPSLLQMasked128,
|
||||
ssa.OpAMD64VPSLLQMasked256,
|
||||
ssa.OpAMD64VPSLLQMasked512,
|
||||
|
|
@ -1210,12 +1240,24 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
|||
ssa.OpAMD64VPSHRDQMasked128,
|
||||
ssa.OpAMD64VPSHRDQMasked256,
|
||||
ssa.OpAMD64VPSHRDQMasked512,
|
||||
ssa.OpAMD64VPSRLQMasked128,
|
||||
ssa.OpAMD64VPSRLQMasked256,
|
||||
ssa.OpAMD64VPSRLQMasked512,
|
||||
ssa.OpAMD64VPSRAWMasked128,
|
||||
ssa.OpAMD64VPSRAWMasked256,
|
||||
ssa.OpAMD64VPSRAWMasked512,
|
||||
ssa.OpAMD64VPSRADMasked128,
|
||||
ssa.OpAMD64VPSRADMasked256,
|
||||
ssa.OpAMD64VPSRADMasked512,
|
||||
ssa.OpAMD64VPSRAQMasked128,
|
||||
ssa.OpAMD64VPSRAQMasked256,
|
||||
ssa.OpAMD64VPSRAQMasked512,
|
||||
ssa.OpAMD64VPSRLWMasked128,
|
||||
ssa.OpAMD64VPSRLWMasked256,
|
||||
ssa.OpAMD64VPSRLWMasked512,
|
||||
ssa.OpAMD64VPSRLDMasked128,
|
||||
ssa.OpAMD64VPSRLDMasked256,
|
||||
ssa.OpAMD64VPSRLDMasked512,
|
||||
ssa.OpAMD64VPSRLQMasked128,
|
||||
ssa.OpAMD64VPSRLQMasked256,
|
||||
ssa.OpAMD64VPSRLQMasked512,
|
||||
ssa.OpAMD64VPSHLDVWMasked128,
|
||||
ssa.OpAMD64VPSHLDVWMasked256,
|
||||
ssa.OpAMD64VPSHLDVWMasked512,
|
||||
|
|
@ -1243,15 +1285,6 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
|||
ssa.OpAMD64VPSHRDVQMasked128,
|
||||
ssa.OpAMD64VPSHRDVQMasked256,
|
||||
ssa.OpAMD64VPSHRDVQMasked512,
|
||||
ssa.OpAMD64VPSRLVWMasked128,
|
||||
ssa.OpAMD64VPSRLVWMasked256,
|
||||
ssa.OpAMD64VPSRLVWMasked512,
|
||||
ssa.OpAMD64VPSRLVDMasked128,
|
||||
ssa.OpAMD64VPSRLVDMasked256,
|
||||
ssa.OpAMD64VPSRLVDMasked512,
|
||||
ssa.OpAMD64VPSRLVQMasked128,
|
||||
ssa.OpAMD64VPSRLVQMasked256,
|
||||
ssa.OpAMD64VPSRLVQMasked512,
|
||||
ssa.OpAMD64VPSRAVWMasked128,
|
||||
ssa.OpAMD64VPSRAVWMasked256,
|
||||
ssa.OpAMD64VPSRAVWMasked512,
|
||||
|
|
@ -1261,6 +1294,15 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
|||
ssa.OpAMD64VPSRAVQMasked128,
|
||||
ssa.OpAMD64VPSRAVQMasked256,
|
||||
ssa.OpAMD64VPSRAVQMasked512,
|
||||
ssa.OpAMD64VPSRLVWMasked128,
|
||||
ssa.OpAMD64VPSRLVWMasked256,
|
||||
ssa.OpAMD64VPSRLVWMasked512,
|
||||
ssa.OpAMD64VPSRLVDMasked128,
|
||||
ssa.OpAMD64VPSRLVDMasked256,
|
||||
ssa.OpAMD64VPSRLVDMasked512,
|
||||
ssa.OpAMD64VPSRLVQMasked128,
|
||||
ssa.OpAMD64VPSRLVQMasked256,
|
||||
ssa.OpAMD64VPSRLVQMasked512,
|
||||
ssa.OpAMD64VSQRTPSMasked128,
|
||||
ssa.OpAMD64VSQRTPSMasked256,
|
||||
ssa.OpAMD64VSQRTPSMasked512,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue