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runtime: save and restore all fcc registers in async preempt on loong64
Currently, all Op implementations on loong64 use fcc0 by default, so only fcc0 is saved in CL 475577. However, fcc1-fcc7 may also be used by users when writing assembly code, such as in CL 693878. Change-Id: Idb60d8101a0f7d602dfcbbb39bd5da9f2c475bfd Reviewed-on: https://go-review.googlesource.com/c/go/+/696875 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Carlos Amedee <carlos@golang.org>
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parent
119546ea4f
commit
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2 changed files with 55 additions and 5 deletions
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@ -610,10 +610,30 @@ func genLoong64(g *gen) {
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l.add(movf, reg, regsize)
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l.add(movf, reg, regsize)
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}
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}
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// save/restore FCC0
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// Add condition flag register fcc0-fcc7
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sv := ""
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rs := ""
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last := 7
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for i := 0; i <= last; i++ {
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msb := 7 + (i * 8)
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lsb := 0 + (i * 8)
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// MOVV FCCx, R4,
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// BSTRINSV $msb, R4, $lsb, R5
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sv += fmt.Sprintf("%s FCC%d, R4\n", mov, i)
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sv += fmt.Sprintf("BSTRINSV $%d, R4, $%d, R5\n", msb, lsb)
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// BSTRPICKV $msb, R5, $lsb, R4
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// MOVV R4, FCCx
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rs += fmt.Sprintf("BSTRPICKV $%d, R5, $%d, R4\n", msb, lsb)
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rs += fmt.Sprintf("%s R4, FCC%d", mov, i)
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if i != last {
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rs += fmt.Sprintf("\n")
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}
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}
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l.addSpecial(
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l.addSpecial(
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mov+" FCC0, R4\n"+mov+" R4, %d(R3)",
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sv+mov+" R5, %d(R3)",
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mov+" %d(R3), R4\n"+mov+" R4, FCC0",
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mov+" %d(R3), R5\n"+rs,
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regsize)
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regsize)
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// allocate frame, save PC of interrupted instruction (in LR)
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// allocate frame, save PC of interrupted instruction (in LR)
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@ -65,10 +65,40 @@ TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0
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MOVD F30, 456(R3)
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MOVD F30, 456(R3)
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MOVD F31, 464(R3)
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MOVD F31, 464(R3)
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MOVV FCC0, R4
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MOVV FCC0, R4
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MOVV R4, 472(R3)
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BSTRINSV $7, R4, $0, R5
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MOVV FCC1, R4
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BSTRINSV $15, R4, $8, R5
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MOVV FCC2, R4
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BSTRINSV $23, R4, $16, R5
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MOVV FCC3, R4
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BSTRINSV $31, R4, $24, R5
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MOVV FCC4, R4
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BSTRINSV $39, R4, $32, R5
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MOVV FCC5, R4
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BSTRINSV $47, R4, $40, R5
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MOVV FCC6, R4
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BSTRINSV $55, R4, $48, R5
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MOVV FCC7, R4
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BSTRINSV $63, R4, $56, R5
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MOVV R5, 472(R3)
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CALL ·asyncPreempt2(SB)
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CALL ·asyncPreempt2(SB)
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MOVV 472(R3), R4
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MOVV 472(R3), R5
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BSTRPICKV $7, R5, $0, R4
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MOVV R4, FCC0
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MOVV R4, FCC0
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BSTRPICKV $15, R5, $8, R4
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MOVV R4, FCC1
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BSTRPICKV $23, R5, $16, R4
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MOVV R4, FCC2
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BSTRPICKV $31, R5, $24, R4
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MOVV R4, FCC3
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BSTRPICKV $39, R5, $32, R4
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MOVV R4, FCC4
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BSTRPICKV $47, R5, $40, R4
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MOVV R4, FCC5
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BSTRPICKV $55, R5, $48, R4
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MOVV R4, FCC6
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BSTRPICKV $63, R5, $56, R4
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MOVV R4, FCC7
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MOVD 464(R3), F31
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MOVD 464(R3), F31
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MOVD 456(R3), F30
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MOVD 456(R3), F30
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MOVD 448(R3), F29
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MOVD 448(R3), F29
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