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cmd/internal/obj/loong64: add aliases to 32-bit arithmetic instructions
Both the MULW and MUL instructions point to the mul.w instruction in the loong64 ISA. Previously, MULW was not encoded; now it is encoded and used as an alias for MUL. The same applies to the following instructions: ADD, SUB, DIV. For consistency, we have added additional aliases for DIVU, REM and REMU. Change-Id: Iba201a3c4c2893ff7d301ef877fad9c81e54291b Reviewed-on: https://go-review.googlesource.com/c/go/+/721523 Reviewed-by: Cherry Mui <cherryyz@google.com> Auto-Submit: abner chenc <chenguoqi@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
This commit is contained in:
Xiaolin Zhao
Gopher Robot
parent
37ce4adcd4
commit
c0f02c11ff
6 changed files with 45 additions and 8 deletions
16
src/cmd/asm/internal/asm/testdata/loong64enc1.s
vendored
16
src/cmd/asm/internal/asm/testdata/loong64enc1.s
vendored
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@ -33,13 +33,17 @@ lable2:
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MOVV R4, R5 // 85001500
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MOVBU R4, R5 // 85fc4303
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SUB R4, R5, R6 // a6101100
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SUBW R4, R5, R6 // a6101100
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SUBV R4, R5, R6 // a6901100
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ADD R4, R5, R6 // a6101000
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ADDW R4, R5, R6 // a6101000
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ADDV R4, R5, R6 // a6901000
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AND R4, R5, R6 // a6901400
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SUB R4, R5 // a5101100
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SUBW R4, R5 // a5101100
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SUBV R4, R5 // a5901100
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ADD R4, R5 // a5101000
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ADDW R4, R5 // a5101000
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ADDV R4, R5 // a5901000
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AND R4, R5 // a5901400
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NEGW R4, R5 // 05101100
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@ -115,6 +119,8 @@ lable2:
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MOVV $1, R4 // 04048003
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ADD $-1, R4, R5 // 85fcbf02
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ADD $-1, R4 // 84fcbf02
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ADDW $-1, R4, R5 // 85fcbf02
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ADDW $-1, R4 // 84fcbf02
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ADDV $-1, R4, R5 // 85fcff02
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ADDV $-1, R4 // 84fcff02
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AND $1, R4, R5 // 85044003
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@ -165,6 +171,8 @@ lable2:
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// mul
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MUL R4, R5 // a5101c00
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MUL R4, R5, R6 // a6101c00
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MULW R4, R5 // a5101c00
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MULW R4, R5, R6 // a6101c00
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MULV R4, R5 // a5901d00
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MULV R4, R5, R6 // a6901d00
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MULVU R4, R5 // a5901d00
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@ -199,12 +207,20 @@ lable2:
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MULHU R4, R5, R6 // a6101d00
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REM R4, R5 // a5902000
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REM R4, R5, R6 // a6902000
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REMW R4, R5 // a5902000
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REMW R4, R5, R6 // a6902000
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REMU R4, R5 // a5902100
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REMU R4, R5, R6 // a6902100
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REMWU R4, R5 // a5902100
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REMWU R4, R5, R6 // a6902100
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DIV R4, R5 // a5102000
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DIV R4, R5, R6 // a6102000
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DIVW R4, R5 // a5102000
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DIVW R4, R5, R6 // a6102000
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DIVU R4, R5 // a5102100
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DIVU R4, R5, R6 // a6102100
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DIVWU R4, R5 // a5102100
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DIVWU R4, R5, R6 // a6102100
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SRLV R4, R5 // a5101900
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SRLV R4, R5, R6 // a6101900
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SRLV $4, R4, R5 // 85104500
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@ -21,6 +21,10 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
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ADD $4096, R4, R5 // 3e00001485781000
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ADD $65536, R4 // 1e02001484781000
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ADD $4096, R4 // 3e00001484781000
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ADDW $65536, R4, R5 // 1e02001485781000
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ADDW $4096, R4, R5 // 3e00001485781000
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ADDW $65536, R4 // 1e02001484781000
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ADDW $4096, R4 // 3e00001484781000
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ADDV $65536, R4, R5 // 1e02001485f81000
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ADDV $4096, R4, R5 // 3e00001485f81000
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ADDV $65536, R4 // 1e02001484f81000
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@ -11,12 +11,16 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
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MOVV $4096(R4), R5 // 3e000014de03800385f81000
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ADD $74565, R4 // 5e020014de178d0384781000
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ADD $4097, R4 // 3e000014de07800384781000
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ADDW $74565, R4 // 5e020014de178d0384781000
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ADDW $4097, R4 // 3e000014de07800384781000
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ADDV $74565, R4 // 5e020014de178d0384f81000
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ADDV $4097, R4 // 3e000014de07800384f81000
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AND $74565, R4 // 5e020014de178d0384f81400
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AND $4097, R4 // 3e000014de07800384f81400
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ADD $74565, R4, R5 // 5e020014de178d0385781000
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ADD $4097, R4, R5 // 3e000014de07800385781000
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ADDW $74565, R4, R5 // 5e020014de178d0385781000
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ADDW $4097, R4, R5 // 3e000014de07800385781000
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ADDV $74565, R4, R5 // 5e020014de178d0385f81000
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ADDV $4097, R4, R5 // 3e000014de07800385f81000
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AND $74565, R4, R5 // 5e020014de178d0385f81400
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@ -468,6 +468,7 @@ const (
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ADIVF
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ADIVU
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ADIVW
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ADIVWU
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ALL
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ALLV
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@ -508,7 +509,9 @@ const (
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ANOR
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AOR
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AREM
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AREMW
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AREMU
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AREMWU
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ARFE
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@ -43,6 +43,7 @@ var Anames = []string{
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"DIVF",
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"DIVU",
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"DIVW",
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"DIVWU",
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"LL",
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"LLV",
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"LUI",
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@ -74,7 +75,9 @@ var Anames = []string{
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"NOR",
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"OR",
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"REM",
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"REMW",
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"REMU",
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"REMWU",
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"RFE",
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"SC",
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"SCV",
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@ -1428,6 +1428,7 @@ func buildop(ctxt *obj.Link) {
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opset(AFTINTRNEVD, r0)
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case AADD:
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opset(AADDW, r0)
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opset(ASGT, r0)
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opset(ASGTU, r0)
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opset(AADDU, r0)
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@ -1512,18 +1513,24 @@ func buildop(ctxt *obj.Link) {
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opset(ABSTRINSV, r0)
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case ASUB:
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opset(ASUBW, r0)
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opset(ASUBU, r0)
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opset(ANOR, r0)
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opset(ASUBV, r0)
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opset(ASUBVU, r0)
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opset(AMUL, r0)
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opset(AMULW, r0)
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opset(AMULU, r0)
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opset(AMULH, r0)
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opset(AMULHU, r0)
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opset(AREM, r0)
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opset(AREMW, r0)
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opset(AREMU, r0)
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opset(AREMWU, r0)
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opset(ADIV, r0)
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opset(ADIVW, r0)
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opset(ADIVU, r0)
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opset(ADIVWU, r0)
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opset(AMULV, r0)
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opset(AMULVU, r0)
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opset(AMULHV, r0)
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@ -3244,7 +3251,7 @@ func (c *ctxt0) oprrrr(a obj.As) uint32 {
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func (c *ctxt0) oprrr(a obj.As) uint32 {
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switch a {
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case AADD:
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case AADD, AADDW:
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return 0x20 << 15
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case AADDU:
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return 0x20 << 15
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@ -3266,7 +3273,7 @@ func (c *ctxt0) oprrr(a obj.As) uint32 {
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return 0x2c << 15 // orn
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case AANDN:
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return 0x2d << 15 // andn
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case ASUB:
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case ASUB, ASUBW:
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return 0x22 << 15
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case ASUBU, ANEGW:
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return 0x22 << 15
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@ -3297,7 +3304,7 @@ func (c *ctxt0) oprrr(a obj.As) uint32 {
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case ASUBVU, ANEGV:
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return 0x23 << 15
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case AMUL:
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case AMUL, AMULW:
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return 0x38 << 15 // mul.w
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case AMULU:
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return 0x38 << 15 // mul.w
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@ -3317,17 +3324,17 @@ func (c *ctxt0) oprrr(a obj.As) uint32 {
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return 0x3e << 15 // mulw.d.w
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case AMULWVWU:
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return 0x3f << 15 // mulw.d.wu
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case ADIV:
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case ADIV, ADIVW:
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return 0x40 << 15 // div.w
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case ADIVU:
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case ADIVU, ADIVWU:
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return 0x42 << 15 // div.wu
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case ADIVV:
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return 0x44 << 15 // div.d
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case ADIVVU:
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return 0x46 << 15 // div.du
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case AREM:
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case AREM, AREMW:
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return 0x41 << 15 // mod.w
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case AREMU:
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case AREMU, AREMWU:
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return 0x43 << 15 // mod.wu
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case AREMV:
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return 0x45 << 15 // mod.d
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@ -4485,7 +4492,7 @@ func (c *ctxt0) opir(a obj.As) uint32 {
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func (c *ctxt0) opirr(a obj.As) uint32 {
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switch a {
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case AADD, AADDU:
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case AADD, AADDW, AADDU:
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return 0x00a << 22
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case ASGT:
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return 0x008 << 22
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