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cmd/compile, runtime: remove plan9 special case avoiding SSE

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Change-Id: Id5258a72b0727bf7c66d558e30486eac2c6c8c36
Reviewed-on: https://go-review.googlesource.com/c/go/+/655875
Reviewed-by: Keith Randall <khr@golang.org>
Auto-Submit: Russ Cox <rsc@golang.org>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Keith Randall <khr@google.com>
Reviewed-by: David du Colombier <0intro@gmail.com>
This commit is contained in:
Russ Cox 2025-03-04 15:01:54 -05:00 • committed by Gopher Robot
parent 3e033b7553
commit c18ff21cc8
4 changed files with 4 additions and 21 deletions
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8
src/cmd/compile/internal/amd64/ggen.go
View file

@ -10,12 +10,8 @@ import (
"cmd/compile/internal/types" "cmd/compile/internal/types"
"cmd/internal/obj" "cmd/internal/obj"
"cmd/internal/obj/x86" "cmd/internal/obj/x86"
"internal/buildcfg"
) )
// no floating point in note handlers on Plan 9
var isPlan9 = buildcfg.GOOS == "plan9"
// DUFFZERO consists of repeated blocks of 4 MOVUPSs + LEAQ, // DUFFZERO consists of repeated blocks of 4 MOVUPSs + LEAQ,
// See runtime/mkduff.go. // See runtime/mkduff.go.
const ( const (
@ -64,7 +60,7 @@ func zerorange(pp *objw.Progs, p *obj.Prog, off, cnt int64, state *uint32) *obj.
if cnt == 8 { if cnt == 8 {
p = pp.Append(p, x86.AMOVQ, obj.TYPE_REG, x86.REG_X15, 0, obj.TYPE_MEM, x86.REG_SP, off) p = pp.Append(p, x86.AMOVQ, obj.TYPE_REG, x86.REG_X15, 0, obj.TYPE_MEM, x86.REG_SP, off)
} else if !isPlan9 && cnt <= int64(8*types.RegSize) { } else if cnt <= int64(8*types.RegSize) {
for i := int64(0); i < cnt/16; i++ { for i := int64(0); i < cnt/16; i++ {
p = pp.Append(p, x86.AMOVUPS, obj.TYPE_REG, x86.REG_X15, 0, obj.TYPE_MEM, x86.REG_SP, off+i*16) p = pp.Append(p, x86.AMOVUPS, obj.TYPE_REG, x86.REG_X15, 0, obj.TYPE_MEM, x86.REG_SP, off+i*16)
} }
@ -72,7 +68,7 @@ func zerorange(pp *objw.Progs, p *obj.Prog, off, cnt int64, state *uint32) *obj.
if cnt%16 != 0 { if cnt%16 != 0 {
p = pp.Append(p, x86.AMOVUPS, obj.TYPE_REG, x86.REG_X15, 0, obj.TYPE_MEM, x86.REG_SP, off+cnt-int64(16)) p = pp.Append(p, x86.AMOVUPS, obj.TYPE_REG, x86.REG_X15, 0, obj.TYPE_MEM, x86.REG_SP, off+cnt-int64(16))
} }
} else if !isPlan9 && (cnt <= int64(128*types.RegSize)) { } else if cnt <= int64(128*types.RegSize) {
// Save DI to r12. With the amd64 Go register abi, DI can contain // Save DI to r12. With the amd64 Go register abi, DI can contain
// an incoming parameter, whereas R12 is always scratch. // an incoming parameter, whereas R12 is always scratch.
p = pp.Append(p, x86.AMOVQ, obj.TYPE_REG, x86.REG_DI, 0, obj.TYPE_REG, x86.REG_R12, 0) p = pp.Append(p, x86.AMOVQ, obj.TYPE_REG, x86.REG_DI, 0, obj.TYPE_REG, x86.REG_R12, 0)

9
src/cmd/compile/internal/amd64/ssa.go
View file

@ -6,7 +6,6 @@ package amd64
import ( import (
"fmt" "fmt"
"internal/buildcfg"
"math" "math"
"cmd/compile/internal/base" "cmd/compile/internal/base"
@ -1090,9 +1089,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
case ssa.OpAMD64CALLstatic, ssa.OpAMD64CALLtail: case ssa.OpAMD64CALLstatic, ssa.OpAMD64CALLtail:
if s.ABI == obj.ABI0 && v.Aux.(*ssa.AuxCall).Fn.ABI() == obj.ABIInternal { if s.ABI == obj.ABI0 && v.Aux.(*ssa.AuxCall).Fn.ABI() == obj.ABIInternal {
// zeroing X15 when entering ABIInternal from ABI0 // zeroing X15 when entering ABIInternal from ABI0
if buildcfg.GOOS != "plan9" { // do not use SSE on Plan 9 opregreg(s, x86.AXORPS, x86.REG_X15, x86.REG_X15)
opregreg(s, x86.AXORPS, x86.REG_X15, x86.REG_X15)
}
// set G register from TLS // set G register from TLS
getgFromTLS(s, x86.REG_R14) getgFromTLS(s, x86.REG_R14)
} }
@ -1103,9 +1100,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
s.Call(v) s.Call(v)
if s.ABI == obj.ABIInternal && v.Aux.(*ssa.AuxCall).Fn.ABI() == obj.ABI0 { if s.ABI == obj.ABIInternal && v.Aux.(*ssa.AuxCall).Fn.ABI() == obj.ABI0 {
// zeroing X15 when entering ABIInternal from ABI0 // zeroing X15 when entering ABIInternal from ABI0
if buildcfg.GOOS != "plan9" { // do not use SSE on Plan 9 opregreg(s, x86.AXORPS, x86.REG_X15, x86.REG_X15)
opregreg(s, x86.AXORPS, x86.REG_X15, x86.REG_X15)
}
// set G register from TLS // set G register from TLS
getgFromTLS(s, x86.REG_R14) getgFromTLS(s, x86.REG_R14)
} }

6
src/cmd/compile/internal/ssa/config.go
View file

@ -369,12 +369,6 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize, softfloat boo
if buildcfg.GOOS == "plan9" { if buildcfg.GOOS == "plan9" {
// Don't use FMA on Plan 9 // Don't use FMA on Plan 9
c.UseFMA = false c.UseFMA = false
// Don't use Duff's device and SSE on Plan 9 AMD64.
if arch == "amd64" {
c.noDuffDevice = true
c.useSSE = false
}
} }
if ctxt.Flag_shared { if ctxt.Flag_shared {

2
src/runtime/asm_amd64.s
View file

@ -1710,9 +1710,7 @@ TEXT runtime·addmoduledata(SB),NOSPLIT,$0-0
TEXT ·sigpanic0(SB),NOSPLIT,$0-0 TEXT ·sigpanic0(SB),NOSPLIT,$0-0
get_tls(R14) get_tls(R14)
MOVQ g(R14), R14 MOVQ g(R14), R14
#ifndef GOOS_plan9
XORPS X15, X15 XORPS X15, X15
#endif
JMP ·sigpanic<ABIInternal>(SB) JMP ·sigpanic<ABIInternal>(SB)
// gcWriteBarrier informs the GC about heap pointer writes. // gcWriteBarrier informs the GC about heap pointer writes.