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cmd/compile: simplify memory load and store operations on loong64
If the memory load and store operations use the same ptr, they are combined into a direct move operation between registers, like riscv64. Change-Id: I889e51a5146aee7f15340114bc4abd12eb6b8a1f Reviewed-on: https://go-review.googlesource.com/c/go/+/700535 Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Keith Randall <khr@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Pratt <mpratt@google.com> Auto-Submit: Keith Randall <khr@golang.org>
This commit is contained in:
Xiaolin Zhao
Gopher Robot
parent
e8f9127d1f
commit
c552ad913f
2 changed files with 123 additions and 0 deletions
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@ -455,6 +455,10 @@
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(MOVWUload [off] {sym} ptr (MOVFstore [off] {sym} ptr val _)) => (ZeroExt32to64 (MOVWfpgp <typ.Float32> val))
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(MOVFload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) => (MOVWgpfp val)
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// If the memory load and store operations use the same ptr, they are combined into a direct move operation between registers.
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(MOV(V|W|H|B)load [off] {sym} ptr (MOV(V|W|H|B)store [off] {sym} ptr x _)) => (MOV(V|W|H|B)reg x)
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(MOV(W|H|B)Uload [off] {sym} ptr (MOV(W|H|B)store [off] {sym} ptr x _)) => (MOV(W|H|B)Ureg x)
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// Similarly for stores, if we see a store after FPR <=> GPR move, then redirect store to use the other register set.
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(MOVVstore [off] {sym} ptr (MOVVfpgp val) mem) => (MOVDstore [off] {sym} ptr val mem)
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(MOVDstore [off] {sym} ptr (MOVVgpfp val) mem) => (MOVVstore [off] {sym} ptr val mem)
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@ -2329,6 +2329,23 @@ func rewriteValueLOONG64_OpLOONG64MOVBUload(v *Value) bool {
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v_0 := v.Args[0]
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b := v.Block
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config := b.Func.Config
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// match: (MOVBUload [off] {sym} ptr (MOVBstore [off] {sym} ptr x _))
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// result: (MOVBUreg x)
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for {
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off := auxIntToInt32(v.AuxInt)
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sym := auxToSym(v.Aux)
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ptr := v_0
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if v_1.Op != OpLOONG64MOVBstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym {
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break
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}
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x := v_1.Args[1]
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if ptr != v_1.Args[0] {
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break
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}
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v.reset(OpLOONG64MOVBUreg)
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v.AddArg(x)
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return true
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}
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// match: (MOVBUload [off1] {sym} (ADDVconst [off2] ptr) mem)
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// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
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// result: (MOVBUload [off1+int32(off2)] {sym} ptr mem)
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@ -2606,6 +2623,23 @@ func rewriteValueLOONG64_OpLOONG64MOVBload(v *Value) bool {
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v_0 := v.Args[0]
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b := v.Block
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config := b.Func.Config
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// match: (MOVBload [off] {sym} ptr (MOVBstore [off] {sym} ptr x _))
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// result: (MOVBreg x)
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for {
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off := auxIntToInt32(v.AuxInt)
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sym := auxToSym(v.Aux)
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ptr := v_0
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if v_1.Op != OpLOONG64MOVBstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym {
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break
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}
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x := v_1.Args[1]
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if ptr != v_1.Args[0] {
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break
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}
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v.reset(OpLOONG64MOVBreg)
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v.AddArg(x)
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return true
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}
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// match: (MOVBload [off1] {sym} (ADDVconst [off2] ptr) mem)
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// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
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// result: (MOVBload [off1+int32(off2)] {sym} ptr mem)
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@ -3526,6 +3560,23 @@ func rewriteValueLOONG64_OpLOONG64MOVHUload(v *Value) bool {
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v_0 := v.Args[0]
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b := v.Block
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config := b.Func.Config
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// match: (MOVHUload [off] {sym} ptr (MOVHstore [off] {sym} ptr x _))
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// result: (MOVHUreg x)
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for {
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off := auxIntToInt32(v.AuxInt)
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sym := auxToSym(v.Aux)
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ptr := v_0
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if v_1.Op != OpLOONG64MOVHstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym {
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break
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}
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x := v_1.Args[1]
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if ptr != v_1.Args[0] {
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break
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}
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v.reset(OpLOONG64MOVHUreg)
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v.AddArg(x)
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return true
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}
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// match: (MOVHUload [off1] {sym} (ADDVconst [off2] ptr) mem)
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// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
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// result: (MOVHUload [off1+int32(off2)] {sym} ptr mem)
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@ -3765,6 +3816,23 @@ func rewriteValueLOONG64_OpLOONG64MOVHload(v *Value) bool {
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v_0 := v.Args[0]
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b := v.Block
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config := b.Func.Config
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// match: (MOVHload [off] {sym} ptr (MOVHstore [off] {sym} ptr x _))
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// result: (MOVHreg x)
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for {
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off := auxIntToInt32(v.AuxInt)
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sym := auxToSym(v.Aux)
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ptr := v_0
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if v_1.Op != OpLOONG64MOVHstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym {
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break
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}
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x := v_1.Args[1]
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if ptr != v_1.Args[0] {
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break
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}
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v.reset(OpLOONG64MOVHreg)
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v.AddArg(x)
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return true
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}
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// match: (MOVHload [off1] {sym} (ADDVconst [off2] ptr) mem)
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// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
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// result: (MOVHload [off1+int32(off2)] {sym} ptr mem)
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@ -4208,6 +4276,23 @@ func rewriteValueLOONG64_OpLOONG64MOVVload(v *Value) bool {
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v.AddArg(val)
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return true
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}
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// match: (MOVVload [off] {sym} ptr (MOVVstore [off] {sym} ptr x _))
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// result: (MOVVreg x)
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for {
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off := auxIntToInt32(v.AuxInt)
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sym := auxToSym(v.Aux)
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ptr := v_0
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if v_1.Op != OpLOONG64MOVVstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym {
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break
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}
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x := v_1.Args[1]
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if ptr != v_1.Args[0] {
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break
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}
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v.reset(OpLOONG64MOVVreg)
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v.AddArg(x)
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return true
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}
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// match: (MOVVload [off1] {sym} (ADDVconst [off2] ptr) mem)
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// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
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// result: (MOVVload [off1+int32(off2)] {sym} ptr mem)
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@ -4516,6 +4601,23 @@ func rewriteValueLOONG64_OpLOONG64MOVWUload(v *Value) bool {
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v.AddArg(v0)
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return true
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}
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// match: (MOVWUload [off] {sym} ptr (MOVWstore [off] {sym} ptr x _))
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// result: (MOVWUreg x)
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for {
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off := auxIntToInt32(v.AuxInt)
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sym := auxToSym(v.Aux)
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ptr := v_0
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if v_1.Op != OpLOONG64MOVWstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym {
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break
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}
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x := v_1.Args[1]
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if ptr != v_1.Args[0] {
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break
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}
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v.reset(OpLOONG64MOVWUreg)
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v.AddArg(x)
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return true
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}
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// match: (MOVWUload [off1] {sym} (ADDVconst [off2] ptr) mem)
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// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
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// result: (MOVWUload [off1+int32(off2)] {sym} ptr mem)
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@ -4788,6 +4890,23 @@ func rewriteValueLOONG64_OpLOONG64MOVWload(v *Value) bool {
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v_0 := v.Args[0]
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b := v.Block
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config := b.Func.Config
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// match: (MOVWload [off] {sym} ptr (MOVWstore [off] {sym} ptr x _))
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// result: (MOVWreg x)
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for {
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off := auxIntToInt32(v.AuxInt)
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sym := auxToSym(v.Aux)
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ptr := v_0
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if v_1.Op != OpLOONG64MOVWstore || auxIntToInt32(v_1.AuxInt) != off || auxToSym(v_1.Aux) != sym {
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break
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}
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x := v_1.Args[1]
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if ptr != v_1.Args[0] {
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break
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}
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v.reset(OpLOONG64MOVWreg)
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v.AddArg(x)
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return true
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}
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// match: (MOVWload [off1] {sym} (ADDVconst [off2] ptr) mem)
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// cond: is32Bit(int64(off1)+off2) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink)
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// result: (MOVWload [off1+int32(off2)] {sym} ptr mem)
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