mirror of
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[dev.simd] cmd/compile: add fused mul add sub ops
This CL is generated by CL 680595. Change-Id: I5e06ea9bc6a62593fc3b00fd44c119a5ed0d9e90 Reviewed-on: https://go-review.googlesource.com/c/go/+/681299 Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
This commit is contained in:
Junyang Shao
parent
ded6e0ac71
commit
ca01eab9c7
8 changed files with 10046 additions and 2 deletions
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@ -679,7 +679,115 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPCMPBMasked512:
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p = simdFp2k1k1Imm8(s, v)
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case ssa.OpAMD64VPDPWSSD128,
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case ssa.OpAMD64VFMADD132PS512,
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ssa.OpAMD64VFMADD132PS128,
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ssa.OpAMD64VFMADD132PS256,
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ssa.OpAMD64VFMADD132PD128,
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ssa.OpAMD64VFMADD132PD256,
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ssa.OpAMD64VFMADD132PD512,
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ssa.OpAMD64VFMADD213PS512,
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ssa.OpAMD64VFMADD213PS128,
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ssa.OpAMD64VFMADD213PS256,
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ssa.OpAMD64VFMADD213PD128,
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ssa.OpAMD64VFMADD213PD256,
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ssa.OpAMD64VFMADD213PD512,
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ssa.OpAMD64VFMADD231PS512,
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ssa.OpAMD64VFMADD231PS128,
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ssa.OpAMD64VFMADD231PS256,
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ssa.OpAMD64VFMADD231PD128,
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ssa.OpAMD64VFMADD231PD256,
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ssa.OpAMD64VFMADD231PD512,
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ssa.OpAMD64VFMADDSUB132PS512,
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ssa.OpAMD64VFMADDSUB132PS128,
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ssa.OpAMD64VFMADDSUB132PS256,
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ssa.OpAMD64VFMADDSUB132PD128,
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ssa.OpAMD64VFMADDSUB132PD256,
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ssa.OpAMD64VFMADDSUB132PD512,
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ssa.OpAMD64VFMADDSUB213PS512,
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ssa.OpAMD64VFMADDSUB213PS128,
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ssa.OpAMD64VFMADDSUB213PS256,
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ssa.OpAMD64VFMADDSUB213PD128,
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ssa.OpAMD64VFMADDSUB213PD256,
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ssa.OpAMD64VFMADDSUB213PD512,
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ssa.OpAMD64VFMADDSUB231PS512,
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ssa.OpAMD64VFMADDSUB231PS128,
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ssa.OpAMD64VFMADDSUB231PS256,
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ssa.OpAMD64VFMADDSUB231PD128,
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ssa.OpAMD64VFMADDSUB231PD256,
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ssa.OpAMD64VFMADDSUB231PD512,
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ssa.OpAMD64VFMSUB132PS512,
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ssa.OpAMD64VFMSUB132PS128,
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ssa.OpAMD64VFMSUB132PS256,
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ssa.OpAMD64VFMSUB132PD128,
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ssa.OpAMD64VFMSUB132PD256,
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ssa.OpAMD64VFMSUB132PD512,
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ssa.OpAMD64VFMSUB213PS512,
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ssa.OpAMD64VFMSUB213PS128,
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ssa.OpAMD64VFMSUB213PS256,
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ssa.OpAMD64VFMSUB213PD128,
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ssa.OpAMD64VFMSUB213PD256,
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ssa.OpAMD64VFMSUB213PD512,
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ssa.OpAMD64VFMSUB231PS512,
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ssa.OpAMD64VFMSUB231PS128,
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ssa.OpAMD64VFMSUB231PS256,
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ssa.OpAMD64VFMSUB231PD128,
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ssa.OpAMD64VFMSUB231PD256,
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ssa.OpAMD64VFMSUB231PD512,
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ssa.OpAMD64VFMSUBADD132PS512,
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ssa.OpAMD64VFMSUBADD132PS128,
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ssa.OpAMD64VFMSUBADD132PS256,
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ssa.OpAMD64VFMSUBADD132PD128,
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ssa.OpAMD64VFMSUBADD132PD256,
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ssa.OpAMD64VFMSUBADD132PD512,
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ssa.OpAMD64VFMSUBADD213PS512,
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ssa.OpAMD64VFMSUBADD213PS128,
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ssa.OpAMD64VFMSUBADD213PS256,
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ssa.OpAMD64VFMSUBADD213PD128,
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ssa.OpAMD64VFMSUBADD213PD256,
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ssa.OpAMD64VFMSUBADD213PD512,
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ssa.OpAMD64VFMSUBADD231PS512,
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ssa.OpAMD64VFMSUBADD231PS128,
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ssa.OpAMD64VFMSUBADD231PS256,
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ssa.OpAMD64VFMSUBADD231PD128,
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ssa.OpAMD64VFMSUBADD231PD256,
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ssa.OpAMD64VFMSUBADD231PD512,
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ssa.OpAMD64VFNMADD132PS512,
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ssa.OpAMD64VFNMADD132PS128,
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ssa.OpAMD64VFNMADD132PS256,
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ssa.OpAMD64VFNMADD132PD128,
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ssa.OpAMD64VFNMADD132PD256,
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ssa.OpAMD64VFNMADD132PD512,
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ssa.OpAMD64VFNMADD213PS512,
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ssa.OpAMD64VFNMADD213PS128,
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ssa.OpAMD64VFNMADD213PS256,
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ssa.OpAMD64VFNMADD213PD128,
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ssa.OpAMD64VFNMADD213PD256,
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ssa.OpAMD64VFNMADD213PD512,
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ssa.OpAMD64VFNMADD231PS512,
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ssa.OpAMD64VFNMADD231PS128,
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ssa.OpAMD64VFNMADD231PS256,
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ssa.OpAMD64VFNMADD231PD128,
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ssa.OpAMD64VFNMADD231PD256,
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ssa.OpAMD64VFNMADD231PD512,
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ssa.OpAMD64VFNMSUB132PS512,
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ssa.OpAMD64VFNMSUB132PS128,
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ssa.OpAMD64VFNMSUB132PS256,
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ssa.OpAMD64VFNMSUB132PD128,
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ssa.OpAMD64VFNMSUB132PD256,
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ssa.OpAMD64VFNMSUB132PD512,
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ssa.OpAMD64VFNMSUB213PS512,
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ssa.OpAMD64VFNMSUB213PS128,
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ssa.OpAMD64VFNMSUB213PS256,
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ssa.OpAMD64VFNMSUB213PD128,
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ssa.OpAMD64VFNMSUB213PD256,
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ssa.OpAMD64VFNMSUB213PD512,
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ssa.OpAMD64VFNMSUB231PS512,
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ssa.OpAMD64VFNMSUB231PS128,
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ssa.OpAMD64VFNMSUB231PS256,
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ssa.OpAMD64VFNMSUB231PD128,
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ssa.OpAMD64VFNMSUB231PD256,
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ssa.OpAMD64VFNMSUB231PD512,
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ssa.OpAMD64VPDPWSSD128,
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ssa.OpAMD64VPDPWSSD256,
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ssa.OpAMD64VPDPWSSD512,
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ssa.OpAMD64VPDPWSSDS128,
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@ -693,7 +801,115 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPDPBUSD512:
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p = simdFp31ResultInArg0(s, v)
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case ssa.OpAMD64VPDPWSSDMasked512,
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case ssa.OpAMD64VFMADD132PSMasked512,
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ssa.OpAMD64VFMADD132PSMasked128,
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ssa.OpAMD64VFMADD132PSMasked256,
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ssa.OpAMD64VFMADD132PDMasked128,
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ssa.OpAMD64VFMADD132PDMasked256,
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ssa.OpAMD64VFMADD132PDMasked512,
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ssa.OpAMD64VFMADD213PSMasked512,
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ssa.OpAMD64VFMADD213PSMasked128,
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ssa.OpAMD64VFMADD213PSMasked256,
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ssa.OpAMD64VFMADD213PDMasked128,
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ssa.OpAMD64VFMADD213PDMasked256,
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ssa.OpAMD64VFMADD213PDMasked512,
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ssa.OpAMD64VFMADD231PSMasked512,
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ssa.OpAMD64VFMADD231PSMasked128,
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ssa.OpAMD64VFMADD231PSMasked256,
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ssa.OpAMD64VFMADD231PDMasked128,
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ssa.OpAMD64VFMADD231PDMasked256,
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ssa.OpAMD64VFMADD231PDMasked512,
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ssa.OpAMD64VFMADDSUB132PSMasked512,
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ssa.OpAMD64VFMADDSUB132PSMasked128,
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ssa.OpAMD64VFMADDSUB132PSMasked256,
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ssa.OpAMD64VFMADDSUB132PDMasked128,
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ssa.OpAMD64VFMADDSUB132PDMasked256,
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ssa.OpAMD64VFMADDSUB132PDMasked512,
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ssa.OpAMD64VFMADDSUB213PSMasked512,
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ssa.OpAMD64VFMADDSUB213PSMasked128,
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ssa.OpAMD64VFMADDSUB213PSMasked256,
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ssa.OpAMD64VFMADDSUB213PDMasked128,
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ssa.OpAMD64VFMADDSUB213PDMasked256,
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ssa.OpAMD64VFMADDSUB213PDMasked512,
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ssa.OpAMD64VFMADDSUB231PSMasked512,
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ssa.OpAMD64VFMADDSUB231PSMasked128,
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ssa.OpAMD64VFMADDSUB231PSMasked256,
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ssa.OpAMD64VFMADDSUB231PDMasked128,
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ssa.OpAMD64VFMADDSUB231PDMasked256,
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ssa.OpAMD64VFMADDSUB231PDMasked512,
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ssa.OpAMD64VFMSUB132PSMasked512,
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ssa.OpAMD64VFMSUB132PSMasked128,
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ssa.OpAMD64VFMSUB132PSMasked256,
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ssa.OpAMD64VFMSUB132PDMasked128,
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ssa.OpAMD64VFMSUB132PDMasked256,
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ssa.OpAMD64VFMSUB132PDMasked512,
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ssa.OpAMD64VFMSUB213PSMasked512,
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ssa.OpAMD64VFMSUB213PSMasked128,
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ssa.OpAMD64VFMSUB213PSMasked256,
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ssa.OpAMD64VFMSUB213PDMasked128,
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ssa.OpAMD64VFMSUB213PDMasked256,
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ssa.OpAMD64VFMSUB213PDMasked512,
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ssa.OpAMD64VFMSUB231PSMasked512,
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ssa.OpAMD64VFMSUB231PSMasked128,
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ssa.OpAMD64VFMSUB231PSMasked256,
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ssa.OpAMD64VFMSUB231PDMasked128,
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ssa.OpAMD64VFMSUB231PDMasked256,
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ssa.OpAMD64VFMSUB231PDMasked512,
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ssa.OpAMD64VFMSUBADD132PSMasked512,
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ssa.OpAMD64VFMSUBADD132PSMasked128,
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ssa.OpAMD64VFMSUBADD132PSMasked256,
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ssa.OpAMD64VFMSUBADD132PDMasked128,
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ssa.OpAMD64VFMSUBADD132PDMasked256,
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ssa.OpAMD64VFMSUBADD132PDMasked512,
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ssa.OpAMD64VFMSUBADD213PSMasked512,
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ssa.OpAMD64VFMSUBADD213PSMasked128,
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ssa.OpAMD64VFMSUBADD213PSMasked256,
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ssa.OpAMD64VFMSUBADD213PDMasked128,
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ssa.OpAMD64VFMSUBADD213PDMasked256,
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ssa.OpAMD64VFMSUBADD213PDMasked512,
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ssa.OpAMD64VFMSUBADD231PSMasked512,
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ssa.OpAMD64VFMSUBADD231PSMasked128,
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ssa.OpAMD64VFMSUBADD231PSMasked256,
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ssa.OpAMD64VFMSUBADD231PDMasked128,
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ssa.OpAMD64VFMSUBADD231PDMasked256,
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ssa.OpAMD64VFMSUBADD231PDMasked512,
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ssa.OpAMD64VFNMADD132PSMasked512,
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ssa.OpAMD64VFNMADD132PSMasked128,
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ssa.OpAMD64VFNMADD132PSMasked256,
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ssa.OpAMD64VFNMADD132PDMasked128,
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ssa.OpAMD64VFNMADD132PDMasked256,
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ssa.OpAMD64VFNMADD132PDMasked512,
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ssa.OpAMD64VFNMADD213PSMasked512,
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ssa.OpAMD64VFNMADD213PSMasked128,
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ssa.OpAMD64VFNMADD213PSMasked256,
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ssa.OpAMD64VFNMADD213PDMasked128,
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ssa.OpAMD64VFNMADD213PDMasked256,
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ssa.OpAMD64VFNMADD213PDMasked512,
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ssa.OpAMD64VFNMADD231PSMasked512,
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ssa.OpAMD64VFNMADD231PSMasked128,
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ssa.OpAMD64VFNMADD231PSMasked256,
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ssa.OpAMD64VFNMADD231PDMasked128,
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ssa.OpAMD64VFNMADD231PDMasked256,
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ssa.OpAMD64VFNMADD231PDMasked512,
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ssa.OpAMD64VFNMSUB132PSMasked512,
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ssa.OpAMD64VFNMSUB132PSMasked128,
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ssa.OpAMD64VFNMSUB132PSMasked256,
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ssa.OpAMD64VFNMSUB132PDMasked128,
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ssa.OpAMD64VFNMSUB132PDMasked256,
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ssa.OpAMD64VFNMSUB132PDMasked512,
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ssa.OpAMD64VFNMSUB213PSMasked512,
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ssa.OpAMD64VFNMSUB213PSMasked128,
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ssa.OpAMD64VFNMSUB213PSMasked256,
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ssa.OpAMD64VFNMSUB213PDMasked128,
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ssa.OpAMD64VFNMSUB213PDMasked256,
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ssa.OpAMD64VFNMSUB213PDMasked512,
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ssa.OpAMD64VFNMSUB231PSMasked512,
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ssa.OpAMD64VFNMSUB231PSMasked128,
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ssa.OpAMD64VFNMSUB231PSMasked256,
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ssa.OpAMD64VFNMSUB231PDMasked128,
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ssa.OpAMD64VFNMSUB231PDMasked256,
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ssa.OpAMD64VFNMSUB231PDMasked512,
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ssa.OpAMD64VPDPWSSDMasked512,
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ssa.OpAMD64VPDPWSSDMasked128,
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ssa.OpAMD64VPDPWSSDMasked256,
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ssa.OpAMD64VPDPWSSDSMasked512,
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@ -804,6 +1020,114 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VDIVPDMasked128,
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ssa.OpAMD64VDIVPDMasked256,
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ssa.OpAMD64VDIVPDMasked512,
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ssa.OpAMD64VFMADD132PSMasked512,
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ssa.OpAMD64VFMADD132PSMasked128,
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ssa.OpAMD64VFMADD132PSMasked256,
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ssa.OpAMD64VFMADD132PDMasked128,
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ssa.OpAMD64VFMADD132PDMasked256,
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ssa.OpAMD64VFMADD132PDMasked512,
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ssa.OpAMD64VFMADD213PSMasked512,
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ssa.OpAMD64VFMADD213PSMasked128,
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ssa.OpAMD64VFMADD213PSMasked256,
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ssa.OpAMD64VFMADD213PDMasked128,
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ssa.OpAMD64VFMADD213PDMasked256,
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ssa.OpAMD64VFMADD213PDMasked512,
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ssa.OpAMD64VFMADD231PSMasked512,
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ssa.OpAMD64VFMADD231PSMasked128,
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ssa.OpAMD64VFMADD231PSMasked256,
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ssa.OpAMD64VFMADD231PDMasked128,
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ssa.OpAMD64VFMADD231PDMasked256,
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ssa.OpAMD64VFMADD231PDMasked512,
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ssa.OpAMD64VFMADDSUB132PSMasked512,
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ssa.OpAMD64VFMADDSUB132PSMasked128,
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ssa.OpAMD64VFMADDSUB132PSMasked256,
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ssa.OpAMD64VFMADDSUB132PDMasked128,
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ssa.OpAMD64VFMADDSUB132PDMasked256,
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ssa.OpAMD64VFMADDSUB132PDMasked512,
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ssa.OpAMD64VFMADDSUB213PSMasked512,
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ssa.OpAMD64VFMADDSUB213PSMasked128,
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ssa.OpAMD64VFMADDSUB213PSMasked256,
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ssa.OpAMD64VFMADDSUB213PDMasked128,
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ssa.OpAMD64VFMADDSUB213PDMasked256,
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ssa.OpAMD64VFMADDSUB213PDMasked512,
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ssa.OpAMD64VFMADDSUB231PSMasked512,
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ssa.OpAMD64VFMADDSUB231PSMasked128,
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ssa.OpAMD64VFMADDSUB231PSMasked256,
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ssa.OpAMD64VFMADDSUB231PDMasked128,
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ssa.OpAMD64VFMADDSUB231PDMasked256,
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ssa.OpAMD64VFMADDSUB231PDMasked512,
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ssa.OpAMD64VFMSUB132PSMasked512,
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ssa.OpAMD64VFMSUB132PSMasked128,
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ssa.OpAMD64VFMSUB132PSMasked256,
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ssa.OpAMD64VFMSUB132PDMasked128,
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ssa.OpAMD64VFMSUB132PDMasked256,
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ssa.OpAMD64VFMSUB132PDMasked512,
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ssa.OpAMD64VFMSUB213PSMasked512,
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ssa.OpAMD64VFMSUB213PSMasked128,
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ssa.OpAMD64VFMSUB213PSMasked256,
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ssa.OpAMD64VFMSUB213PDMasked128,
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ssa.OpAMD64VFMSUB213PDMasked256,
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ssa.OpAMD64VFMSUB213PDMasked512,
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ssa.OpAMD64VFMSUB231PSMasked512,
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ssa.OpAMD64VFMSUB231PSMasked128,
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ssa.OpAMD64VFMSUB231PSMasked256,
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ssa.OpAMD64VFMSUB231PDMasked128,
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ssa.OpAMD64VFMSUB231PDMasked256,
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ssa.OpAMD64VFMSUB231PDMasked512,
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ssa.OpAMD64VFMSUBADD132PSMasked512,
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ssa.OpAMD64VFMSUBADD132PSMasked128,
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ssa.OpAMD64VFMSUBADD132PSMasked256,
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ssa.OpAMD64VFMSUBADD132PDMasked128,
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ssa.OpAMD64VFMSUBADD132PDMasked256,
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ssa.OpAMD64VFMSUBADD132PDMasked512,
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ssa.OpAMD64VFMSUBADD213PSMasked512,
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ssa.OpAMD64VFMSUBADD213PSMasked128,
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ssa.OpAMD64VFMSUBADD213PSMasked256,
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ssa.OpAMD64VFMSUBADD213PDMasked128,
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ssa.OpAMD64VFMSUBADD213PDMasked256,
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ssa.OpAMD64VFMSUBADD213PDMasked512,
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ssa.OpAMD64VFMSUBADD231PSMasked512,
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ssa.OpAMD64VFMSUBADD231PSMasked128,
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ssa.OpAMD64VFMSUBADD231PSMasked256,
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ssa.OpAMD64VFMSUBADD231PDMasked128,
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ssa.OpAMD64VFMSUBADD231PDMasked256,
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ssa.OpAMD64VFMSUBADD231PDMasked512,
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ssa.OpAMD64VFNMADD132PSMasked512,
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ssa.OpAMD64VFNMADD132PSMasked128,
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ssa.OpAMD64VFNMADD132PSMasked256,
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ssa.OpAMD64VFNMADD132PDMasked128,
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ssa.OpAMD64VFNMADD132PDMasked256,
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ssa.OpAMD64VFNMADD132PDMasked512,
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ssa.OpAMD64VFNMADD213PSMasked512,
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ssa.OpAMD64VFNMADD213PSMasked128,
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ssa.OpAMD64VFNMADD213PSMasked256,
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ssa.OpAMD64VFNMADD213PDMasked128,
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ssa.OpAMD64VFNMADD213PDMasked256,
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ssa.OpAMD64VFNMADD213PDMasked512,
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ssa.OpAMD64VFNMADD231PSMasked512,
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ssa.OpAMD64VFNMADD231PSMasked128,
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ssa.OpAMD64VFNMADD231PSMasked256,
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ssa.OpAMD64VFNMADD231PDMasked128,
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ssa.OpAMD64VFNMADD231PDMasked256,
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ssa.OpAMD64VFNMADD231PDMasked512,
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ssa.OpAMD64VFNMSUB132PSMasked512,
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ssa.OpAMD64VFNMSUB132PSMasked128,
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ssa.OpAMD64VFNMSUB132PSMasked256,
|
||||
ssa.OpAMD64VFNMSUB132PDMasked128,
|
||||
ssa.OpAMD64VFNMSUB132PDMasked256,
|
||||
ssa.OpAMD64VFNMSUB132PDMasked512,
|
||||
ssa.OpAMD64VFNMSUB213PSMasked512,
|
||||
ssa.OpAMD64VFNMSUB213PSMasked128,
|
||||
ssa.OpAMD64VFNMSUB213PSMasked256,
|
||||
ssa.OpAMD64VFNMSUB213PDMasked128,
|
||||
ssa.OpAMD64VFNMSUB213PDMasked256,
|
||||
ssa.OpAMD64VFNMSUB213PDMasked512,
|
||||
ssa.OpAMD64VFNMSUB231PSMasked512,
|
||||
ssa.OpAMD64VFNMSUB231PSMasked128,
|
||||
ssa.OpAMD64VFNMSUB231PSMasked256,
|
||||
ssa.OpAMD64VFNMSUB231PDMasked128,
|
||||
ssa.OpAMD64VFNMSUB231PDMasked256,
|
||||
ssa.OpAMD64VFNMSUB231PDMasked512,
|
||||
ssa.OpAMD64VMAXPSMasked512,
|
||||
ssa.OpAMD64VMAXPSMasked128,
|
||||
ssa.OpAMD64VMAXPSMasked256,
|
||||
|
|
|
|||
|
|
@ -233,6 +233,114 @@
|
|||
(FloorWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+1] x)
|
||||
(FloorWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+1] x)
|
||||
(FloorWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+1] x)
|
||||
(FusedMultiplyAdd132Float32x16 ...) => (VFMADD132PS512 ...)
|
||||
(FusedMultiplyAdd132Float32x4 ...) => (VFMADD132PS128 ...)
|
||||
(FusedMultiplyAdd132Float32x8 ...) => (VFMADD132PS256 ...)
|
||||
(FusedMultiplyAdd132Float64x2 ...) => (VFMADD132PD128 ...)
|
||||
(FusedMultiplyAdd132Float64x4 ...) => (VFMADD132PD256 ...)
|
||||
(FusedMultiplyAdd132Float64x8 ...) => (VFMADD132PD512 ...)
|
||||
(FusedMultiplyAdd213Float32x16 ...) => (VFMADD213PS512 ...)
|
||||
(FusedMultiplyAdd213Float32x4 ...) => (VFMADD213PS128 ...)
|
||||
(FusedMultiplyAdd213Float32x8 ...) => (VFMADD213PS256 ...)
|
||||
(FusedMultiplyAdd213Float64x2 ...) => (VFMADD213PD128 ...)
|
||||
(FusedMultiplyAdd213Float64x4 ...) => (VFMADD213PD256 ...)
|
||||
(FusedMultiplyAdd213Float64x8 ...) => (VFMADD213PD512 ...)
|
||||
(FusedMultiplyAdd231Float32x16 ...) => (VFMADD231PS512 ...)
|
||||
(FusedMultiplyAdd231Float32x4 ...) => (VFMADD231PS128 ...)
|
||||
(FusedMultiplyAdd231Float32x8 ...) => (VFMADD231PS256 ...)
|
||||
(FusedMultiplyAdd231Float64x2 ...) => (VFMADD231PD128 ...)
|
||||
(FusedMultiplyAdd231Float64x4 ...) => (VFMADD231PD256 ...)
|
||||
(FusedMultiplyAdd231Float64x8 ...) => (VFMADD231PD512 ...)
|
||||
(FusedMultiplyAddSub132Float32x16 ...) => (VFMADDSUB132PS512 ...)
|
||||
(FusedMultiplyAddSub132Float32x4 ...) => (VFMADDSUB132PS128 ...)
|
||||
(FusedMultiplyAddSub132Float32x8 ...) => (VFMADDSUB132PS256 ...)
|
||||
(FusedMultiplyAddSub132Float64x2 ...) => (VFMADDSUB132PD128 ...)
|
||||
(FusedMultiplyAddSub132Float64x4 ...) => (VFMADDSUB132PD256 ...)
|
||||
(FusedMultiplyAddSub132Float64x8 ...) => (VFMADDSUB132PD512 ...)
|
||||
(FusedMultiplyAddSub213Float32x16 ...) => (VFMADDSUB213PS512 ...)
|
||||
(FusedMultiplyAddSub213Float32x4 ...) => (VFMADDSUB213PS128 ...)
|
||||
(FusedMultiplyAddSub213Float32x8 ...) => (VFMADDSUB213PS256 ...)
|
||||
(FusedMultiplyAddSub213Float64x2 ...) => (VFMADDSUB213PD128 ...)
|
||||
(FusedMultiplyAddSub213Float64x4 ...) => (VFMADDSUB213PD256 ...)
|
||||
(FusedMultiplyAddSub213Float64x8 ...) => (VFMADDSUB213PD512 ...)
|
||||
(FusedMultiplyAddSub231Float32x16 ...) => (VFMADDSUB231PS512 ...)
|
||||
(FusedMultiplyAddSub231Float32x4 ...) => (VFMADDSUB231PS128 ...)
|
||||
(FusedMultiplyAddSub231Float32x8 ...) => (VFMADDSUB231PS256 ...)
|
||||
(FusedMultiplyAddSub231Float64x2 ...) => (VFMADDSUB231PD128 ...)
|
||||
(FusedMultiplyAddSub231Float64x4 ...) => (VFMADDSUB231PD256 ...)
|
||||
(FusedMultiplyAddSub231Float64x8 ...) => (VFMADDSUB231PD512 ...)
|
||||
(FusedMultiplySub132Float32x16 ...) => (VFMSUB132PS512 ...)
|
||||
(FusedMultiplySub132Float32x4 ...) => (VFMSUB132PS128 ...)
|
||||
(FusedMultiplySub132Float32x8 ...) => (VFMSUB132PS256 ...)
|
||||
(FusedMultiplySub132Float64x2 ...) => (VFMSUB132PD128 ...)
|
||||
(FusedMultiplySub132Float64x4 ...) => (VFMSUB132PD256 ...)
|
||||
(FusedMultiplySub132Float64x8 ...) => (VFMSUB132PD512 ...)
|
||||
(FusedMultiplySub213Float32x16 ...) => (VFMSUB213PS512 ...)
|
||||
(FusedMultiplySub213Float32x4 ...) => (VFMSUB213PS128 ...)
|
||||
(FusedMultiplySub213Float32x8 ...) => (VFMSUB213PS256 ...)
|
||||
(FusedMultiplySub213Float64x2 ...) => (VFMSUB213PD128 ...)
|
||||
(FusedMultiplySub213Float64x4 ...) => (VFMSUB213PD256 ...)
|
||||
(FusedMultiplySub213Float64x8 ...) => (VFMSUB213PD512 ...)
|
||||
(FusedMultiplySub231Float32x16 ...) => (VFMSUB231PS512 ...)
|
||||
(FusedMultiplySub231Float32x4 ...) => (VFMSUB231PS128 ...)
|
||||
(FusedMultiplySub231Float32x8 ...) => (VFMSUB231PS256 ...)
|
||||
(FusedMultiplySub231Float64x2 ...) => (VFMSUB231PD128 ...)
|
||||
(FusedMultiplySub231Float64x4 ...) => (VFMSUB231PD256 ...)
|
||||
(FusedMultiplySub231Float64x8 ...) => (VFMSUB231PD512 ...)
|
||||
(FusedMultiplySubAdd132Float32x16 ...) => (VFMSUBADD132PS512 ...)
|
||||
(FusedMultiplySubAdd132Float32x4 ...) => (VFMSUBADD132PS128 ...)
|
||||
(FusedMultiplySubAdd132Float32x8 ...) => (VFMSUBADD132PS256 ...)
|
||||
(FusedMultiplySubAdd132Float64x2 ...) => (VFMSUBADD132PD128 ...)
|
||||
(FusedMultiplySubAdd132Float64x4 ...) => (VFMSUBADD132PD256 ...)
|
||||
(FusedMultiplySubAdd132Float64x8 ...) => (VFMSUBADD132PD512 ...)
|
||||
(FusedMultiplySubAdd213Float32x16 ...) => (VFMSUBADD213PS512 ...)
|
||||
(FusedMultiplySubAdd213Float32x4 ...) => (VFMSUBADD213PS128 ...)
|
||||
(FusedMultiplySubAdd213Float32x8 ...) => (VFMSUBADD213PS256 ...)
|
||||
(FusedMultiplySubAdd213Float64x2 ...) => (VFMSUBADD213PD128 ...)
|
||||
(FusedMultiplySubAdd213Float64x4 ...) => (VFMSUBADD213PD256 ...)
|
||||
(FusedMultiplySubAdd213Float64x8 ...) => (VFMSUBADD213PD512 ...)
|
||||
(FusedMultiplySubAdd231Float32x16 ...) => (VFMSUBADD231PS512 ...)
|
||||
(FusedMultiplySubAdd231Float32x4 ...) => (VFMSUBADD231PS128 ...)
|
||||
(FusedMultiplySubAdd231Float32x8 ...) => (VFMSUBADD231PS256 ...)
|
||||
(FusedMultiplySubAdd231Float64x2 ...) => (VFMSUBADD231PD128 ...)
|
||||
(FusedMultiplySubAdd231Float64x4 ...) => (VFMSUBADD231PD256 ...)
|
||||
(FusedMultiplySubAdd231Float64x8 ...) => (VFMSUBADD231PD512 ...)
|
||||
(FusedNegativeMultiplyAdd132Float32x16 ...) => (VFNMADD132PS512 ...)
|
||||
(FusedNegativeMultiplyAdd132Float32x4 ...) => (VFNMADD132PS128 ...)
|
||||
(FusedNegativeMultiplyAdd132Float32x8 ...) => (VFNMADD132PS256 ...)
|
||||
(FusedNegativeMultiplyAdd132Float64x2 ...) => (VFNMADD132PD128 ...)
|
||||
(FusedNegativeMultiplyAdd132Float64x4 ...) => (VFNMADD132PD256 ...)
|
||||
(FusedNegativeMultiplyAdd132Float64x8 ...) => (VFNMADD132PD512 ...)
|
||||
(FusedNegativeMultiplyAdd213Float32x16 ...) => (VFNMADD213PS512 ...)
|
||||
(FusedNegativeMultiplyAdd213Float32x4 ...) => (VFNMADD213PS128 ...)
|
||||
(FusedNegativeMultiplyAdd213Float32x8 ...) => (VFNMADD213PS256 ...)
|
||||
(FusedNegativeMultiplyAdd213Float64x2 ...) => (VFNMADD213PD128 ...)
|
||||
(FusedNegativeMultiplyAdd213Float64x4 ...) => (VFNMADD213PD256 ...)
|
||||
(FusedNegativeMultiplyAdd213Float64x8 ...) => (VFNMADD213PD512 ...)
|
||||
(FusedNegativeMultiplyAdd231Float32x16 ...) => (VFNMADD231PS512 ...)
|
||||
(FusedNegativeMultiplyAdd231Float32x4 ...) => (VFNMADD231PS128 ...)
|
||||
(FusedNegativeMultiplyAdd231Float32x8 ...) => (VFNMADD231PS256 ...)
|
||||
(FusedNegativeMultiplyAdd231Float64x2 ...) => (VFNMADD231PD128 ...)
|
||||
(FusedNegativeMultiplyAdd231Float64x4 ...) => (VFNMADD231PD256 ...)
|
||||
(FusedNegativeMultiplyAdd231Float64x8 ...) => (VFNMADD231PD512 ...)
|
||||
(FusedNegativeMultiplySub132Float32x16 ...) => (VFNMSUB132PS512 ...)
|
||||
(FusedNegativeMultiplySub132Float32x4 ...) => (VFNMSUB132PS128 ...)
|
||||
(FusedNegativeMultiplySub132Float32x8 ...) => (VFNMSUB132PS256 ...)
|
||||
(FusedNegativeMultiplySub132Float64x2 ...) => (VFNMSUB132PD128 ...)
|
||||
(FusedNegativeMultiplySub132Float64x4 ...) => (VFNMSUB132PD256 ...)
|
||||
(FusedNegativeMultiplySub132Float64x8 ...) => (VFNMSUB132PD512 ...)
|
||||
(FusedNegativeMultiplySub213Float32x16 ...) => (VFNMSUB213PS512 ...)
|
||||
(FusedNegativeMultiplySub213Float32x4 ...) => (VFNMSUB213PS128 ...)
|
||||
(FusedNegativeMultiplySub213Float32x8 ...) => (VFNMSUB213PS256 ...)
|
||||
(FusedNegativeMultiplySub213Float64x2 ...) => (VFNMSUB213PD128 ...)
|
||||
(FusedNegativeMultiplySub213Float64x4 ...) => (VFNMSUB213PD256 ...)
|
||||
(FusedNegativeMultiplySub213Float64x8 ...) => (VFNMSUB213PD512 ...)
|
||||
(FusedNegativeMultiplySub231Float32x16 ...) => (VFNMSUB231PS512 ...)
|
||||
(FusedNegativeMultiplySub231Float32x4 ...) => (VFNMSUB231PS128 ...)
|
||||
(FusedNegativeMultiplySub231Float32x8 ...) => (VFNMSUB231PS256 ...)
|
||||
(FusedNegativeMultiplySub231Float64x2 ...) => (VFNMSUB231PD128 ...)
|
||||
(FusedNegativeMultiplySub231Float64x4 ...) => (VFNMSUB231PD256 ...)
|
||||
(FusedNegativeMultiplySub231Float64x8 ...) => (VFNMSUB231PD512 ...)
|
||||
(GreaterFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [6] x y))
|
||||
(GreaterFloat32x4 x y) => (VCMPPS128 [6] x y)
|
||||
(GreaterFloat32x8 x y) => (VCMPPS256 [6] x y)
|
||||
|
|
@ -563,6 +671,114 @@
|
|||
(MaskedFloorWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+1] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFloorWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+1] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFloorWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+1] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd132Float32x16 x y z mask) => (VFMADD132PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd132Float32x4 x y z mask) => (VFMADD132PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd132Float32x8 x y z mask) => (VFMADD132PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd132Float64x2 x y z mask) => (VFMADD132PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd132Float64x4 x y z mask) => (VFMADD132PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd132Float64x8 x y z mask) => (VFMADD132PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd213Float32x16 x y z mask) => (VFMADD213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd213Float32x4 x y z mask) => (VFMADD213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd213Float32x8 x y z mask) => (VFMADD213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd213Float64x2 x y z mask) => (VFMADD213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd213Float64x4 x y z mask) => (VFMADD213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd213Float64x8 x y z mask) => (VFMADD213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd231Float32x16 x y z mask) => (VFMADD231PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd231Float32x4 x y z mask) => (VFMADD231PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd231Float32x8 x y z mask) => (VFMADD231PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd231Float64x2 x y z mask) => (VFMADD231PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd231Float64x4 x y z mask) => (VFMADD231PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAdd231Float64x8 x y z mask) => (VFMADD231PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub132Float32x16 x y z mask) => (VFMADDSUB132PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub132Float32x4 x y z mask) => (VFMADDSUB132PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub132Float32x8 x y z mask) => (VFMADDSUB132PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub132Float64x2 x y z mask) => (VFMADDSUB132PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub132Float64x4 x y z mask) => (VFMADDSUB132PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub132Float64x8 x y z mask) => (VFMADDSUB132PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub213Float32x16 x y z mask) => (VFMADDSUB213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub213Float32x4 x y z mask) => (VFMADDSUB213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub213Float32x8 x y z mask) => (VFMADDSUB213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub213Float64x2 x y z mask) => (VFMADDSUB213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub213Float64x4 x y z mask) => (VFMADDSUB213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub213Float64x8 x y z mask) => (VFMADDSUB213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub231Float32x16 x y z mask) => (VFMADDSUB231PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub231Float32x4 x y z mask) => (VFMADDSUB231PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub231Float32x8 x y z mask) => (VFMADDSUB231PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub231Float64x2 x y z mask) => (VFMADDSUB231PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub231Float64x4 x y z mask) => (VFMADDSUB231PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplyAddSub231Float64x8 x y z mask) => (VFMADDSUB231PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub132Float32x16 x y z mask) => (VFMSUB132PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub132Float32x4 x y z mask) => (VFMSUB132PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub132Float32x8 x y z mask) => (VFMSUB132PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub132Float64x2 x y z mask) => (VFMSUB132PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub132Float64x4 x y z mask) => (VFMSUB132PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub132Float64x8 x y z mask) => (VFMSUB132PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub213Float32x16 x y z mask) => (VFMSUB213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub213Float32x4 x y z mask) => (VFMSUB213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub213Float32x8 x y z mask) => (VFMSUB213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub213Float64x2 x y z mask) => (VFMSUB213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub213Float64x4 x y z mask) => (VFMSUB213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub213Float64x8 x y z mask) => (VFMSUB213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub231Float32x16 x y z mask) => (VFMSUB231PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub231Float32x4 x y z mask) => (VFMSUB231PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub231Float32x8 x y z mask) => (VFMSUB231PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub231Float64x2 x y z mask) => (VFMSUB231PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub231Float64x4 x y z mask) => (VFMSUB231PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySub231Float64x8 x y z mask) => (VFMSUB231PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd132Float32x16 x y z mask) => (VFMSUBADD132PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd132Float32x4 x y z mask) => (VFMSUBADD132PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd132Float32x8 x y z mask) => (VFMSUBADD132PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd132Float64x2 x y z mask) => (VFMSUBADD132PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd132Float64x4 x y z mask) => (VFMSUBADD132PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd132Float64x8 x y z mask) => (VFMSUBADD132PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd213Float32x16 x y z mask) => (VFMSUBADD213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd213Float32x4 x y z mask) => (VFMSUBADD213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd213Float32x8 x y z mask) => (VFMSUBADD213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd213Float64x2 x y z mask) => (VFMSUBADD213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd213Float64x4 x y z mask) => (VFMSUBADD213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd213Float64x8 x y z mask) => (VFMSUBADD213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd231Float32x16 x y z mask) => (VFMSUBADD231PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd231Float32x4 x y z mask) => (VFMSUBADD231PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd231Float32x8 x y z mask) => (VFMSUBADD231PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd231Float64x2 x y z mask) => (VFMSUBADD231PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd231Float64x4 x y z mask) => (VFMSUBADD231PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedMultiplySubAdd231Float64x8 x y z mask) => (VFMSUBADD231PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd132Float32x16 x y z mask) => (VFNMADD132PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd132Float32x4 x y z mask) => (VFNMADD132PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd132Float32x8 x y z mask) => (VFNMADD132PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd132Float64x2 x y z mask) => (VFNMADD132PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd132Float64x4 x y z mask) => (VFNMADD132PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd132Float64x8 x y z mask) => (VFNMADD132PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd213Float32x16 x y z mask) => (VFNMADD213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd213Float32x4 x y z mask) => (VFNMADD213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd213Float32x8 x y z mask) => (VFNMADD213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd213Float64x2 x y z mask) => (VFNMADD213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd213Float64x4 x y z mask) => (VFNMADD213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd213Float64x8 x y z mask) => (VFNMADD213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd231Float32x16 x y z mask) => (VFNMADD231PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd231Float32x4 x y z mask) => (VFNMADD231PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd231Float32x8 x y z mask) => (VFNMADD231PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd231Float64x2 x y z mask) => (VFNMADD231PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd231Float64x4 x y z mask) => (VFNMADD231PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplyAdd231Float64x8 x y z mask) => (VFNMADD231PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub132Float32x16 x y z mask) => (VFNMSUB132PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub132Float32x4 x y z mask) => (VFNMSUB132PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub132Float32x8 x y z mask) => (VFNMSUB132PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub132Float64x2 x y z mask) => (VFNMSUB132PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub132Float64x4 x y z mask) => (VFNMSUB132PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub132Float64x8 x y z mask) => (VFNMSUB132PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub213Float32x16 x y z mask) => (VFNMSUB213PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub213Float32x4 x y z mask) => (VFNMSUB213PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub213Float32x8 x y z mask) => (VFNMSUB213PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub213Float64x2 x y z mask) => (VFNMSUB213PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub213Float64x4 x y z mask) => (VFNMSUB213PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub213Float64x8 x y z mask) => (VFNMSUB213PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub231Float32x16 x y z mask) => (VFNMSUB231PSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub231Float32x4 x y z mask) => (VFNMSUB231PSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub231Float32x8 x y z mask) => (VFNMSUB231PSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub231Float64x2 x y z mask) => (VFNMSUB231PDMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub231Float64x4 x y z mask) => (VFNMSUB231PDMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(MaskedFusedNegativeMultiplySub231Float64x8 x y z mask) => (VFNMSUB231PDMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||
(MaskedGreaterFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [6] x y (VPMOVVec32x16ToM <types.TypeMask> mask)))
|
||||
(MaskedGreaterFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [6] x y (VPMOVVec32x4ToM <types.TypeMask> mask)))
|
||||
(MaskedGreaterFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [6] x y (VPMOVVec32x8ToM <types.TypeMask> mask)))
|
||||
|
|
|
|||
|
|
@ -9,12 +9,48 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
|
|||
{name: "VRCP14PS512", argLength: 1, reg: fp11, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VRSQRT14PS512", argLength: 1, reg: fp11, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VDIVPS512", argLength: 2, reg: fp21, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VFMADD132PS512", argLength: 3, reg: fp31, asm: "VFMADD132PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADD213PS512", argLength: 3, reg: fp31, asm: "VFMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADD231PS512", argLength: 3, reg: fp31, asm: "VFMADD231PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADDSUB132PS512", argLength: 3, reg: fp31, asm: "VFMADDSUB132PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADDSUB213PS512", argLength: 3, reg: fp31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADDSUB231PS512", argLength: 3, reg: fp31, asm: "VFMADDSUB231PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUB132PS512", argLength: 3, reg: fp31, asm: "VFMSUB132PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUB213PS512", argLength: 3, reg: fp31, asm: "VFMSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUB231PS512", argLength: 3, reg: fp31, asm: "VFMSUB231PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUBADD132PS512", argLength: 3, reg: fp31, asm: "VFMSUBADD132PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUBADD213PS512", argLength: 3, reg: fp31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUBADD231PS512", argLength: 3, reg: fp31, asm: "VFMSUBADD231PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMADD132PS512", argLength: 3, reg: fp31, asm: "VFNMADD132PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMADD213PS512", argLength: 3, reg: fp31, asm: "VFNMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMADD231PS512", argLength: 3, reg: fp31, asm: "VFNMADD231PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMSUB132PS512", argLength: 3, reg: fp31, asm: "VFNMSUB132PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMSUB213PS512", argLength: 3, reg: fp31, asm: "VFNMSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMSUB231PS512", argLength: 3, reg: fp31, asm: "VFNMSUB231PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VADDPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VANDPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VANDPS", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VANDNPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VANDNPS", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VRCP14PSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VRSQRT14PSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VDIVPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VFMADD132PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD132PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADD213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADD231PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD231PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADDSUB132PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB132PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADDSUB213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADDSUB231PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB231PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUB132PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB132PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUB213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUB231PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB231PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUBADD132PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD132PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUBADD213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUBADD231PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD231PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMADD132PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD132PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMADD213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMADD231PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD231PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMSUB132PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB132PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMSUB213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMSUB231PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB231PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VMAXPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMAXPS", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VMINPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VMULPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
|
|
@ -36,12 +72,48 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
|
|||
{name: "VRCP14PS128", argLength: 1, reg: fp11, asm: "VRCP14PS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VRSQRTPS128", argLength: 1, reg: fp11, asm: "VRSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VDIVPS128", argLength: 2, reg: fp21, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VFMADD132PS128", argLength: 3, reg: fp31, asm: "VFMADD132PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADD213PS128", argLength: 3, reg: fp31, asm: "VFMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADD231PS128", argLength: 3, reg: fp31, asm: "VFMADD231PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADDSUB132PS128", argLength: 3, reg: fp31, asm: "VFMADDSUB132PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADDSUB213PS128", argLength: 3, reg: fp31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADDSUB231PS128", argLength: 3, reg: fp31, asm: "VFMADDSUB231PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUB132PS128", argLength: 3, reg: fp31, asm: "VFMSUB132PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUB213PS128", argLength: 3, reg: fp31, asm: "VFMSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUB231PS128", argLength: 3, reg: fp31, asm: "VFMSUB231PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUBADD132PS128", argLength: 3, reg: fp31, asm: "VFMSUBADD132PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUBADD213PS128", argLength: 3, reg: fp31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUBADD231PS128", argLength: 3, reg: fp31, asm: "VFMSUBADD231PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMADD132PS128", argLength: 3, reg: fp31, asm: "VFNMADD132PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMADD213PS128", argLength: 3, reg: fp31, asm: "VFNMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMADD231PS128", argLength: 3, reg: fp31, asm: "VFNMADD231PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMSUB132PS128", argLength: 3, reg: fp31, asm: "VFNMSUB132PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMSUB213PS128", argLength: 3, reg: fp31, asm: "VFNMSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMSUB231PS128", argLength: 3, reg: fp31, asm: "VFNMSUB231PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VADDPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VADDPS", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VANDPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VANDPS", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VANDNPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VANDNPS", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VRCP14PSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VRSQRT14PSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VDIVPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VFMADD132PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD132PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADD213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADD231PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD231PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADDSUB132PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB132PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADDSUB213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADDSUB231PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB231PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUB132PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB132PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUB213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUB231PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB231PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUBADD132PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD132PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUBADD213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUBADD231PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD231PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMADD132PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD132PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMADD213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMADD231PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD231PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMSUB132PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB132PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMSUB213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMSUB231PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB231PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VMAXPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMAXPS", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VMINPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VMULPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
|
|
@ -65,12 +137,48 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
|
|||
{name: "VRCP14PS256", argLength: 1, reg: fp11, asm: "VRCP14PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VRSQRTPS256", argLength: 1, reg: fp11, asm: "VRSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VDIVPS256", argLength: 2, reg: fp21, asm: "VDIVPS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VFMADD132PS256", argLength: 3, reg: fp31, asm: "VFMADD132PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADD213PS256", argLength: 3, reg: fp31, asm: "VFMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADD231PS256", argLength: 3, reg: fp31, asm: "VFMADD231PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADDSUB132PS256", argLength: 3, reg: fp31, asm: "VFMADDSUB132PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADDSUB213PS256", argLength: 3, reg: fp31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADDSUB231PS256", argLength: 3, reg: fp31, asm: "VFMADDSUB231PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUB132PS256", argLength: 3, reg: fp31, asm: "VFMSUB132PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUB213PS256", argLength: 3, reg: fp31, asm: "VFMSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUB231PS256", argLength: 3, reg: fp31, asm: "VFMSUB231PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUBADD132PS256", argLength: 3, reg: fp31, asm: "VFMSUBADD132PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUBADD213PS256", argLength: 3, reg: fp31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUBADD231PS256", argLength: 3, reg: fp31, asm: "VFMSUBADD231PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMADD132PS256", argLength: 3, reg: fp31, asm: "VFNMADD132PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMADD213PS256", argLength: 3, reg: fp31, asm: "VFNMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMADD231PS256", argLength: 3, reg: fp31, asm: "VFNMADD231PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMSUB132PS256", argLength: 3, reg: fp31, asm: "VFNMSUB132PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMSUB213PS256", argLength: 3, reg: fp31, asm: "VFNMSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMSUB231PS256", argLength: 3, reg: fp31, asm: "VFNMSUB231PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VADDPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VADDPS", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VANDPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VANDPS", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VANDNPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VANDNPS", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VRCP14PSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VRSQRT14PSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VDIVPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VDIVPS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VFMADD132PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD132PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADD213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADD231PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD231PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADDSUB132PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB132PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADDSUB213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADDSUB231PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB231PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUB132PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB132PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUB213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUB231PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB231PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUBADD132PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD132PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUBADD213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUBADD231PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD231PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMADD132PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD132PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMADD213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMADD231PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD231PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMSUB132PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB132PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMSUB213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMSUB231PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB231PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VMAXPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMAXPS", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VMINPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VMULPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
|
|
@ -94,12 +202,48 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
|
|||
{name: "VRCP14PD128", argLength: 1, reg: fp11, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VRSQRT14PD128", argLength: 1, reg: fp11, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VDIVPD128", argLength: 2, reg: fp21, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VFMADD132PD128", argLength: 3, reg: fp31, asm: "VFMADD132PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADD213PD128", argLength: 3, reg: fp31, asm: "VFMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADD231PD128", argLength: 3, reg: fp31, asm: "VFMADD231PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADDSUB132PD128", argLength: 3, reg: fp31, asm: "VFMADDSUB132PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADDSUB213PD128", argLength: 3, reg: fp31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADDSUB231PD128", argLength: 3, reg: fp31, asm: "VFMADDSUB231PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUB132PD128", argLength: 3, reg: fp31, asm: "VFMSUB132PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUB213PD128", argLength: 3, reg: fp31, asm: "VFMSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUB231PD128", argLength: 3, reg: fp31, asm: "VFMSUB231PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUBADD132PD128", argLength: 3, reg: fp31, asm: "VFMSUBADD132PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUBADD213PD128", argLength: 3, reg: fp31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUBADD231PD128", argLength: 3, reg: fp31, asm: "VFMSUBADD231PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMADD132PD128", argLength: 3, reg: fp31, asm: "VFNMADD132PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMADD213PD128", argLength: 3, reg: fp31, asm: "VFNMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMADD231PD128", argLength: 3, reg: fp31, asm: "VFNMADD231PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMSUB132PD128", argLength: 3, reg: fp31, asm: "VFNMSUB132PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMSUB213PD128", argLength: 3, reg: fp31, asm: "VFNMSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMSUB231PD128", argLength: 3, reg: fp31, asm: "VFNMSUB231PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VADDPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VANDPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VANDPD", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VANDNPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VANDNPD", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VRCP14PDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VRSQRT14PDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VDIVPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VFMADD132PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD132PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADD213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADD231PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD231PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADDSUB132PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB132PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADDSUB213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMADDSUB231PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB231PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUB132PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB132PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUB213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUB231PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB231PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUBADD132PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD132PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUBADD213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFMSUBADD231PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD231PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMADD132PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD132PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMADD213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMADD231PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD231PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMSUB132PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB132PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMSUB213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VFNMSUB231PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB231PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VMAXPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMAXPD", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VMINPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VMULPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||
|
|
@ -123,12 +267,48 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
|
|||
{name: "VRCP14PD256", argLength: 1, reg: fp11, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VRSQRT14PD256", argLength: 1, reg: fp11, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VDIVPD256", argLength: 2, reg: fp21, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VFMADD132PD256", argLength: 3, reg: fp31, asm: "VFMADD132PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADD213PD256", argLength: 3, reg: fp31, asm: "VFMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADD231PD256", argLength: 3, reg: fp31, asm: "VFMADD231PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADDSUB132PD256", argLength: 3, reg: fp31, asm: "VFMADDSUB132PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADDSUB213PD256", argLength: 3, reg: fp31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADDSUB231PD256", argLength: 3, reg: fp31, asm: "VFMADDSUB231PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUB132PD256", argLength: 3, reg: fp31, asm: "VFMSUB132PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUB213PD256", argLength: 3, reg: fp31, asm: "VFMSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUB231PD256", argLength: 3, reg: fp31, asm: "VFMSUB231PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUBADD132PD256", argLength: 3, reg: fp31, asm: "VFMSUBADD132PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUBADD213PD256", argLength: 3, reg: fp31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUBADD231PD256", argLength: 3, reg: fp31, asm: "VFMSUBADD231PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMADD132PD256", argLength: 3, reg: fp31, asm: "VFNMADD132PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMADD213PD256", argLength: 3, reg: fp31, asm: "VFNMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMADD231PD256", argLength: 3, reg: fp31, asm: "VFNMADD231PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMSUB132PD256", argLength: 3, reg: fp31, asm: "VFNMSUB132PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMSUB213PD256", argLength: 3, reg: fp31, asm: "VFNMSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMSUB231PD256", argLength: 3, reg: fp31, asm: "VFNMSUB231PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VADDPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VANDPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VANDPD", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VANDNPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VANDNPD", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VRCP14PDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VRSQRT14PDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VDIVPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VFMADD132PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD132PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADD213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADD231PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD231PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADDSUB132PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB132PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADDSUB213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMADDSUB231PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB231PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUB132PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB132PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUB213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUB231PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB231PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUBADD132PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD132PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUBADD213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFMSUBADD231PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD231PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMADD132PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD132PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMADD213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMADD231PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD231PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMSUB132PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB132PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMSUB213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VFNMSUB231PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB231PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VMAXPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMAXPD", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VMINPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VMULPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||
|
|
@ -151,12 +331,48 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
|
|||
{name: "VRCP14PD512", argLength: 1, reg: fp11, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VRSQRT14PD512", argLength: 1, reg: fp11, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VDIVPD512", argLength: 2, reg: fp21, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VFMADD132PD512", argLength: 3, reg: fp31, asm: "VFMADD132PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADD213PD512", argLength: 3, reg: fp31, asm: "VFMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADD231PD512", argLength: 3, reg: fp31, asm: "VFMADD231PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADDSUB132PD512", argLength: 3, reg: fp31, asm: "VFMADDSUB132PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADDSUB213PD512", argLength: 3, reg: fp31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADDSUB231PD512", argLength: 3, reg: fp31, asm: "VFMADDSUB231PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUB132PD512", argLength: 3, reg: fp31, asm: "VFMSUB132PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUB213PD512", argLength: 3, reg: fp31, asm: "VFMSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUB231PD512", argLength: 3, reg: fp31, asm: "VFMSUB231PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUBADD132PD512", argLength: 3, reg: fp31, asm: "VFMSUBADD132PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUBADD213PD512", argLength: 3, reg: fp31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUBADD231PD512", argLength: 3, reg: fp31, asm: "VFMSUBADD231PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMADD132PD512", argLength: 3, reg: fp31, asm: "VFNMADD132PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMADD213PD512", argLength: 3, reg: fp31, asm: "VFNMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMADD231PD512", argLength: 3, reg: fp31, asm: "VFNMADD231PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMSUB132PD512", argLength: 3, reg: fp31, asm: "VFNMSUB132PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMSUB213PD512", argLength: 3, reg: fp31, asm: "VFNMSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMSUB231PD512", argLength: 3, reg: fp31, asm: "VFNMSUB231PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VADDPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VADDPD", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VANDPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VANDPD", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VANDNPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VANDNPD", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VRCP14PDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VRSQRT14PDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VDIVPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VFMADD132PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD132PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADD213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADD231PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD231PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADDSUB132PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB132PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADDSUB213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMADDSUB231PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB231PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUB132PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB132PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUB213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUB231PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB231PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUBADD132PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD132PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUBADD213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFMSUBADD231PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD231PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMADD132PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD132PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMADD213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMADD231PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD231PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMSUB132PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB132PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMSUB213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VFNMSUB231PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB231PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VMAXPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMAXPD", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VMINPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMINPD", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VMULPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMULPD", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||
|
|
|
|||
|
|
@ -10,6 +10,24 @@ func simdGenericOps() []opData {
|
|||
{name: "ApproximateReciprocalOfSqrtFloat32x16", argLength: 1, commutative: false},
|
||||
{name: "DivFloat32x16", argLength: 2, commutative: false},
|
||||
{name: "EqualFloat32x16", argLength: 2, commutative: true},
|
||||
{name: "FusedMultiplyAdd132Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAdd213Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAdd231Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub132Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub213Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub231Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub132Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub213Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub231Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd132Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd213Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd231Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd132Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd213Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd231Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub132Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub213Float32x16", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub231Float32x16", argLength: 3, commutative: false},
|
||||
{name: "GreaterFloat32x16", argLength: 2, commutative: false},
|
||||
{name: "GreaterEqualFloat32x16", argLength: 2, commutative: false},
|
||||
{name: "IsNanFloat32x16", argLength: 2, commutative: true},
|
||||
|
|
@ -22,6 +40,24 @@ func simdGenericOps() []opData {
|
|||
{name: "MaskedApproximateReciprocalOfSqrtFloat32x16", argLength: 2, commutative: false},
|
||||
{name: "MaskedDivFloat32x16", argLength: 3, commutative: false},
|
||||
{name: "MaskedEqualFloat32x16", argLength: 3, commutative: true},
|
||||
{name: "MaskedFusedMultiplyAdd132Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAdd213Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAdd231Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub132Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub213Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub231Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub132Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub213Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub231Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd132Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd213Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd231Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd132Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd213Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd231Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub132Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub213Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub231Float32x16", argLength: 4, commutative: false},
|
||||
{name: "MaskedGreaterFloat32x16", argLength: 3, commutative: false},
|
||||
{name: "MaskedGreaterEqualFloat32x16", argLength: 3, commutative: false},
|
||||
{name: "MaskedIsNanFloat32x16", argLength: 3, commutative: true},
|
||||
|
|
@ -55,6 +91,24 @@ func simdGenericOps() []opData {
|
|||
{name: "DivFloat32x4", argLength: 2, commutative: false},
|
||||
{name: "EqualFloat32x4", argLength: 2, commutative: true},
|
||||
{name: "FloorFloat32x4", argLength: 1, commutative: false},
|
||||
{name: "FusedMultiplyAdd132Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAdd213Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAdd231Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub132Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub213Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub231Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub132Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub213Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub231Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd132Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd213Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd231Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd132Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd213Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd231Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub132Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub213Float32x4", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub231Float32x4", argLength: 3, commutative: false},
|
||||
{name: "GreaterFloat32x4", argLength: 2, commutative: false},
|
||||
{name: "GreaterEqualFloat32x4", argLength: 2, commutative: false},
|
||||
{name: "IsNanFloat32x4", argLength: 2, commutative: true},
|
||||
|
|
@ -67,6 +121,24 @@ func simdGenericOps() []opData {
|
|||
{name: "MaskedApproximateReciprocalOfSqrtFloat32x4", argLength: 2, commutative: false},
|
||||
{name: "MaskedDivFloat32x4", argLength: 3, commutative: false},
|
||||
{name: "MaskedEqualFloat32x4", argLength: 3, commutative: true},
|
||||
{name: "MaskedFusedMultiplyAdd132Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAdd213Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAdd231Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub132Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub213Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub231Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub132Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub213Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub231Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd132Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd213Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd231Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd132Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd213Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd231Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub132Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub213Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub231Float32x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedGreaterFloat32x4", argLength: 3, commutative: false},
|
||||
{name: "MaskedGreaterEqualFloat32x4", argLength: 3, commutative: false},
|
||||
{name: "MaskedIsNanFloat32x4", argLength: 3, commutative: true},
|
||||
|
|
@ -104,6 +176,24 @@ func simdGenericOps() []opData {
|
|||
{name: "DivFloat32x8", argLength: 2, commutative: false},
|
||||
{name: "EqualFloat32x8", argLength: 2, commutative: true},
|
||||
{name: "FloorFloat32x8", argLength: 1, commutative: false},
|
||||
{name: "FusedMultiplyAdd132Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAdd213Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAdd231Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub132Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub213Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub231Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub132Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub213Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub231Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd132Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd213Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd231Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd132Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd213Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd231Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub132Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub213Float32x8", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub231Float32x8", argLength: 3, commutative: false},
|
||||
{name: "GreaterFloat32x8", argLength: 2, commutative: false},
|
||||
{name: "GreaterEqualFloat32x8", argLength: 2, commutative: false},
|
||||
{name: "IsNanFloat32x8", argLength: 2, commutative: true},
|
||||
|
|
@ -116,6 +206,24 @@ func simdGenericOps() []opData {
|
|||
{name: "MaskedApproximateReciprocalOfSqrtFloat32x8", argLength: 2, commutative: false},
|
||||
{name: "MaskedDivFloat32x8", argLength: 3, commutative: false},
|
||||
{name: "MaskedEqualFloat32x8", argLength: 3, commutative: true},
|
||||
{name: "MaskedFusedMultiplyAdd132Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAdd213Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAdd231Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub132Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub213Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub231Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub132Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub213Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub231Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd132Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd213Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd231Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd132Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd213Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd231Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub132Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub213Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub231Float32x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedGreaterFloat32x8", argLength: 3, commutative: false},
|
||||
{name: "MaskedGreaterEqualFloat32x8", argLength: 3, commutative: false},
|
||||
{name: "MaskedIsNanFloat32x8", argLength: 3, commutative: true},
|
||||
|
|
@ -154,6 +262,24 @@ func simdGenericOps() []opData {
|
|||
{name: "DotProdBroadcastFloat64x2", argLength: 2, commutative: true},
|
||||
{name: "EqualFloat64x2", argLength: 2, commutative: true},
|
||||
{name: "FloorFloat64x2", argLength: 1, commutative: false},
|
||||
{name: "FusedMultiplyAdd132Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAdd213Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAdd231Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub132Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub213Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub231Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub132Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub213Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub231Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd132Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd213Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd231Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd132Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd213Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd231Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub132Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub213Float64x2", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub231Float64x2", argLength: 3, commutative: false},
|
||||
{name: "GreaterFloat64x2", argLength: 2, commutative: false},
|
||||
{name: "GreaterEqualFloat64x2", argLength: 2, commutative: false},
|
||||
{name: "IsNanFloat64x2", argLength: 2, commutative: true},
|
||||
|
|
@ -166,6 +292,24 @@ func simdGenericOps() []opData {
|
|||
{name: "MaskedApproximateReciprocalOfSqrtFloat64x2", argLength: 2, commutative: false},
|
||||
{name: "MaskedDivFloat64x2", argLength: 3, commutative: false},
|
||||
{name: "MaskedEqualFloat64x2", argLength: 3, commutative: true},
|
||||
{name: "MaskedFusedMultiplyAdd132Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAdd213Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAdd231Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub132Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub213Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub231Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub132Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub213Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub231Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd132Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd213Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd231Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd132Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd213Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd231Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub132Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub213Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub231Float64x2", argLength: 4, commutative: false},
|
||||
{name: "MaskedGreaterFloat64x2", argLength: 3, commutative: false},
|
||||
{name: "MaskedGreaterEqualFloat64x2", argLength: 3, commutative: false},
|
||||
{name: "MaskedIsNanFloat64x2", argLength: 3, commutative: true},
|
||||
|
|
@ -203,6 +347,24 @@ func simdGenericOps() []opData {
|
|||
{name: "DivFloat64x4", argLength: 2, commutative: false},
|
||||
{name: "EqualFloat64x4", argLength: 2, commutative: true},
|
||||
{name: "FloorFloat64x4", argLength: 1, commutative: false},
|
||||
{name: "FusedMultiplyAdd132Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAdd213Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAdd231Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub132Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub213Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub231Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub132Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub213Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub231Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd132Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd213Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd231Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd132Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd213Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd231Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub132Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub213Float64x4", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub231Float64x4", argLength: 3, commutative: false},
|
||||
{name: "GreaterFloat64x4", argLength: 2, commutative: false},
|
||||
{name: "GreaterEqualFloat64x4", argLength: 2, commutative: false},
|
||||
{name: "IsNanFloat64x4", argLength: 2, commutative: true},
|
||||
|
|
@ -215,6 +377,24 @@ func simdGenericOps() []opData {
|
|||
{name: "MaskedApproximateReciprocalOfSqrtFloat64x4", argLength: 2, commutative: false},
|
||||
{name: "MaskedDivFloat64x4", argLength: 3, commutative: false},
|
||||
{name: "MaskedEqualFloat64x4", argLength: 3, commutative: true},
|
||||
{name: "MaskedFusedMultiplyAdd132Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAdd213Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAdd231Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub132Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub213Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub231Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub132Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub213Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub231Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd132Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd213Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd231Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd132Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd213Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd231Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub132Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub213Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub231Float64x4", argLength: 4, commutative: false},
|
||||
{name: "MaskedGreaterFloat64x4", argLength: 3, commutative: false},
|
||||
{name: "MaskedGreaterEqualFloat64x4", argLength: 3, commutative: false},
|
||||
{name: "MaskedIsNanFloat64x4", argLength: 3, commutative: true},
|
||||
|
|
@ -249,6 +429,24 @@ func simdGenericOps() []opData {
|
|||
{name: "ApproximateReciprocalOfSqrtFloat64x8", argLength: 1, commutative: false},
|
||||
{name: "DivFloat64x8", argLength: 2, commutative: false},
|
||||
{name: "EqualFloat64x8", argLength: 2, commutative: true},
|
||||
{name: "FusedMultiplyAdd132Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAdd213Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAdd231Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub132Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub213Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplyAddSub231Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub132Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub213Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySub231Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd132Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd213Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedMultiplySubAdd231Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd132Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd213Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplyAdd231Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub132Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub213Float64x8", argLength: 3, commutative: false},
|
||||
{name: "FusedNegativeMultiplySub231Float64x8", argLength: 3, commutative: false},
|
||||
{name: "GreaterFloat64x8", argLength: 2, commutative: false},
|
||||
{name: "GreaterEqualFloat64x8", argLength: 2, commutative: false},
|
||||
{name: "IsNanFloat64x8", argLength: 2, commutative: true},
|
||||
|
|
@ -261,6 +459,24 @@ func simdGenericOps() []opData {
|
|||
{name: "MaskedApproximateReciprocalOfSqrtFloat64x8", argLength: 2, commutative: false},
|
||||
{name: "MaskedDivFloat64x8", argLength: 3, commutative: false},
|
||||
{name: "MaskedEqualFloat64x8", argLength: 3, commutative: true},
|
||||
{name: "MaskedFusedMultiplyAdd132Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAdd213Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAdd231Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub132Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub213Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplyAddSub231Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub132Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub213Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySub231Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd132Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd213Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedMultiplySubAdd231Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd132Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd213Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplyAdd231Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub132Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub213Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedFusedNegativeMultiplySub231Float64x8", argLength: 4, commutative: false},
|
||||
{name: "MaskedGreaterFloat64x8", argLength: 3, commutative: false},
|
||||
{name: "MaskedGreaterEqualFloat64x8", argLength: 3, commutative: false},
|
||||
{name: "MaskedIsNanFloat64x8", argLength: 3, commutative: true},
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -665,6 +665,24 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Uint8x64.SaturatedAdd", opLen2(ssa.OpSaturatedAddUint8x64, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Uint8x64.SaturatedSub", opLen2(ssa.OpSaturatedSubUint8x64, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Uint8x64.Sub", opLen2(ssa.OpSubUint8x64, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedMultiplyAdd132", opLen3(ssa.OpFusedMultiplyAdd132Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedMultiplyAdd213", opLen3(ssa.OpFusedMultiplyAdd213Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedMultiplyAdd231", opLen3(ssa.OpFusedMultiplyAdd231Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedMultiplyAddSub132", opLen3(ssa.OpFusedMultiplyAddSub132Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedMultiplyAddSub213", opLen3(ssa.OpFusedMultiplyAddSub213Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedMultiplyAddSub231", opLen3(ssa.OpFusedMultiplyAddSub231Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedMultiplySub132", opLen3(ssa.OpFusedMultiplySub132Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedMultiplySub213", opLen3(ssa.OpFusedMultiplySub213Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedMultiplySub231", opLen3(ssa.OpFusedMultiplySub231Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedMultiplySubAdd132", opLen3(ssa.OpFusedMultiplySubAdd132Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedMultiplySubAdd213", opLen3(ssa.OpFusedMultiplySubAdd213Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedMultiplySubAdd231", opLen3(ssa.OpFusedMultiplySubAdd231Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedNegativeMultiplyAdd132", opLen3(ssa.OpFusedNegativeMultiplyAdd132Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedNegativeMultiplyAdd213", opLen3(ssa.OpFusedNegativeMultiplyAdd213Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedNegativeMultiplyAdd231", opLen3(ssa.OpFusedNegativeMultiplyAdd231Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedNegativeMultiplySub132", opLen3(ssa.OpFusedNegativeMultiplySub132Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedNegativeMultiplySub213", opLen3(ssa.OpFusedNegativeMultiplySub213Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.FusedNegativeMultiplySub231", opLen3(ssa.OpFusedNegativeMultiplySub231Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedAdd", opLen3(ssa.OpMaskedAddFloat32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedAnd", opLen3(ssa.OpMaskedAndFloat32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedAndNot", opLen3(ssa.OpMaskedAndNotFloat32x16, types.TypeVec512), sys.AMD64)
|
||||
|
|
@ -683,6 +701,24 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Float32x16.MaskedOr", opLen3(ssa.OpMaskedOrFloat32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedSub", opLen3(ssa.OpMaskedSubFloat32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedXor", opLen3(ssa.OpMaskedXorFloat32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedMultiplyAdd132", opLen3(ssa.OpFusedMultiplyAdd132Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedMultiplyAdd213", opLen3(ssa.OpFusedMultiplyAdd213Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedMultiplyAdd231", opLen3(ssa.OpFusedMultiplyAdd231Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedMultiplyAddSub132", opLen3(ssa.OpFusedMultiplyAddSub132Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedMultiplyAddSub213", opLen3(ssa.OpFusedMultiplyAddSub213Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedMultiplyAddSub231", opLen3(ssa.OpFusedMultiplyAddSub231Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedMultiplySub132", opLen3(ssa.OpFusedMultiplySub132Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedMultiplySub213", opLen3(ssa.OpFusedMultiplySub213Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedMultiplySub231", opLen3(ssa.OpFusedMultiplySub231Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedMultiplySubAdd132", opLen3(ssa.OpFusedMultiplySubAdd132Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedMultiplySubAdd213", opLen3(ssa.OpFusedMultiplySubAdd213Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedMultiplySubAdd231", opLen3(ssa.OpFusedMultiplySubAdd231Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedNegativeMultiplyAdd132", opLen3(ssa.OpFusedNegativeMultiplyAdd132Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedNegativeMultiplyAdd213", opLen3(ssa.OpFusedNegativeMultiplyAdd213Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedNegativeMultiplyAdd231", opLen3(ssa.OpFusedNegativeMultiplyAdd231Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedNegativeMultiplySub132", opLen3(ssa.OpFusedNegativeMultiplySub132Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedNegativeMultiplySub213", opLen3(ssa.OpFusedNegativeMultiplySub213Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.FusedNegativeMultiplySub231", opLen3(ssa.OpFusedNegativeMultiplySub231Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedAdd", opLen3(ssa.OpMaskedAddFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedAnd", opLen3(ssa.OpMaskedAndFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedAndNot", opLen3(ssa.OpMaskedAndNotFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
|
|
@ -701,6 +737,24 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Float32x4.MaskedOr", opLen3(ssa.OpMaskedOrFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedSub", opLen3(ssa.OpMaskedSubFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedXor", opLen3(ssa.OpMaskedXorFloat32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedMultiplyAdd132", opLen3(ssa.OpFusedMultiplyAdd132Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedMultiplyAdd213", opLen3(ssa.OpFusedMultiplyAdd213Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedMultiplyAdd231", opLen3(ssa.OpFusedMultiplyAdd231Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedMultiplyAddSub132", opLen3(ssa.OpFusedMultiplyAddSub132Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedMultiplyAddSub213", opLen3(ssa.OpFusedMultiplyAddSub213Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedMultiplyAddSub231", opLen3(ssa.OpFusedMultiplyAddSub231Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedMultiplySub132", opLen3(ssa.OpFusedMultiplySub132Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedMultiplySub213", opLen3(ssa.OpFusedMultiplySub213Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedMultiplySub231", opLen3(ssa.OpFusedMultiplySub231Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedMultiplySubAdd132", opLen3(ssa.OpFusedMultiplySubAdd132Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedMultiplySubAdd213", opLen3(ssa.OpFusedMultiplySubAdd213Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedMultiplySubAdd231", opLen3(ssa.OpFusedMultiplySubAdd231Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedNegativeMultiplyAdd132", opLen3(ssa.OpFusedNegativeMultiplyAdd132Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedNegativeMultiplyAdd213", opLen3(ssa.OpFusedNegativeMultiplyAdd213Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedNegativeMultiplyAdd231", opLen3(ssa.OpFusedNegativeMultiplyAdd231Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedNegativeMultiplySub132", opLen3(ssa.OpFusedNegativeMultiplySub132Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedNegativeMultiplySub213", opLen3(ssa.OpFusedNegativeMultiplySub213Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.FusedNegativeMultiplySub231", opLen3(ssa.OpFusedNegativeMultiplySub231Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedAdd", opLen3(ssa.OpMaskedAddFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedAnd", opLen3(ssa.OpMaskedAndFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedAndNot", opLen3(ssa.OpMaskedAndNotFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
|
|
@ -719,6 +773,24 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Float32x8.MaskedOr", opLen3(ssa.OpMaskedOrFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedSub", opLen3(ssa.OpMaskedSubFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedXor", opLen3(ssa.OpMaskedXorFloat32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedMultiplyAdd132", opLen3(ssa.OpFusedMultiplyAdd132Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedMultiplyAdd213", opLen3(ssa.OpFusedMultiplyAdd213Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedMultiplyAdd231", opLen3(ssa.OpFusedMultiplyAdd231Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedMultiplyAddSub132", opLen3(ssa.OpFusedMultiplyAddSub132Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedMultiplyAddSub213", opLen3(ssa.OpFusedMultiplyAddSub213Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedMultiplyAddSub231", opLen3(ssa.OpFusedMultiplyAddSub231Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedMultiplySub132", opLen3(ssa.OpFusedMultiplySub132Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedMultiplySub213", opLen3(ssa.OpFusedMultiplySub213Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedMultiplySub231", opLen3(ssa.OpFusedMultiplySub231Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedMultiplySubAdd132", opLen3(ssa.OpFusedMultiplySubAdd132Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedMultiplySubAdd213", opLen3(ssa.OpFusedMultiplySubAdd213Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedMultiplySubAdd231", opLen3(ssa.OpFusedMultiplySubAdd231Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedNegativeMultiplyAdd132", opLen3(ssa.OpFusedNegativeMultiplyAdd132Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedNegativeMultiplyAdd213", opLen3(ssa.OpFusedNegativeMultiplyAdd213Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedNegativeMultiplyAdd231", opLen3(ssa.OpFusedNegativeMultiplyAdd231Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedNegativeMultiplySub132", opLen3(ssa.OpFusedNegativeMultiplySub132Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedNegativeMultiplySub213", opLen3(ssa.OpFusedNegativeMultiplySub213Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.FusedNegativeMultiplySub231", opLen3(ssa.OpFusedNegativeMultiplySub231Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedAdd", opLen3(ssa.OpMaskedAddFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedAnd", opLen3(ssa.OpMaskedAndFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedAndNot", opLen3(ssa.OpMaskedAndNotFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
|
|
@ -737,6 +809,24 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Float64x2.MaskedOr", opLen3(ssa.OpMaskedOrFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedSub", opLen3(ssa.OpMaskedSubFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedXor", opLen3(ssa.OpMaskedXorFloat64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedMultiplyAdd132", opLen3(ssa.OpFusedMultiplyAdd132Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedMultiplyAdd213", opLen3(ssa.OpFusedMultiplyAdd213Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedMultiplyAdd231", opLen3(ssa.OpFusedMultiplyAdd231Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedMultiplyAddSub132", opLen3(ssa.OpFusedMultiplyAddSub132Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedMultiplyAddSub213", opLen3(ssa.OpFusedMultiplyAddSub213Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedMultiplyAddSub231", opLen3(ssa.OpFusedMultiplyAddSub231Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedMultiplySub132", opLen3(ssa.OpFusedMultiplySub132Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedMultiplySub213", opLen3(ssa.OpFusedMultiplySub213Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedMultiplySub231", opLen3(ssa.OpFusedMultiplySub231Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedMultiplySubAdd132", opLen3(ssa.OpFusedMultiplySubAdd132Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedMultiplySubAdd213", opLen3(ssa.OpFusedMultiplySubAdd213Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedMultiplySubAdd231", opLen3(ssa.OpFusedMultiplySubAdd231Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedNegativeMultiplyAdd132", opLen3(ssa.OpFusedNegativeMultiplyAdd132Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedNegativeMultiplyAdd213", opLen3(ssa.OpFusedNegativeMultiplyAdd213Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedNegativeMultiplyAdd231", opLen3(ssa.OpFusedNegativeMultiplyAdd231Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedNegativeMultiplySub132", opLen3(ssa.OpFusedNegativeMultiplySub132Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedNegativeMultiplySub213", opLen3(ssa.OpFusedNegativeMultiplySub213Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.FusedNegativeMultiplySub231", opLen3(ssa.OpFusedNegativeMultiplySub231Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedAdd", opLen3(ssa.OpMaskedAddFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedAnd", opLen3(ssa.OpMaskedAndFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedAndNot", opLen3(ssa.OpMaskedAndNotFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
|
|
@ -755,6 +845,24 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Float64x4.MaskedOr", opLen3(ssa.OpMaskedOrFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedSub", opLen3(ssa.OpMaskedSubFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedXor", opLen3(ssa.OpMaskedXorFloat64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedMultiplyAdd132", opLen3(ssa.OpFusedMultiplyAdd132Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedMultiplyAdd213", opLen3(ssa.OpFusedMultiplyAdd213Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedMultiplyAdd231", opLen3(ssa.OpFusedMultiplyAdd231Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedMultiplyAddSub132", opLen3(ssa.OpFusedMultiplyAddSub132Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedMultiplyAddSub213", opLen3(ssa.OpFusedMultiplyAddSub213Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedMultiplyAddSub231", opLen3(ssa.OpFusedMultiplyAddSub231Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedMultiplySub132", opLen3(ssa.OpFusedMultiplySub132Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedMultiplySub213", opLen3(ssa.OpFusedMultiplySub213Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedMultiplySub231", opLen3(ssa.OpFusedMultiplySub231Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedMultiplySubAdd132", opLen3(ssa.OpFusedMultiplySubAdd132Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedMultiplySubAdd213", opLen3(ssa.OpFusedMultiplySubAdd213Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedMultiplySubAdd231", opLen3(ssa.OpFusedMultiplySubAdd231Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedNegativeMultiplyAdd132", opLen3(ssa.OpFusedNegativeMultiplyAdd132Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedNegativeMultiplyAdd213", opLen3(ssa.OpFusedNegativeMultiplyAdd213Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedNegativeMultiplyAdd231", opLen3(ssa.OpFusedNegativeMultiplyAdd231Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedNegativeMultiplySub132", opLen3(ssa.OpFusedNegativeMultiplySub132Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedNegativeMultiplySub213", opLen3(ssa.OpFusedNegativeMultiplySub213Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.FusedNegativeMultiplySub231", opLen3(ssa.OpFusedNegativeMultiplySub231Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedAdd", opLen3(ssa.OpMaskedAddFloat64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedAnd", opLen3(ssa.OpMaskedAndFloat64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedAndNot", opLen3(ssa.OpMaskedAndNotFloat64x8, types.TypeVec512), sys.AMD64)
|
||||
|
|
@ -1136,6 +1244,114 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Uint8x64.MaskedSaturatedAdd", opLen3(ssa.OpMaskedSaturatedAddUint8x64, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Uint8x64.MaskedSaturatedSub", opLen3(ssa.OpMaskedSaturatedSubUint8x64, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Uint8x64.MaskedSub", opLen3(ssa.OpMaskedSubUint8x64, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedMultiplyAdd132", opLen4(ssa.OpMaskedFusedMultiplyAdd132Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedMultiplyAdd213", opLen4(ssa.OpMaskedFusedMultiplyAdd213Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedMultiplyAdd231", opLen4(ssa.OpMaskedFusedMultiplyAdd231Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedMultiplyAddSub132", opLen4(ssa.OpMaskedFusedMultiplyAddSub132Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedMultiplyAddSub213", opLen4(ssa.OpMaskedFusedMultiplyAddSub213Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedMultiplyAddSub231", opLen4(ssa.OpMaskedFusedMultiplyAddSub231Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedMultiplySub132", opLen4(ssa.OpMaskedFusedMultiplySub132Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedMultiplySub213", opLen4(ssa.OpMaskedFusedMultiplySub213Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedMultiplySub231", opLen4(ssa.OpMaskedFusedMultiplySub231Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedMultiplySubAdd132", opLen4(ssa.OpMaskedFusedMultiplySubAdd132Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedMultiplySubAdd213", opLen4(ssa.OpMaskedFusedMultiplySubAdd213Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedMultiplySubAdd231", opLen4(ssa.OpMaskedFusedMultiplySubAdd231Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedNegativeMultiplyAdd132", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd132Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedNegativeMultiplyAdd213", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd213Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedNegativeMultiplyAdd231", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd231Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedNegativeMultiplySub132", opLen4(ssa.OpMaskedFusedNegativeMultiplySub132Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedNegativeMultiplySub213", opLen4(ssa.OpMaskedFusedNegativeMultiplySub213Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.MaskedFusedNegativeMultiplySub231", opLen4(ssa.OpMaskedFusedNegativeMultiplySub231Float32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedMultiplyAdd132", opLen4(ssa.OpMaskedFusedMultiplyAdd132Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedMultiplyAdd213", opLen4(ssa.OpMaskedFusedMultiplyAdd213Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedMultiplyAdd231", opLen4(ssa.OpMaskedFusedMultiplyAdd231Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedMultiplyAddSub132", opLen4(ssa.OpMaskedFusedMultiplyAddSub132Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedMultiplyAddSub213", opLen4(ssa.OpMaskedFusedMultiplyAddSub213Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedMultiplyAddSub231", opLen4(ssa.OpMaskedFusedMultiplyAddSub231Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedMultiplySub132", opLen4(ssa.OpMaskedFusedMultiplySub132Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedMultiplySub213", opLen4(ssa.OpMaskedFusedMultiplySub213Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedMultiplySub231", opLen4(ssa.OpMaskedFusedMultiplySub231Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedMultiplySubAdd132", opLen4(ssa.OpMaskedFusedMultiplySubAdd132Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedMultiplySubAdd213", opLen4(ssa.OpMaskedFusedMultiplySubAdd213Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedMultiplySubAdd231", opLen4(ssa.OpMaskedFusedMultiplySubAdd231Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedNegativeMultiplyAdd132", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd132Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedNegativeMultiplyAdd213", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd213Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedNegativeMultiplyAdd231", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd231Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedNegativeMultiplySub132", opLen4(ssa.OpMaskedFusedNegativeMultiplySub132Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedNegativeMultiplySub213", opLen4(ssa.OpMaskedFusedNegativeMultiplySub213Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.MaskedFusedNegativeMultiplySub231", opLen4(ssa.OpMaskedFusedNegativeMultiplySub231Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedMultiplyAdd132", opLen4(ssa.OpMaskedFusedMultiplyAdd132Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedMultiplyAdd213", opLen4(ssa.OpMaskedFusedMultiplyAdd213Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedMultiplyAdd231", opLen4(ssa.OpMaskedFusedMultiplyAdd231Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedMultiplyAddSub132", opLen4(ssa.OpMaskedFusedMultiplyAddSub132Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedMultiplyAddSub213", opLen4(ssa.OpMaskedFusedMultiplyAddSub213Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedMultiplyAddSub231", opLen4(ssa.OpMaskedFusedMultiplyAddSub231Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedMultiplySub132", opLen4(ssa.OpMaskedFusedMultiplySub132Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedMultiplySub213", opLen4(ssa.OpMaskedFusedMultiplySub213Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedMultiplySub231", opLen4(ssa.OpMaskedFusedMultiplySub231Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedMultiplySubAdd132", opLen4(ssa.OpMaskedFusedMultiplySubAdd132Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedMultiplySubAdd213", opLen4(ssa.OpMaskedFusedMultiplySubAdd213Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedMultiplySubAdd231", opLen4(ssa.OpMaskedFusedMultiplySubAdd231Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedNegativeMultiplyAdd132", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd132Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedNegativeMultiplyAdd213", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd213Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedNegativeMultiplyAdd231", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd231Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedNegativeMultiplySub132", opLen4(ssa.OpMaskedFusedNegativeMultiplySub132Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedNegativeMultiplySub213", opLen4(ssa.OpMaskedFusedNegativeMultiplySub213Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.MaskedFusedNegativeMultiplySub231", opLen4(ssa.OpMaskedFusedNegativeMultiplySub231Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedMultiplyAdd132", opLen4(ssa.OpMaskedFusedMultiplyAdd132Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedMultiplyAdd213", opLen4(ssa.OpMaskedFusedMultiplyAdd213Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedMultiplyAdd231", opLen4(ssa.OpMaskedFusedMultiplyAdd231Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedMultiplyAddSub132", opLen4(ssa.OpMaskedFusedMultiplyAddSub132Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedMultiplyAddSub213", opLen4(ssa.OpMaskedFusedMultiplyAddSub213Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedMultiplyAddSub231", opLen4(ssa.OpMaskedFusedMultiplyAddSub231Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedMultiplySub132", opLen4(ssa.OpMaskedFusedMultiplySub132Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedMultiplySub213", opLen4(ssa.OpMaskedFusedMultiplySub213Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedMultiplySub231", opLen4(ssa.OpMaskedFusedMultiplySub231Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedMultiplySubAdd132", opLen4(ssa.OpMaskedFusedMultiplySubAdd132Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedMultiplySubAdd213", opLen4(ssa.OpMaskedFusedMultiplySubAdd213Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedMultiplySubAdd231", opLen4(ssa.OpMaskedFusedMultiplySubAdd231Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedNegativeMultiplyAdd132", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd132Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedNegativeMultiplyAdd213", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd213Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedNegativeMultiplyAdd231", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd231Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedNegativeMultiplySub132", opLen4(ssa.OpMaskedFusedNegativeMultiplySub132Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedNegativeMultiplySub213", opLen4(ssa.OpMaskedFusedNegativeMultiplySub213Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x2.MaskedFusedNegativeMultiplySub231", opLen4(ssa.OpMaskedFusedNegativeMultiplySub231Float64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedMultiplyAdd132", opLen4(ssa.OpMaskedFusedMultiplyAdd132Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedMultiplyAdd213", opLen4(ssa.OpMaskedFusedMultiplyAdd213Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedMultiplyAdd231", opLen4(ssa.OpMaskedFusedMultiplyAdd231Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedMultiplyAddSub132", opLen4(ssa.OpMaskedFusedMultiplyAddSub132Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedMultiplyAddSub213", opLen4(ssa.OpMaskedFusedMultiplyAddSub213Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedMultiplyAddSub231", opLen4(ssa.OpMaskedFusedMultiplyAddSub231Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedMultiplySub132", opLen4(ssa.OpMaskedFusedMultiplySub132Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedMultiplySub213", opLen4(ssa.OpMaskedFusedMultiplySub213Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedMultiplySub231", opLen4(ssa.OpMaskedFusedMultiplySub231Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedMultiplySubAdd132", opLen4(ssa.OpMaskedFusedMultiplySubAdd132Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedMultiplySubAdd213", opLen4(ssa.OpMaskedFusedMultiplySubAdd213Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedMultiplySubAdd231", opLen4(ssa.OpMaskedFusedMultiplySubAdd231Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedNegativeMultiplyAdd132", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd132Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedNegativeMultiplyAdd213", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd213Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedNegativeMultiplyAdd231", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd231Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedNegativeMultiplySub132", opLen4(ssa.OpMaskedFusedNegativeMultiplySub132Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedNegativeMultiplySub213", opLen4(ssa.OpMaskedFusedNegativeMultiplySub213Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x4.MaskedFusedNegativeMultiplySub231", opLen4(ssa.OpMaskedFusedNegativeMultiplySub231Float64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedMultiplyAdd132", opLen4(ssa.OpMaskedFusedMultiplyAdd132Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedMultiplyAdd213", opLen4(ssa.OpMaskedFusedMultiplyAdd213Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedMultiplyAdd231", opLen4(ssa.OpMaskedFusedMultiplyAdd231Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedMultiplyAddSub132", opLen4(ssa.OpMaskedFusedMultiplyAddSub132Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedMultiplyAddSub213", opLen4(ssa.OpMaskedFusedMultiplyAddSub213Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedMultiplyAddSub231", opLen4(ssa.OpMaskedFusedMultiplyAddSub231Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedMultiplySub132", opLen4(ssa.OpMaskedFusedMultiplySub132Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedMultiplySub213", opLen4(ssa.OpMaskedFusedMultiplySub213Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedMultiplySub231", opLen4(ssa.OpMaskedFusedMultiplySub231Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedMultiplySubAdd132", opLen4(ssa.OpMaskedFusedMultiplySubAdd132Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedMultiplySubAdd213", opLen4(ssa.OpMaskedFusedMultiplySubAdd213Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedMultiplySubAdd231", opLen4(ssa.OpMaskedFusedMultiplySubAdd231Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedNegativeMultiplyAdd132", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd132Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedNegativeMultiplyAdd213", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd213Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedNegativeMultiplyAdd231", opLen4(ssa.OpMaskedFusedNegativeMultiplyAdd231Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedNegativeMultiplySub132", opLen4(ssa.OpMaskedFusedNegativeMultiplySub132Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedNegativeMultiplySub213", opLen4(ssa.OpMaskedFusedNegativeMultiplySub213Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float64x8.MaskedFusedNegativeMultiplySub231", opLen4(ssa.OpMaskedFusedNegativeMultiplySub231Float64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Int32x16.MaskedPairDotProdAccumulate", opLen4(ssa.OpMaskedPairDotProdAccumulateInt32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Int32x16.MaskedSaturatedPairDotProdAccumulate", opLen4(ssa.OpMaskedSaturatedPairDotProdAccumulateInt32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Int32x16.MaskedSaturatedUnsignedSignedQuadDotProdAccumulate", opLen4(ssa.OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16, types.TypeVec512), sys.AMD64)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Loading…
Add table
Add a link
Reference in a new issue