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cmd/internal/obj/loong64: add [X]VLDREPL.{B/H/W/D} instructions support
Go asm syntax: VMOVQ offset(Rj), Vd.<T> XVMOVQ offset(Rj), Xd.<T> <T> can have the following values: B16, H8, W4, V2, B32, H16, W8, V4 Change-Id: I44af51d58bb62649d3fe360b3abb771565e78a8a Reviewed-on: https://go-review.googlesource.com/c/go/+/682895 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Freeman <mark@golang.org>
This commit is contained in:
Xiaolin Zhao
abner chenc
parent
d6beda863e
commit
d44749b65b
3 changed files with 104 additions and 34 deletions
10
src/cmd/asm/internal/asm/testdata/loong64enc1.s
vendored
10
src/cmd/asm/internal/asm/testdata/loong64enc1.s
vendored
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@ -510,6 +510,16 @@ lable2:
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VMOVQ V3.W[1], V7.W4 // 67e4f772
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VMOVQ V4.V[0], V6.V2 // 86f0f772
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// Load data from memory and broadcast to each element of a vector register: VMOVQ offset(Rj), <Vd>.<T>
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VMOVQ (R4), V0.B16 // 80008030
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VMOVQ 1(R4), V1.H8 // 81044030
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VMOVQ 2(R4), V2.W4 // 82082030
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VMOVQ 3(R4), V3.V2 // 830c1030
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XVMOVQ (R4), X0.B32 // 80008032
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XVMOVQ 1(R4), X1.H16 // 81044032
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XVMOVQ 2(R4), X2.W8 // 82082032
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XVMOVQ 3(R4), X3.V4 // 830c1032
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// VSEQ{B,H,W,V}, XVSEQ{B,H,W,V} instruction
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VSEQB V1, V2, V3 // 43040070
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VSEQH V1, V2, V3 // 43840070
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@ -416,8 +416,11 @@ var optab = []Optab{
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{AVMOVQ, C_ELEM, C_NONE, C_NONE, C_ARNG, C_NONE, 45, 4, 0, 0},
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{APRELD, C_SOREG, C_U5CON, C_NONE, C_NONE, C_NONE, 46, 4, 0, 0},
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{APRELDX, C_SOREG, C_DCON, C_U5CON, C_NONE, C_NONE, 47, 20, 0, 0},
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{AVMOVQ, C_SOREG, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
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{AXVMOVQ, C_SOREG, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
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{APRELD, C_SOREG, C_U5CON, C_NONE, C_NONE, C_NONE, 47, 4, 0, 0},
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{APRELDX, C_SOREG, C_DCON, C_U5CON, C_NONE, C_NONE, 48, 20, 0, 0},
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{obj.APCALIGN, C_U12CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
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{obj.APCDATA, C_32CON, C_NONE, C_NONE, C_32CON, C_NONE, 0, 0, 0, 0},
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@ -2395,7 +2398,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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o1 = uint32(c.regoff(&p.From))
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case 39: // vmov Rn, Vd.<T>[index]
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v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
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v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
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if v == 0 {
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c.ctxt.Diag("illegal arng type combination: %v\n", p)
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}
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@ -2407,7 +2410,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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o1 = v | (index << 10) | (Rj << 5) | Vd
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case 40: // vmov Vd.<T>[index], Rn
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v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
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v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
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if v == 0 {
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c.ctxt.Diag("illegal arng type combination: %v\n", p)
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}
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@ -2419,7 +2422,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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o1 = v | (index << 10) | (Vj << 5) | Rd
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case 41: // vmov Rn, Vd.<T>
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v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
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v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
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if v == 0 {
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c.ctxt.Diag("illegal arng type combination: %v\n", p)
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}
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@ -2429,7 +2432,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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o1 = v | (Rj << 5) | Vd
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case 42: // vmov xj, xd.<T>
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v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
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v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
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if v == 0 {
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c.ctxt.Diag("illegal arng type combination: %v\n", p)
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}
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@ -2439,7 +2442,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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o1 = v | (Xj << 5) | Xd
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case 43: // vmov xj, xd.<T>[index]
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v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
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v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
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if v == 0 {
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c.ctxt.Diag("illegal arng type combination: %v\n", p)
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}
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@ -2451,7 +2454,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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o1 = v | (index << 10) | (Xj << 5) | Xd
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case 44: // vmov xj.<T>[index], xd
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v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
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v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
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if v == 0 {
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c.ctxt.Diag("illegal arng type combination: %v\n", p)
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}
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@ -2463,7 +2466,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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o1 = v | (index << 10) | (Xj << 5) | Xd
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case 45: // vmov vj.<T>[index], vd.<T>
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v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg)
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v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
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if v == 0 {
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c.ctxt.Diag("illegal arng type combination: %v\n", p)
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}
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@ -2474,12 +2477,23 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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c.checkindex(p, index, m)
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o1 = v | (index << 10) | (vj << 5) | vd
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case 46: // preld offset(Rbase), $hint
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case 46: // vmov offset(vj), vd.<T>
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v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, true)
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if v == 0 {
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c.ctxt.Diag("illegal arng type combination: %v\n", p)
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}
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si := c.regoff(&p.From)
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Rj := uint32(p.From.Reg & EXT_REG_MASK)
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Vd := uint32(p.To.Reg & EXT_REG_MASK)
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o1 = v | uint32(si<<10) | (Rj << 5) | Vd
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case 47: // preld offset(Rbase), $hint
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offs := c.regoff(&p.From)
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hint := p.GetFrom3().Offset
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o1 = OP_12IR_5I(c.opiir(p.As), uint32(offs), uint32(p.From.Reg), uint32(hint))
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case 47: // preldx offset(Rbase), $n, $hint
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case 48: // preldx offset(Rbase), $n, $hint
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offs := c.regoff(&p.From)
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hint := p.RestArgs[1].Offset
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n := uint64(p.GetFrom3().Offset)
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@ -4192,7 +4206,7 @@ func (c *ctxt0) specialFpMovInst(a obj.As, fclass int, tclass int) uint32 {
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return 0
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}
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func (c *ctxt0) specialLsxMovInst(a obj.As, fReg, tReg int16) (op_code, index_mask uint32) {
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func (c *ctxt0) specialLsxMovInst(a obj.As, fReg, tReg int16, offset_flag bool) (op_code, index_mask uint32) {
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farng := (fReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
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tarng := (tReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
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fclass := c.rclass(fReg)
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@ -4258,29 +4272,58 @@ func (c *ctxt0) specialLsxMovInst(a obj.As, fReg, tReg int16) (op_code, index_ma
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}
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case C_REG | (C_ARNG << 16):
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// vmov Rn, Vd.<T>
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switch a {
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case AVMOVQ:
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switch tarng {
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case ARNG_16B:
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return (0x1CA7C0 << 10), 0x0 // vreplgr2vr.b
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case ARNG_8H:
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return (0x1CA7C1 << 10), 0x0 // vreplgr2vr.h
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case ARNG_4W:
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return (0x1CA7C2 << 10), 0x0 // vreplgr2vr.w
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case ARNG_2V:
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return (0x1CA7C3 << 10), 0x0 // vreplgr2vr.d
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switch {
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case offset_flag:
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// vmov offset(vj), vd.<T>
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switch a {
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case AVMOVQ:
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switch tarng {
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case ARNG_16B:
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return (0xC2 << 22), 0x0 // vldrepl.b
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case ARNG_8H:
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return (0x182 << 21), 0x0 // vldrepl.h
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case ARNG_4W:
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return (0x302 << 20), 0x0 // vldrepl.w
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case ARNG_2V:
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return (0x602 << 19), 0x0 // vldrepl.d
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}
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case AXVMOVQ:
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switch tarng {
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case ARNG_32B:
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return (0xCA << 22), 0x0 // xvldrepl.b
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case ARNG_16H:
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return (0x192 << 21), 0x0 // xvldrepl.h
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case ARNG_8W:
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return (0x322 << 20), 0x0 // xvldrepl.w
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case ARNG_4V:
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return (0x642 << 19), 0x0 // xvldrepl.d
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}
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}
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case AXVMOVQ:
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switch tarng {
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case ARNG_32B:
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return (0x1DA7C0 << 10), 0x0 // xvreplgr2vr.b
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case ARNG_16H:
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return (0x1DA7C1 << 10), 0x0 // xvreplgr2vr.h
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case ARNG_8W:
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return (0x1DA7C2 << 10), 0x0 // xvreplgr2vr.w
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case ARNG_4V:
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return (0x1DA7C3 << 10), 0x0 // xvreplgr2vr.d
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default:
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// vmov Rn, Vd.<T>
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switch a {
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case AVMOVQ:
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switch tarng {
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case ARNG_16B:
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return (0x1CA7C0 << 10), 0x0 // vreplgr2vr.b
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case ARNG_8H:
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return (0x1CA7C1 << 10), 0x0 // vreplgr2vr.h
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case ARNG_4W:
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return (0x1CA7C2 << 10), 0x0 // vreplgr2vr.w
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case ARNG_2V:
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return (0x1CA7C3 << 10), 0x0 // vreplgr2vr.d
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}
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case AXVMOVQ:
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switch tarng {
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case ARNG_32B:
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return (0x1DA7C0 << 10), 0x0 // xvreplgr2vr.b
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case ARNG_16H:
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return (0x1DA7C1 << 10), 0x0 // xvreplgr2vr.h
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case ARNG_8W:
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return (0x1DA7C2 << 10), 0x0 // xvreplgr2vr.w
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case ARNG_4V:
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return (0x1DA7C3 << 10), 0x0 // xvreplgr2vr.d
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}
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}
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}
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@ -203,6 +203,23 @@ Note: In the following sections 3.1 to 3.6, "ui4" (4-bit unsigned int immediate)
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VMOVQ Vj.W[index], Vd.W4 | vreplvei.w vd, vj, ui2 | for i in range(4) : VR[vd].w[i] = VR[vj].w[ui2]
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VMOVQ Vj.V[index], Vd.V2 | vreplvei.d vd, vj, ui1 | for i in range(2) : VR[vd].d[i] = VR[vj].d[ui1]
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3.7 Load data from memory and broadcast to each element of a vector register.
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Instruction format:
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VMOVQ offset(Rj), <Vd>.<T>
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Mapping between Go and platform assembly:
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Go assembly | platform assembly | semantics
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-------------------------------------------------------------------------------------------------------------------------------------------------------
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VMOVQ offset(Rj), Vd.B16 | vldrepl.b Vd, Rj, si12 | for i in range(16): VR[vd].b[i] = load 8 bit memory data from (GR[rj]+SignExtend(si12))
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VMOVQ offset(Rj), Vd.H8 | vldrepl.h Vd, Rj, si11 | for i in range(8) : VR[vd].h[i] = load 16 bit memory data from (GR[rj]+SignExtend(si11<<1))
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VMOVQ offset(Rj), Vd.W4 | vldrepl.w Vd, Rj, si10 | for i in range(4) : VR[vd].w[i] = load 32 bit memory data from (GR[rj]+SignExtend(si10<<2))
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VMOVQ offset(Rj), Vd.V2 | vldrepl.d Vd, Rj, si9 | for i in range(2) : VR[vd].d[i] = load 64 bit memory data from (GR[rj]+SignExtend(si9<<3))
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XVMOVQ offset(Rj), Xd.B32 | xvldrepl.b Xd, Rj, si12 | for i in range(32): XR[xd].b[i] = load 8 bit memory data from (GR[rj]+SignExtend(si12))
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XVMOVQ offset(Rj), Xd.H16 | xvldrepl.h Xd, Rj, si11 | for i in range(16): XR[xd].h[i] = load 16 bit memory data from (GR[rj]+SignExtend(si11<<1))
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XVMOVQ offset(Rj), Xd.W8 | xvldrepl.w Xd, Rj, si10 | for i in range(8) : XR[xd].w[i] = load 32 bit memory data from (GR[rj]+SignExtend(si10<<2))
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XVMOVQ offset(Rj), Xd.V4 | xvldrepl.d Xd, Rj, si9 | for i in range(4) : XR[xd].d[i] = load 64 bit memory data from (GR[rj]+SignExtend(si9<<3))
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# Special instruction encoding definition and description on LoongArch
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1. DBAR hint encoding for LA664(Loongson 3A6000) and later micro-architectures, paraphrased
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