mirror of
https://github.com/golang/go.git
synced 2025-12-08 06:10:04 +00:00
[dev.simd] simd, cmd/compile: add int -> fp conversions
Change-Id: Iadfa2dd982d7156d60fb6977ed9afb7894d6e8a0 Reviewed-on: https://go-review.googlesource.com/c/go/+/724321 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Junyang Shao
parent
86cd9b5c90
commit
d6564ed088
11 changed files with 4317 additions and 27 deletions
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@ -42,6 +42,28 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPBROADCASTW512,
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ssa.OpAMD64VPBROADCASTD512,
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ssa.OpAMD64VPBROADCASTQ512,
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ssa.OpAMD64VCVTDQ2PS128,
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ssa.OpAMD64VCVTDQ2PS256,
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ssa.OpAMD64VCVTDQ2PS512,
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ssa.OpAMD64VCVTQQ2PSX128,
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ssa.OpAMD64VCVTQQ2PSY128,
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ssa.OpAMD64VCVTQQ2PS256,
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ssa.OpAMD64VCVTUDQ2PS128,
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ssa.OpAMD64VCVTUDQ2PS256,
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ssa.OpAMD64VCVTUDQ2PS512,
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ssa.OpAMD64VCVTUQQ2PSX128,
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ssa.OpAMD64VCVTUQQ2PSY128,
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ssa.OpAMD64VCVTUQQ2PS256,
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ssa.OpAMD64VCVTDQ2PD256,
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ssa.OpAMD64VCVTDQ2PD512,
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ssa.OpAMD64VCVTQQ2PD128,
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ssa.OpAMD64VCVTQQ2PD256,
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ssa.OpAMD64VCVTQQ2PD512,
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ssa.OpAMD64VCVTUDQ2PD256,
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ssa.OpAMD64VCVTUDQ2PD512,
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ssa.OpAMD64VCVTUQQ2PD128,
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ssa.OpAMD64VCVTUQQ2PD256,
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ssa.OpAMD64VCVTUQQ2PD512,
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ssa.OpAMD64VCVTTPS2DQ128,
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ssa.OpAMD64VCVTTPS2DQ256,
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ssa.OpAMD64VCVTTPS2DQ512,
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@ -832,6 +854,28 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPCOMPRESSQMasked128,
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ssa.OpAMD64VPCOMPRESSQMasked256,
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ssa.OpAMD64VPCOMPRESSQMasked512,
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ssa.OpAMD64VCVTDQ2PSMasked128,
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ssa.OpAMD64VCVTDQ2PSMasked256,
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ssa.OpAMD64VCVTDQ2PSMasked512,
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ssa.OpAMD64VCVTQQ2PSXMasked128,
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ssa.OpAMD64VCVTQQ2PSYMasked128,
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ssa.OpAMD64VCVTQQ2PSMasked256,
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ssa.OpAMD64VCVTUDQ2PSMasked128,
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ssa.OpAMD64VCVTUDQ2PSMasked256,
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ssa.OpAMD64VCVTUDQ2PSMasked512,
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ssa.OpAMD64VCVTUQQ2PSXMasked128,
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ssa.OpAMD64VCVTUQQ2PSYMasked128,
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ssa.OpAMD64VCVTUQQ2PSMasked256,
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ssa.OpAMD64VCVTDQ2PDMasked256,
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ssa.OpAMD64VCVTDQ2PDMasked512,
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ssa.OpAMD64VCVTQQ2PDMasked128,
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ssa.OpAMD64VCVTQQ2PDMasked256,
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ssa.OpAMD64VCVTQQ2PDMasked512,
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ssa.OpAMD64VCVTUDQ2PDMasked256,
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ssa.OpAMD64VCVTUDQ2PDMasked512,
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ssa.OpAMD64VCVTUQQ2PDMasked128,
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ssa.OpAMD64VCVTUQQ2PDMasked256,
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ssa.OpAMD64VCVTUQQ2PDMasked512,
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ssa.OpAMD64VCVTTPS2DQMasked128,
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ssa.OpAMD64VCVTTPS2DQMasked256,
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ssa.OpAMD64VCVTTPS2DQMasked512,
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@ -1720,6 +1764,28 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPABSQMasked128load,
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ssa.OpAMD64VPABSQMasked256load,
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ssa.OpAMD64VPABSQMasked512load,
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ssa.OpAMD64VCVTDQ2PSMasked128load,
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ssa.OpAMD64VCVTDQ2PSMasked256load,
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ssa.OpAMD64VCVTDQ2PSMasked512load,
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ssa.OpAMD64VCVTQQ2PSXMasked128load,
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ssa.OpAMD64VCVTQQ2PSYMasked128load,
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ssa.OpAMD64VCVTQQ2PSMasked256load,
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ssa.OpAMD64VCVTUDQ2PSMasked128load,
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ssa.OpAMD64VCVTUDQ2PSMasked256load,
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ssa.OpAMD64VCVTUDQ2PSMasked512load,
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ssa.OpAMD64VCVTUQQ2PSXMasked128load,
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ssa.OpAMD64VCVTUQQ2PSYMasked128load,
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ssa.OpAMD64VCVTUQQ2PSMasked256load,
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ssa.OpAMD64VCVTDQ2PDMasked256load,
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ssa.OpAMD64VCVTDQ2PDMasked512load,
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ssa.OpAMD64VCVTQQ2PDMasked128load,
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ssa.OpAMD64VCVTQQ2PDMasked256load,
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ssa.OpAMD64VCVTQQ2PDMasked512load,
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ssa.OpAMD64VCVTUDQ2PDMasked256load,
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ssa.OpAMD64VCVTUDQ2PDMasked512load,
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ssa.OpAMD64VCVTUQQ2PDMasked128load,
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ssa.OpAMD64VCVTUQQ2PDMasked256load,
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ssa.OpAMD64VCVTUQQ2PDMasked512load,
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ssa.OpAMD64VCVTTPS2DQMasked128load,
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ssa.OpAMD64VCVTTPS2DQMasked256load,
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ssa.OpAMD64VCVTTPS2DQMasked512load,
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@ -2124,6 +2190,25 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPABSQ128load,
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ssa.OpAMD64VPABSQ256load,
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ssa.OpAMD64VPABSQ512load,
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ssa.OpAMD64VCVTDQ2PS512load,
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ssa.OpAMD64VCVTQQ2PSX128load,
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ssa.OpAMD64VCVTQQ2PSY128load,
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ssa.OpAMD64VCVTQQ2PS256load,
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ssa.OpAMD64VCVTUDQ2PS128load,
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ssa.OpAMD64VCVTUDQ2PS256load,
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ssa.OpAMD64VCVTUDQ2PS512load,
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ssa.OpAMD64VCVTUQQ2PSX128load,
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ssa.OpAMD64VCVTUQQ2PSY128load,
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ssa.OpAMD64VCVTUQQ2PS256load,
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ssa.OpAMD64VCVTDQ2PD512load,
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ssa.OpAMD64VCVTQQ2PD128load,
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ssa.OpAMD64VCVTQQ2PD256load,
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ssa.OpAMD64VCVTQQ2PD512load,
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ssa.OpAMD64VCVTUDQ2PD256load,
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ssa.OpAMD64VCVTUDQ2PD512load,
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ssa.OpAMD64VCVTUQQ2PD128load,
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ssa.OpAMD64VCVTUQQ2PD256load,
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ssa.OpAMD64VCVTUQQ2PD512load,
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ssa.OpAMD64VCVTTPS2DQ512load,
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ssa.OpAMD64VCVTTPD2DQ256load,
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ssa.OpAMD64VCVTTPS2QQ256load,
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@ -2388,6 +2473,28 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VREDUCEPDMasked128Merging,
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ssa.OpAMD64VREDUCEPDMasked256Merging,
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ssa.OpAMD64VREDUCEPDMasked512Merging,
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ssa.OpAMD64VCVTDQ2PSMasked128Merging,
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ssa.OpAMD64VCVTDQ2PSMasked256Merging,
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ssa.OpAMD64VCVTDQ2PSMasked512Merging,
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ssa.OpAMD64VCVTQQ2PSXMasked128Merging,
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ssa.OpAMD64VCVTQQ2PSYMasked128Merging,
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ssa.OpAMD64VCVTQQ2PSMasked256Merging,
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ssa.OpAMD64VCVTUDQ2PSMasked128Merging,
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ssa.OpAMD64VCVTUDQ2PSMasked256Merging,
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ssa.OpAMD64VCVTUDQ2PSMasked512Merging,
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ssa.OpAMD64VCVTUQQ2PSXMasked128Merging,
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ssa.OpAMD64VCVTUQQ2PSYMasked128Merging,
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ssa.OpAMD64VCVTUQQ2PSMasked256Merging,
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ssa.OpAMD64VCVTDQ2PDMasked256Merging,
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ssa.OpAMD64VCVTDQ2PDMasked512Merging,
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ssa.OpAMD64VCVTQQ2PDMasked128Merging,
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ssa.OpAMD64VCVTQQ2PDMasked256Merging,
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ssa.OpAMD64VCVTQQ2PDMasked512Merging,
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ssa.OpAMD64VCVTUDQ2PDMasked256Merging,
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ssa.OpAMD64VCVTUDQ2PDMasked512Merging,
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ssa.OpAMD64VCVTUQQ2PDMasked128Merging,
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ssa.OpAMD64VCVTUQQ2PDMasked256Merging,
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ssa.OpAMD64VCVTUQQ2PDMasked512Merging,
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ssa.OpAMD64VCVTTPS2DQMasked128Merging,
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ssa.OpAMD64VCVTTPS2DQMasked256Merging,
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ssa.OpAMD64VCVTTPS2DQMasked512Merging,
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@ -2773,6 +2880,50 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPALIGNRMasked256,
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ssa.OpAMD64VPALIGNRMasked512,
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ssa.OpAMD64VPALIGNRMasked128,
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ssa.OpAMD64VCVTDQ2PSMasked128,
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ssa.OpAMD64VCVTDQ2PSMasked128load,
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ssa.OpAMD64VCVTDQ2PSMasked256,
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ssa.OpAMD64VCVTDQ2PSMasked256load,
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ssa.OpAMD64VCVTDQ2PSMasked512,
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ssa.OpAMD64VCVTDQ2PSMasked512load,
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ssa.OpAMD64VCVTQQ2PSXMasked128,
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ssa.OpAMD64VCVTQQ2PSXMasked128load,
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ssa.OpAMD64VCVTQQ2PSYMasked128,
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ssa.OpAMD64VCVTQQ2PSYMasked128load,
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ssa.OpAMD64VCVTQQ2PSMasked256,
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ssa.OpAMD64VCVTQQ2PSMasked256load,
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ssa.OpAMD64VCVTUDQ2PSMasked128,
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ssa.OpAMD64VCVTUDQ2PSMasked128load,
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ssa.OpAMD64VCVTUDQ2PSMasked256,
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ssa.OpAMD64VCVTUDQ2PSMasked256load,
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ssa.OpAMD64VCVTUDQ2PSMasked512,
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ssa.OpAMD64VCVTUDQ2PSMasked512load,
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ssa.OpAMD64VCVTUQQ2PSXMasked128,
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ssa.OpAMD64VCVTUQQ2PSXMasked128load,
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ssa.OpAMD64VCVTUQQ2PSYMasked128,
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ssa.OpAMD64VCVTUQQ2PSYMasked128load,
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ssa.OpAMD64VCVTUQQ2PSMasked256,
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ssa.OpAMD64VCVTUQQ2PSMasked256load,
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ssa.OpAMD64VCVTDQ2PDMasked256,
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ssa.OpAMD64VCVTDQ2PDMasked256load,
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ssa.OpAMD64VCVTDQ2PDMasked512,
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ssa.OpAMD64VCVTDQ2PDMasked512load,
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ssa.OpAMD64VCVTQQ2PDMasked128,
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ssa.OpAMD64VCVTQQ2PDMasked128load,
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ssa.OpAMD64VCVTQQ2PDMasked256,
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ssa.OpAMD64VCVTQQ2PDMasked256load,
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ssa.OpAMD64VCVTQQ2PDMasked512,
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ssa.OpAMD64VCVTQQ2PDMasked512load,
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ssa.OpAMD64VCVTUDQ2PDMasked256,
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ssa.OpAMD64VCVTUDQ2PDMasked256load,
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ssa.OpAMD64VCVTUDQ2PDMasked512,
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ssa.OpAMD64VCVTUDQ2PDMasked512load,
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ssa.OpAMD64VCVTUQQ2PDMasked128,
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ssa.OpAMD64VCVTUQQ2PDMasked128load,
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ssa.OpAMD64VCVTUQQ2PDMasked256,
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ssa.OpAMD64VCVTUQQ2PDMasked256load,
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ssa.OpAMD64VCVTUQQ2PDMasked512,
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ssa.OpAMD64VCVTUQQ2PDMasked512load,
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ssa.OpAMD64VCVTTPS2DQMasked128,
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ssa.OpAMD64VCVTTPS2DQMasked128load,
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ssa.OpAMD64VCVTTPS2DQMasked256,
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@ -249,6 +249,28 @@
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(ConcatShiftBytesRightUint8x16 ...) => (VPALIGNR128 ...)
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(ConcatShiftBytesRightGroupedUint8x32 ...) => (VPALIGNR256 ...)
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(ConcatShiftBytesRightGroupedUint8x64 ...) => (VPALIGNR512 ...)
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(ConvertToFloat32Int32x4 ...) => (VCVTDQ2PS128 ...)
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(ConvertToFloat32Int32x8 ...) => (VCVTDQ2PS256 ...)
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(ConvertToFloat32Int32x16 ...) => (VCVTDQ2PS512 ...)
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(ConvertToFloat32Int64x2 ...) => (VCVTQQ2PSX128 ...)
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(ConvertToFloat32Int64x4 ...) => (VCVTQQ2PSY128 ...)
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(ConvertToFloat32Int64x8 ...) => (VCVTQQ2PS256 ...)
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(ConvertToFloat32Uint32x4 ...) => (VCVTUDQ2PS128 ...)
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(ConvertToFloat32Uint32x8 ...) => (VCVTUDQ2PS256 ...)
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(ConvertToFloat32Uint32x16 ...) => (VCVTUDQ2PS512 ...)
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(ConvertToFloat32Uint64x2 ...) => (VCVTUQQ2PSX128 ...)
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(ConvertToFloat32Uint64x4 ...) => (VCVTUQQ2PSY128 ...)
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(ConvertToFloat32Uint64x8 ...) => (VCVTUQQ2PS256 ...)
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(ConvertToFloat64Int32x4 ...) => (VCVTDQ2PD256 ...)
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(ConvertToFloat64Int32x8 ...) => (VCVTDQ2PD512 ...)
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(ConvertToFloat64Int64x2 ...) => (VCVTQQ2PD128 ...)
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(ConvertToFloat64Int64x4 ...) => (VCVTQQ2PD256 ...)
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(ConvertToFloat64Int64x8 ...) => (VCVTQQ2PD512 ...)
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(ConvertToFloat64Uint32x4 ...) => (VCVTUDQ2PD256 ...)
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(ConvertToFloat64Uint32x8 ...) => (VCVTUDQ2PD512 ...)
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(ConvertToFloat64Uint64x2 ...) => (VCVTUQQ2PD128 ...)
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(ConvertToFloat64Uint64x4 ...) => (VCVTUQQ2PD256 ...)
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(ConvertToFloat64Uint64x8 ...) => (VCVTUQQ2PD512 ...)
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(ConvertToInt32Float32x4 ...) => (VCVTTPS2DQ128 ...)
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(ConvertToInt32Float32x8 ...) => (VCVTTPS2DQ256 ...)
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(ConvertToInt32Float32x16 ...) => (VCVTTPS2DQ512 ...)
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@ -1456,6 +1478,28 @@
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(VMOVDQU8Masked256 (VPALIGNR256 [a] x y) mask) => (VPALIGNRMasked256 [a] x y mask)
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(VMOVDQU8Masked512 (VPALIGNR512 [a] x y) mask) => (VPALIGNRMasked512 [a] x y mask)
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(VMOVDQU8Masked128 (VPALIGNR128 [a] x y) mask) => (VPALIGNRMasked128 [a] x y mask)
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(VMOVDQU32Masked128 (VCVTDQ2PS128 x) mask) => (VCVTDQ2PSMasked128 x mask)
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(VMOVDQU32Masked256 (VCVTDQ2PS256 x) mask) => (VCVTDQ2PSMasked256 x mask)
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(VMOVDQU32Masked512 (VCVTDQ2PS512 x) mask) => (VCVTDQ2PSMasked512 x mask)
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(VMOVDQU64Masked128 (VCVTQQ2PSX128 x) mask) => (VCVTQQ2PSXMasked128 x mask)
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(VMOVDQU64Masked128 (VCVTQQ2PSY128 x) mask) => (VCVTQQ2PSYMasked128 x mask)
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(VMOVDQU64Masked256 (VCVTQQ2PS256 x) mask) => (VCVTQQ2PSMasked256 x mask)
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(VMOVDQU32Masked128 (VCVTUDQ2PS128 x) mask) => (VCVTUDQ2PSMasked128 x mask)
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(VMOVDQU32Masked256 (VCVTUDQ2PS256 x) mask) => (VCVTUDQ2PSMasked256 x mask)
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(VMOVDQU32Masked512 (VCVTUDQ2PS512 x) mask) => (VCVTUDQ2PSMasked512 x mask)
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(VMOVDQU64Masked128 (VCVTUQQ2PSX128 x) mask) => (VCVTUQQ2PSXMasked128 x mask)
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(VMOVDQU64Masked128 (VCVTUQQ2PSY128 x) mask) => (VCVTUQQ2PSYMasked128 x mask)
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(VMOVDQU64Masked256 (VCVTUQQ2PS256 x) mask) => (VCVTUQQ2PSMasked256 x mask)
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(VMOVDQU32Masked256 (VCVTDQ2PD256 x) mask) => (VCVTDQ2PDMasked256 x mask)
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(VMOVDQU32Masked512 (VCVTDQ2PD512 x) mask) => (VCVTDQ2PDMasked512 x mask)
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(VMOVDQU64Masked128 (VCVTQQ2PD128 x) mask) => (VCVTQQ2PDMasked128 x mask)
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(VMOVDQU64Masked256 (VCVTQQ2PD256 x) mask) => (VCVTQQ2PDMasked256 x mask)
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(VMOVDQU64Masked512 (VCVTQQ2PD512 x) mask) => (VCVTQQ2PDMasked512 x mask)
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(VMOVDQU32Masked256 (VCVTUDQ2PD256 x) mask) => (VCVTUDQ2PDMasked256 x mask)
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(VMOVDQU32Masked512 (VCVTUDQ2PD512 x) mask) => (VCVTUDQ2PDMasked512 x mask)
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(VMOVDQU64Masked128 (VCVTUQQ2PD128 x) mask) => (VCVTUQQ2PDMasked128 x mask)
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(VMOVDQU64Masked256 (VCVTUQQ2PD256 x) mask) => (VCVTUQQ2PDMasked256 x mask)
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(VMOVDQU64Masked512 (VCVTUQQ2PD512 x) mask) => (VCVTUQQ2PDMasked512 x mask)
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(VMOVDQU32Masked128 (VCVTTPS2DQ128 x) mask) => (VCVTTPS2DQMasked128 x mask)
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(VMOVDQU32Masked256 (VCVTTPS2DQ256 x) mask) => (VCVTTPS2DQMasked256 x mask)
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(VMOVDQU32Masked512 (VCVTTPS2DQ512 x) mask) => (VCVTTPS2DQMasked512 x mask)
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@ -1939,8 +1983,10 @@
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(VPBLENDMBMasked512 dst (VPSUBSB512 x y) mask) => (VPSUBSBMasked512Merging dst x y mask)
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(VPBLENDMBMasked512 dst (VPSUBUSB512 x y) mask) => (VPSUBUSBMasked512Merging dst x y mask)
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(VPBLENDMDMasked512 dst (VADDPS512 x y) mask) => (VADDPSMasked512Merging dst x y mask)
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(VPBLENDMDMasked512 dst (VCVTDQ2PS512 x) mask) => (VCVTDQ2PSMasked512Merging dst x mask)
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(VPBLENDMDMasked512 dst (VCVTTPS2DQ512 x) mask) => (VCVTTPS2DQMasked512Merging dst x mask)
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(VPBLENDMDMasked512 dst (VCVTTPS2UDQ512 x) mask) => (VCVTTPS2UDQMasked512Merging dst x mask)
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(VPBLENDMDMasked512 dst (VCVTUDQ2PS512 x) mask) => (VCVTUDQ2PSMasked512Merging dst x mask)
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(VPBLENDMDMasked512 dst (VDIVPS512 x y) mask) => (VDIVPSMasked512Merging dst x y mask)
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(VPBLENDMDMasked512 dst (VMAXPS512 x y) mask) => (VMAXPSMasked512Merging dst x y mask)
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(VPBLENDMDMasked512 dst (VMINPS512 x y) mask) => (VMINPSMasked512Merging dst x y mask)
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@ -1985,10 +2031,14 @@
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(VPBLENDMDMasked512 dst (VSQRTPS512 x) mask) => (VSQRTPSMasked512Merging dst x mask)
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(VPBLENDMDMasked512 dst (VSUBPS512 x y) mask) => (VSUBPSMasked512Merging dst x y mask)
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(VPBLENDMQMasked512 dst (VADDPD512 x y) mask) => (VADDPDMasked512Merging dst x y mask)
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(VPBLENDMQMasked512 dst (VCVTQQ2PD512 x) mask) => (VCVTQQ2PDMasked512Merging dst x mask)
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(VPBLENDMQMasked512 dst (VCVTQQ2PS256 x) mask) => (VCVTQQ2PSMasked256Merging dst x mask)
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(VPBLENDMQMasked512 dst (VCVTTPD2DQ256 x) mask) => (VCVTTPD2DQMasked256Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTTPD2QQ512 x) mask) => (VCVTTPD2QQMasked512Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTTPD2UDQ256 x) mask) => (VCVTTPD2UDQMasked256Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTTPD2UQQ512 x) mask) => (VCVTTPD2UQQMasked512Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTUQQ2PD512 x) mask) => (VCVTUQQ2PDMasked512Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VCVTUQQ2PS256 x) mask) => (VCVTUQQ2PSMasked256Merging dst x mask)
|
||||
(VPBLENDMQMasked512 dst (VDIVPD512 x y) mask) => (VDIVPDMasked512Merging dst x y mask)
|
||||
(VPBLENDMQMasked512 dst (VMAXPD512 x y) mask) => (VMAXPDMasked512Merging dst x y mask)
|
||||
(VPBLENDMQMasked512 dst (VMINPD512 x y) mask) => (VMINPDMasked512Merging dst x y mask)
|
||||
|
|
@ -2069,6 +2119,10 @@
|
|||
(VPBLENDVB128 dst (VBROADCASTSS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VBROADCASTSS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VBROADCASTSS512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VBROADCASTSSMasked512Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTDQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTDQ2PS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTQQ2PD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTQQ2PSX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPD2DQX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2DQXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPD2QQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2QQMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPD2UDQX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UDQXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
|
|
@ -2077,6 +2131,10 @@
|
|||
(VPBLENDVB128 dst (VCVTTPS2QQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2QQMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPS2UDQ128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UDQMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTTPS2UQQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UQQMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTUDQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTUDQ2PS128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTUQQ2PD128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VCVTUQQ2PSX128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VDIVPD128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPDMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VDIVPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB128 dst (VGF2P8MULB128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VGF2P8MULBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
|
||||
|
|
@ -2244,6 +2302,10 @@
|
|||
(VPBLENDVB128 dst (VSUBPS128 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VSUBPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VADDPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VADDPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VADDPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTDQ2PD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTDQ2PS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTQQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTQQ2PSY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPD2DQY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2DQYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPD2QQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2QQMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPD2UDQY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPD2UDQYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
|
|
@ -2252,6 +2314,10 @@
|
|||
(VPBLENDVB256 dst (VCVTTPS2QQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2QQMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPS2UDQ256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UDQMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTTPS2UQQ512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTTPS2UQQMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTUDQ2PD512 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTUDQ2PS256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTUQQ2PD256 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VCVTUQQ2PSY128 x) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VCVTUQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VDIVPD256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VDIVPS256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VDIVPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||
(VPBLENDVB256 dst (VGF2P8MULB256 x y) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (VGF2P8MULBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
|
||||
|
|
@ -2475,6 +2541,47 @@
|
|||
(VPERMI2QMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked256load {sym} [off] x y ptr mask mem)
|
||||
(VPERMI2PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2PDMasked512load {sym} [off] x y ptr mask mem)
|
||||
(VPERMI2QMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VPERMI2QMasked512load {sym} [off] x y ptr mask mem)
|
||||
(VCVTDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PS512load {sym} [off] ptr mem)
|
||||
(VCVTQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSX128load {sym} [off] ptr mem)
|
||||
(VCVTQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSY128load {sym} [off] ptr mem)
|
||||
(VCVTQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PS256load {sym} [off] ptr mem)
|
||||
(VCVTUDQ2PS128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PS128load {sym} [off] ptr mem)
|
||||
(VCVTUDQ2PS256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PS256load {sym} [off] ptr mem)
|
||||
(VCVTUDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PS512load {sym} [off] ptr mem)
|
||||
(VCVTUQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSX128load {sym} [off] ptr mem)
|
||||
(VCVTUQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSY128load {sym} [off] ptr mem)
|
||||
(VCVTUQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PS256load {sym} [off] ptr mem)
|
||||
(VCVTDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PSMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PSMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PSMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSXMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSYMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PSMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTUDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PSMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTUDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PSMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTUDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PSMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTUQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSXMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTUQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSYMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTUQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PSMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PD512load {sym} [off] ptr mem)
|
||||
(VCVTQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PD128load {sym} [off] ptr mem)
|
||||
(VCVTQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PD256load {sym} [off] ptr mem)
|
||||
(VCVTQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PD512load {sym} [off] ptr mem)
|
||||
(VCVTUDQ2PD256 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PD256load {sym} [off] ptr mem)
|
||||
(VCVTUDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PD512load {sym} [off] ptr mem)
|
||||
(VCVTUQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PD128load {sym} [off] ptr mem)
|
||||
(VCVTUQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PD256load {sym} [off] ptr mem)
|
||||
(VCVTUQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PD512load {sym} [off] ptr mem)
|
||||
(VCVTDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PDMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTDQ2PDMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PDMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PDMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTQQ2PDMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTUDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PDMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTUDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUDQ2PDMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTUQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PDMasked128load {sym} [off] ptr mask mem)
|
||||
(VCVTUQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PDMasked256load {sym} [off] ptr mask mem)
|
||||
(VCVTUQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTUQQ2PDMasked512load {sym} [off] ptr mask mem)
|
||||
(VCVTTPS2DQ512 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQ512load {sym} [off] ptr mem)
|
||||
(VCVTTPD2DQ256 l:(VMOVDQUload512 {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (VCVTTPD2DQ256load {sym} [off] ptr mem)
|
||||
(VCVTTPS2DQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask) && canMergeLoad(v, l) && clobber(l) => (VCVTTPS2DQMasked128load {sym} [off] ptr mask mem)
|
||||
|
|
|
|||
|
|
@ -56,6 +56,28 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
|||
{name: "VCOMPRESSPSMasked128", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCOMPRESSPSMasked256", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCOMPRESSPSMasked512", argLength: 2, reg: wkw, asm: "VCOMPRESSPS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTDQ2PD256", argLength: 1, reg: v11, asm: "VCVTDQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTDQ2PD512", argLength: 1, reg: w11, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTDQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTDQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTDQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTDQ2PS128", argLength: 1, reg: v11, asm: "VCVTDQ2PS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTDQ2PS256", argLength: 1, reg: v11, asm: "VCVTDQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTDQ2PS512", argLength: 1, reg: w11, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTDQ2PSMasked128", argLength: 2, reg: wkw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTDQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTDQ2PSMasked512", argLength: 2, reg: wkw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTQQ2PD128", argLength: 1, reg: w11, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTQQ2PD256", argLength: 1, reg: w11, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTQQ2PD512", argLength: 1, reg: w11, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTQQ2PDMasked128", argLength: 2, reg: wkw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTQQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTQQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTQQ2PS256", argLength: 1, reg: w11, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSX128", argLength: 1, reg: w11, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSXMasked128", argLength: 2, reg: wkw, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSY128", argLength: 1, reg: w11, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSYMasked128", argLength: 2, reg: wkw, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQ256", argLength: 1, reg: w11, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQX128", argLength: 1, reg: v11, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
|
|
@ -100,6 +122,28 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
|||
{name: "VCVTTPS2UQQ512", argLength: 1, reg: w11, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQMasked256", argLength: 2, reg: wkw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQMasked512", argLength: 2, reg: wkw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PD256", argLength: 1, reg: w11, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PD512", argLength: 1, reg: w11, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PS128", argLength: 1, reg: w11, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PS256", argLength: 1, reg: w11, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PS512", argLength: 1, reg: w11, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PSMasked128", argLength: 2, reg: wkw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PSMasked512", argLength: 2, reg: wkw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PD128", argLength: 1, reg: w11, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PD256", argLength: 1, reg: w11, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PD512", argLength: 1, reg: w11, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PDMasked128", argLength: 2, reg: wkw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PDMasked256", argLength: 2, reg: wkw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PDMasked512", argLength: 2, reg: wkw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PS256", argLength: 1, reg: w11, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSMasked256", argLength: 2, reg: wkw, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSX128", argLength: 1, reg: w11, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSXMasked128", argLength: 2, reg: wkw, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSY128", argLength: 1, reg: w11, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSYMasked128", argLength: 2, reg: wkw, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VDIVPD128", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||
{name: "VDIVPD256", argLength: 2, reg: v21, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||
{name: "VDIVPD512", argLength: 2, reg: w21, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||
|
|
@ -1437,6 +1481,25 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
|||
{name: "VADDPSMasked128load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VADDPSMasked256load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VADDPSMasked512load", argLength: 4, reg: w2kwload, asm: "VADDPS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PS512load", argLength: 2, reg: w11load, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PSMasked128load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTDQ2PSMasked512load", argLength: 3, reg: wkwload, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PD128load", argLength: 2, reg: w11load, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PD256load", argLength: 2, reg: w11load, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PDMasked128load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PS256load", argLength: 2, reg: w11load, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSX128load", argLength: 2, reg: w11load, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSY128load", argLength: 2, reg: w11load, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTQQ2PSYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQ256load", argLength: 2, reg: w11load, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPD2DQXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
|
|
@ -1477,6 +1540,28 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
|||
{name: "VCVTTPS2UQQ512load", argLength: 2, reg: w11load, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQMasked256load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTTPS2UQQMasked512load", argLength: 3, reg: wkwload, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PD256load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PS128load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PS256load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PS512load", argLength: 2, reg: w11load, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PSMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUDQ2PSMasked512load", argLength: 3, reg: wkwload, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PD128load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PD256load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PD512load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PDMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PDMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PDMasked512load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PS256load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSMasked256load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSX128load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSXMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSY128load", argLength: 2, reg: w11load, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VCVTUQQ2PSYMasked128load", argLength: 3, reg: wkwload, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VDIVPD512load", argLength: 3, reg: w21load, asm: "VDIVPD", commutative: false, typ: "Vec512", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VDIVPDMasked128load", argLength: 4, reg: w2kwload, asm: "VDIVPD", commutative: false, typ: "Vec128", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
{name: "VDIVPDMasked256load", argLength: 4, reg: w2kwload, asm: "VDIVPD", commutative: false, typ: "Vec256", aux: "SymOff", symEffect: "Read", resultInArg0: false},
|
||||
|
|
@ -2024,6 +2109,17 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
|||
{name: "VBROADCASTSSMasked128Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VBROADCASTSSMasked256Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VBROADCASTSSMasked512Merging", argLength: 3, reg: w2kw, asm: "VBROADCASTSS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTDQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTDQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTDQ2PSMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTDQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTDQ2PSMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTDQ2PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTQQ2PDMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTQQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTQQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTQQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTQQ2PSXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTQQ2PSYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2DQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPD2DQXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQX", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTTPD2DQYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTTPD2DQY", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
|
|
@ -2046,6 +2142,17 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
|
|||
{name: "VCVTTPS2UDQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UDQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTTPS2UQQMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTTPS2UQQMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTTPS2UQQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTUDQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTUDQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTUDQ2PSMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTUDQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTUDQ2PSMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTUDQ2PS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTUQQ2PDMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTUQQ2PDMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTUQQ2PDMasked512Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
{name: "VCVTUQQ2PSMasked256Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VCVTUQQ2PSXMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PSX", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VCVTUQQ2PSYMasked128Merging", argLength: 3, reg: w2kw, asm: "VCVTUQQ2PSY", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VDIVPDMasked128Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||
{name: "VDIVPDMasked256Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||
{name: "VDIVPDMasked512Merging", argLength: 4, reg: w3kw, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||
|
|
|
|||
|
|
@ -237,6 +237,28 @@ func simdGenericOps() []opData {
|
|||
{name: "ConcatPermuteUint64x2", argLength: 3, commutative: false},
|
||||
{name: "ConcatPermuteUint64x4", argLength: 3, commutative: false},
|
||||
{name: "ConcatPermuteUint64x8", argLength: 3, commutative: false},
|
||||
{name: "ConvertToFloat32Int32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Int32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Int32x16", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Int64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Int64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Int64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Uint32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Uint32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Uint32x16", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Uint64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Uint64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat32Uint64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Int32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Int32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Int64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Int64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Int64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Uint32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Uint32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Uint64x2", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Uint64x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToFloat64Uint64x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float32x4", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float32x8", argLength: 1, commutative: false},
|
||||
{name: "ConvertToInt32Float32x16", argLength: 1, commutative: false},
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -261,6 +261,28 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
|||
addF(simdPackage, "Uint8x16.ConcatShiftBytesRight", opLen2Imm8(ssa.OpConcatShiftBytesRightUint8x16, types.TypeVec128, 0), sys.AMD64)
|
||||
addF(simdPackage, "Uint8x32.ConcatShiftBytesRightGrouped", opLen2Imm8(ssa.OpConcatShiftBytesRightGroupedUint8x32, types.TypeVec256, 0), sys.AMD64)
|
||||
addF(simdPackage, "Uint8x64.ConcatShiftBytesRightGrouped", opLen2Imm8(ssa.OpConcatShiftBytesRightGroupedUint8x64, types.TypeVec512, 0), sys.AMD64)
|
||||
addF(simdPackage, "Int32x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Int32x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Int32x16.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Int64x2.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Int64x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int64x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Int64x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Int64x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Uint32x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Uint32x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Uint32x16.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint32x16, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Uint64x2.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Uint64x4.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint64x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Uint64x8.ConvertToFloat32", opLen1(ssa.OpConvertToFloat32Uint64x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Int32x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int32x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Int32x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int32x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Int64x2.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Int64x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Int64x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Int64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Uint32x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint32x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Uint32x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint32x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Uint64x2.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint64x2, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Uint64x4.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint64x4, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Uint64x8.ConvertToFloat64", opLen1(ssa.OpConvertToFloat64Uint64x8, types.TypeVec512), sys.AMD64)
|
||||
addF(simdPackage, "Float32x4.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x4, types.TypeVec128), sys.AMD64)
|
||||
addF(simdPackage, "Float32x8.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x8, types.TypeVec256), sys.AMD64)
|
||||
addF(simdPackage, "Float32x16.ConvertToInt32", opLen1(ssa.OpConvertToInt32Float32x16, types.TypeVec512), sys.AMD64)
|
||||
|
|
|
|||
|
|
@ -337,7 +337,7 @@ func (op *Operation) sortOperand() {
|
|||
|
||||
// adjustAsm adjusts the asm to make it align with Go's assembler.
|
||||
func (op *Operation) adjustAsm() {
|
||||
if op.Asm == "VCVTTPD2DQ" || op.Asm == "VCVTTPD2UDQ" {
|
||||
if op.Asm == "VCVTTPD2DQ" || op.Asm == "VCVTTPD2UDQ" || op.Asm == "VCVTQQ2PS" || op.Asm == "VCVTUQQ2PS" {
|
||||
switch *op.In[0].Bits {
|
||||
case 128:
|
||||
op.Asm += "X"
|
||||
|
|
|
|||
|
|
@ -6,28 +6,42 @@
|
|||
documentation: !string |-
|
||||
// NAME converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
- go: "ConvertToUint32"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
- go: "ConvertToInt64"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int64, the indefinite value is returned.
|
||||
// If a converted result cannot be represented in int64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
- go: "ConvertToUint64"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
|
||||
// If a converted result cannot be represented in uint64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
- go: "ConvertToFloat32"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to float32.
|
||||
- go: "ConvertToFloat64"
|
||||
commutative: false
|
||||
regexpTag: "convert"
|
||||
documentation: !string |-
|
||||
// NAME converts element values to float64.
|
||||
|
||||
# Int <-> Int conversions
|
||||
- go: "(Extend|Saturate|Truncate)?ToInt8"
|
||||
|
|
|
|||
|
|
@ -66,6 +66,52 @@
|
|||
base: uint
|
||||
elemBits: 64
|
||||
bits: 256|512
|
||||
# int -> float32
|
||||
- go: ConvertToFloat32
|
||||
regexpTag: "convert"
|
||||
asm: "VCVT[DQ]Q2PS"
|
||||
in: &int
|
||||
- go: $i
|
||||
base: int
|
||||
out:
|
||||
- *fp
|
||||
# int -> float64
|
||||
- go: ConvertToFloat64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTQQ2PD"
|
||||
in: *int
|
||||
out:
|
||||
- *fp
|
||||
- go: ConvertToFloat64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTDQ2PD"
|
||||
in: *int
|
||||
out:
|
||||
- base: float
|
||||
bits: 256|512
|
||||
# uint -> float32
|
||||
- go: ConvertToFloat32
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTU[DQ]Q2PS"
|
||||
in: &uint
|
||||
- go: $u
|
||||
base: uint
|
||||
out:
|
||||
- *fp
|
||||
# uint -> float64
|
||||
- go: ConvertToFloat64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTUQQ2PD"
|
||||
in: *uint
|
||||
out:
|
||||
- *fp
|
||||
- go: ConvertToFloat64
|
||||
regexpTag: "convert"
|
||||
asm: "VCVTUDQ2PD"
|
||||
in: *uint
|
||||
out:
|
||||
- base: float
|
||||
bits: 256|512
|
||||
|
||||
# Widening integer conversions.
|
||||
# uint8 -> uint16
|
||||
|
|
|
|||
|
|
@ -1544,46 +1544,166 @@ func (x Uint8x32) ConcatShiftBytesRightGrouped(constant uint8, y Uint8x32) Uint8
|
|||
// Asm: VPALIGNR, CPU Feature: AVX512
|
||||
func (x Uint8x64) ConcatShiftBytesRightGrouped(constant uint8, y Uint8x64) Uint8x64
|
||||
|
||||
/* ConvertToFloat32 */
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTDQ2PS, CPU Feature: AVX
|
||||
func (x Int32x4) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTDQ2PS, CPU Feature: AVX
|
||||
func (x Int32x8) ConvertToFloat32() Float32x8
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTDQ2PS, CPU Feature: AVX512
|
||||
func (x Int32x16) ConvertToFloat32() Float32x16
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTQQ2PSX, CPU Feature: AVX512
|
||||
func (x Int64x2) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTQQ2PSY, CPU Feature: AVX512
|
||||
func (x Int64x4) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTQQ2PS, CPU Feature: AVX512
|
||||
func (x Int64x8) ConvertToFloat32() Float32x8
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTUDQ2PS, CPU Feature: AVX512
|
||||
func (x Uint32x4) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTUDQ2PS, CPU Feature: AVX512
|
||||
func (x Uint32x8) ConvertToFloat32() Float32x8
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTUDQ2PS, CPU Feature: AVX512
|
||||
func (x Uint32x16) ConvertToFloat32() Float32x16
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTUQQ2PSX, CPU Feature: AVX512
|
||||
func (x Uint64x2) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTUQQ2PSY, CPU Feature: AVX512
|
||||
func (x Uint64x4) ConvertToFloat32() Float32x4
|
||||
|
||||
// ConvertToFloat32 converts element values to float32.
|
||||
//
|
||||
// Asm: VCVTUQQ2PS, CPU Feature: AVX512
|
||||
func (x Uint64x8) ConvertToFloat32() Float32x8
|
||||
|
||||
/* ConvertToFloat64 */
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTDQ2PD, CPU Feature: AVX
|
||||
func (x Int32x4) ConvertToFloat64() Float64x4
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTDQ2PD, CPU Feature: AVX512
|
||||
func (x Int32x8) ConvertToFloat64() Float64x8
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTQQ2PD, CPU Feature: AVX512
|
||||
func (x Int64x2) ConvertToFloat64() Float64x2
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTQQ2PD, CPU Feature: AVX512
|
||||
func (x Int64x4) ConvertToFloat64() Float64x4
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTQQ2PD, CPU Feature: AVX512
|
||||
func (x Int64x8) ConvertToFloat64() Float64x8
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTUDQ2PD, CPU Feature: AVX512
|
||||
func (x Uint32x4) ConvertToFloat64() Float64x4
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTUDQ2PD, CPU Feature: AVX512
|
||||
func (x Uint32x8) ConvertToFloat64() Float64x8
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTUQQ2PD, CPU Feature: AVX512
|
||||
func (x Uint64x2) ConvertToFloat64() Float64x2
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTUQQ2PD, CPU Feature: AVX512
|
||||
func (x Uint64x4) ConvertToFloat64() Float64x4
|
||||
|
||||
// ConvertToFloat64 converts element values to float64.
|
||||
//
|
||||
// Asm: VCVTUQQ2PD, CPU Feature: AVX512
|
||||
func (x Uint64x8) ConvertToFloat64() Float64x8
|
||||
|
||||
/* ConvertToInt32 */
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2DQ, CPU Feature: AVX
|
||||
func (x Float32x4) ConvertToInt32() Int32x4
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2DQ, CPU Feature: AVX
|
||||
func (x Float32x8) ConvertToInt32() Int32x8
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2DQ, CPU Feature: AVX512
|
||||
func (x Float32x16) ConvertToInt32() Int32x16
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2DQX, CPU Feature: AVX
|
||||
func (x Float64x2) ConvertToInt32() Int32x4
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2DQY, CPU Feature: AVX
|
||||
func (x Float64x4) ConvertToInt32() Int32x4
|
||||
|
||||
// ConvertToInt32 converts element values to int32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int32, the indefinite value is returned.
|
||||
// If a converted result cannot be represented in int32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2DQ, CPU Feature: AVX512
|
||||
func (x Float64x8) ConvertToInt32() Int32x8
|
||||
|
|
@ -1592,35 +1712,40 @@ func (x Float64x8) ConvertToInt32() Int32x8
|
|||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int64, the indefinite value is returned.
|
||||
// If a converted result cannot be represented in int64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2QQ, CPU Feature: AVX512
|
||||
func (x Float32x4) ConvertToInt64() Int64x4
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int64, the indefinite value is returned.
|
||||
// If a converted result cannot be represented in int64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2QQ, CPU Feature: AVX512
|
||||
func (x Float32x8) ConvertToInt64() Int64x8
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int64, the indefinite value is returned.
|
||||
// If a converted result cannot be represented in int64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2QQ, CPU Feature: AVX512
|
||||
func (x Float64x2) ConvertToInt64() Int64x2
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int64, the indefinite value is returned.
|
||||
// If a converted result cannot be represented in int64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2QQ, CPU Feature: AVX512
|
||||
func (x Float64x4) ConvertToInt64() Int64x4
|
||||
|
||||
// ConvertToInt64 converts element values to int64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum int64, the indefinite value is returned.
|
||||
// If a converted result cannot be represented in int64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2QQ, CPU Feature: AVX512
|
||||
func (x Float64x8) ConvertToInt64() Int64x8
|
||||
|
|
@ -1629,42 +1754,48 @@ func (x Float64x8) ConvertToInt64() Int64x8
|
|||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2UDQ, CPU Feature: AVX512
|
||||
func (x Float32x4) ConvertToUint32() Uint32x4
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2UDQ, CPU Feature: AVX512
|
||||
func (x Float32x8) ConvertToUint32() Uint32x8
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2UDQ, CPU Feature: AVX512
|
||||
func (x Float32x16) ConvertToUint32() Uint32x16
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UDQX, CPU Feature: AVX512
|
||||
func (x Float64x2) ConvertToUint32() Uint32x4
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UDQY, CPU Feature: AVX512
|
||||
func (x Float64x4) ConvertToUint32() Uint32x4
|
||||
|
||||
// ConvertToUint32 converts element values to uint32.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint32, the maximum uint32 value is returned.
|
||||
// If a converted result cannot be represented in uint32, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UDQ, CPU Feature: AVX512
|
||||
func (x Float64x8) ConvertToUint32() Uint32x8
|
||||
|
|
@ -1673,35 +1804,40 @@ func (x Float64x8) ConvertToUint32() Uint32x8
|
|||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
|
||||
// If a converted result cannot be represented in uint64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2UQQ, CPU Feature: AVX512
|
||||
func (x Float32x4) ConvertToUint64() Uint64x4
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
|
||||
// If a converted result cannot be represented in uint64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPS2UQQ, CPU Feature: AVX512
|
||||
func (x Float32x8) ConvertToUint64() Uint64x8
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
|
||||
// If a converted result cannot be represented in uint64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UQQ, CPU Feature: AVX512
|
||||
func (x Float64x2) ConvertToUint64() Uint64x2
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
|
||||
// If a converted result cannot be represented in uint64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UQQ, CPU Feature: AVX512
|
||||
func (x Float64x4) ConvertToUint64() Uint64x4
|
||||
|
||||
// ConvertToUint64 converts element values to uint64.
|
||||
// When a conversion is inexact, a truncated (round toward zero) value is returned.
|
||||
// If a converted result is larger than the maximum uint64, the maximum uint64 value is returned.
|
||||
// If a converted result cannot be represented in uint64, an implementation-defined
|
||||
// architecture-specific value is returned.
|
||||
//
|
||||
// Asm: VCVTTPD2UQQ, CPU Feature: AVX512
|
||||
func (x Float64x8) ConvertToUint64() Uint64x8
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue