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[dev.ssa] cmd/compile, etc.: more ARM64 optimizations, and enable SSA by default
Add more ARM64 optimizations: - use hardware zero register when it is possible. - use shifted ops. The assembler supports shifted ops but not documented, nor knows how to print it. This CL adds them. - enable fast division. This was disabled because it makes the old backend generate slower code. But with SSA it generates faster code. Turn on SSA by default, also adjust tests. Change-Id: I7794479954c83bb65008dcb457bc1e21d7496da6 Reviewed-on: https://go-review.googlesource.com/26950 Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Cherry Zhang
parent
94c8e59ae1
commit
d99cee79b9
17 changed files with 3458 additions and 35 deletions
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@ -859,6 +859,27 @@ const (
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OpARM64CMNWconst
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OpARM64FCMPS
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OpARM64FCMPD
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OpARM64ADDshiftLL
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OpARM64ADDshiftRL
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OpARM64ADDshiftRA
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OpARM64SUBshiftLL
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OpARM64SUBshiftRL
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OpARM64SUBshiftRA
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OpARM64ANDshiftLL
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OpARM64ANDshiftRL
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OpARM64ANDshiftRA
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OpARM64ORshiftLL
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OpARM64ORshiftRL
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OpARM64ORshiftRA
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OpARM64XORshiftLL
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OpARM64XORshiftRL
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OpARM64XORshiftRA
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OpARM64BICshiftLL
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OpARM64BICshiftRL
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OpARM64BICshiftRA
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OpARM64CMPshiftLL
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OpARM64CMPshiftRL
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OpARM64CMPshiftRA
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OpARM64MOVDconst
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OpARM64FMOVSconst
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OpARM64FMOVDconst
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@ -878,6 +899,10 @@ const (
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OpARM64MOVDstore
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OpARM64FMOVSstore
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OpARM64FMOVDstore
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OpARM64MOVBstorezero
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OpARM64MOVHstorezero
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OpARM64MOVWstorezero
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OpARM64MOVDstorezero
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OpARM64MOVBreg
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OpARM64MOVBUreg
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OpARM64MOVHreg
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@ -905,6 +930,7 @@ const (
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OpARM64FCVTSD
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OpARM64FCVTDS
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OpARM64CSELULT
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OpARM64CSELULT0
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OpARM64CALLstatic
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OpARM64CALLclosure
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OpARM64CALLdefer
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@ -10596,6 +10622,312 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "ADDshiftLL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.AADD,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "ADDshiftRL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.AADD,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "ADDshiftRA",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.AADD,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "SUBshiftLL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.ASUB,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "SUBshiftRL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.ASUB,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "SUBshiftRA",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.ASUB,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "ANDshiftLL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.AAND,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "ANDshiftRL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.AAND,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "ANDshiftRA",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.AAND,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "ORshiftLL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.AORR,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "ORshiftRL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.AORR,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "ORshiftRA",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.AORR,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "XORshiftLL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.AEOR,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "XORshiftRL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.AEOR,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "XORshiftRA",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.AEOR,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "BICshiftLL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.ABIC,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "BICshiftRL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.ABIC,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "BICshiftRA",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.ABIC,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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outputs: []outputInfo{
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{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
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},
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},
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},
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{
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name: "CMPshiftLL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.ACMP,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
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},
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},
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},
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{
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name: "CMPshiftRL",
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auxType: auxInt64,
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argLen: 2,
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asm: arm64.ACMP,
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reg: regInfo{
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inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMPshiftRA",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.ACMP,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVDconst",
|
||||
auxType: auxInt64,
|
||||
|
|
@ -10845,6 +11177,50 @@ var opcodeTable = [...]opInfo{
|
|||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVBstorezero",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: arm64.AMOVB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVHstorezero",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: arm64.AMOVH,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVWstorezero",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: arm64.AMOVW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVDstorezero",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: arm64.AMOVD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVBreg",
|
||||
argLen: 1,
|
||||
|
|
@ -11197,6 +11573,19 @@ var opcodeTable = [...]opInfo{
|
|||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CSELULT0",
|
||||
argLen: 2,
|
||||
asm: arm64.ACSEL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CALLstatic",
|
||||
auxType: auxSymOff,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue