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[dev.ssa] cmd/compile, etc.: more ARM64 optimizations, and enable SSA by default
Add more ARM64 optimizations: - use hardware zero register when it is possible. - use shifted ops. The assembler supports shifted ops but not documented, nor knows how to print it. This CL adds them. - enable fast division. This was disabled because it makes the old backend generate slower code. But with SSA it generates faster code. Turn on SSA by default, also adjust tests. Change-Id: I7794479954c83bb65008dcb457bc1e21d7496da6 Reviewed-on: https://go-review.googlesource.com/26950 Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Cherry Zhang
parent
94c8e59ae1
commit
d99cee79b9
17 changed files with 3458 additions and 35 deletions
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@ -17,6 +17,7 @@ import (
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func setArch(goarch string) (*arch.Arch, *obj.Link) {
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os.Setenv("GOOS", "linux") // obj can handle this OS for all architectures.
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os.Setenv("GOARCH", goarch)
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architecture := arch.Set(goarch)
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if architecture == nil {
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panic("asm: unrecognized architecture " + goarch)
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@ -71,6 +71,7 @@ var progtable = [arm64.ALAST & obj.AMask]obj.ProgInfo{
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arm64.ACMPW & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead},
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arm64.AADC & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite | gc.UseCarry},
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arm64.AROR & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite},
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arm64.ARORW & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite},
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arm64.AADDS & obj.AMask: {Flags: gc.SizeQ | gc.LeftRead | gc.RegRead | gc.RightWrite | gc.SetCarry},
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arm64.ACSET & obj.AMask: {Flags: gc.SizeQ | gc.RightWrite},
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arm64.ACSEL & obj.AMask: {Flags: gc.SizeQ | gc.RegRead | gc.RightWrite},
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@ -148,6 +148,24 @@ func storeByType(t ssa.Type) obj.As {
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panic("bad store type")
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}
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// makeshift encodes a register shifted by a constant, used as an Offset in Prog
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func makeshift(reg int16, typ int64, s int64) int64 {
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return int64(reg&31)<<16 | typ | (s&63)<<10
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}
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// genshift generates a Prog for r = r0 op (r1 shifted by s)
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func genshift(as obj.As, r0, r1, r int16, typ int64, s int64) *obj.Prog {
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p := gc.Prog(as)
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p.From.Type = obj.TYPE_SHIFT
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p.From.Offset = makeshift(r1, typ, s)
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p.Reg = r0
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if r != 0 {
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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}
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return p
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}
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func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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s.SetLineno(v.Line)
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switch v.Op {
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@ -284,6 +302,27 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.Reg = gc.SSARegNum(v.Args[0])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpARM64ADDshiftLL,
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ssa.OpARM64SUBshiftLL,
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ssa.OpARM64ANDshiftLL,
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ssa.OpARM64ORshiftLL,
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ssa.OpARM64XORshiftLL,
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ssa.OpARM64BICshiftLL:
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genshift(v.Op.Asm(), gc.SSARegNum(v.Args[0]), gc.SSARegNum(v.Args[1]), gc.SSARegNum(v), arm64.SHIFT_LL, v.AuxInt)
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case ssa.OpARM64ADDshiftRL,
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ssa.OpARM64SUBshiftRL,
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ssa.OpARM64ANDshiftRL,
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ssa.OpARM64ORshiftRL,
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ssa.OpARM64XORshiftRL,
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ssa.OpARM64BICshiftRL:
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genshift(v.Op.Asm(), gc.SSARegNum(v.Args[0]), gc.SSARegNum(v.Args[1]), gc.SSARegNum(v), arm64.SHIFT_LR, v.AuxInt)
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case ssa.OpARM64ADDshiftRA,
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ssa.OpARM64SUBshiftRA,
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ssa.OpARM64ANDshiftRA,
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ssa.OpARM64ORshiftRA,
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ssa.OpARM64XORshiftRA,
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ssa.OpARM64BICshiftRA:
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genshift(v.Op.Asm(), gc.SSARegNum(v.Args[0]), gc.SSARegNum(v.Args[1]), gc.SSARegNum(v), arm64.SHIFT_AR, v.AuxInt)
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case ssa.OpARM64MOVDconst:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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@ -315,6 +354,12 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.Reg = gc.SSARegNum(v.Args[0])
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case ssa.OpARM64CMPshiftLL:
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genshift(v.Op.Asm(), gc.SSARegNum(v.Args[0]), gc.SSARegNum(v.Args[1]), 0, arm64.SHIFT_LL, v.AuxInt)
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case ssa.OpARM64CMPshiftRL:
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genshift(v.Op.Asm(), gc.SSARegNum(v.Args[0]), gc.SSARegNum(v.Args[1]), 0, arm64.SHIFT_LR, v.AuxInt)
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case ssa.OpARM64CMPshiftRA:
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genshift(v.Op.Asm(), gc.SSARegNum(v.Args[0]), gc.SSARegNum(v.Args[1]), 0, arm64.SHIFT_AR, v.AuxInt)
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case ssa.OpARM64MOVDaddr:
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p := gc.Prog(arm64.AMOVD)
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p.From.Type = obj.TYPE_ADDR
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@ -372,6 +417,16 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Type = obj.TYPE_MEM
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p.To.Reg = gc.SSARegNum(v.Args[0])
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gc.AddAux(&p.To, v)
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case ssa.OpARM64MOVBstorezero,
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ssa.OpARM64MOVHstorezero,
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ssa.OpARM64MOVWstorezero,
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ssa.OpARM64MOVDstorezero:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = arm64.REGZERO
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p.To.Type = obj.TYPE_MEM
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p.To.Reg = gc.SSARegNum(v.Args[0])
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gc.AddAux(&p.To, v)
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case ssa.OpARM64MOVBreg,
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ssa.OpARM64MOVBUreg,
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ssa.OpARM64MOVHreg,
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@ -433,12 +488,17 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.From.Reg = gc.SSARegNum(v.Args[0])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpARM64CSELULT:
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case ssa.OpARM64CSELULT,
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ssa.OpARM64CSELULT0:
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r1 := int16(arm64.REGZERO)
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if v.Op == ssa.OpARM64CSELULT {
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r1 = gc.SSARegNum(v.Args[1])
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}
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG // assembler encodes conditional bits in Reg
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p.From.Reg = arm64.COND_LO
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p.Reg = gc.SSARegNum(v.Args[0])
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p.From3 = &obj.Addr{Type: obj.TYPE_REG, Reg: gc.SSARegNum(v.Args[1])}
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p.From3 = &obj.Addr{Type: obj.TYPE_REG, Reg: r1}
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpARM64DUFFZERO:
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@ -40,7 +40,7 @@ func shouldssa(fn *Node) bool {
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if os.Getenv("SSATEST") == "" {
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return false
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}
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case "amd64", "amd64p32", "arm", "386":
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case "amd64", "amd64p32", "arm", "386", "arm64":
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// Generally available.
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}
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if !ssaEnabled {
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@ -3336,6 +3336,7 @@ func samecheap(a *Node, b *Node) bool {
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// The result of walkrotate MUST be assigned back to n, e.g.
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// n.Left = walkrotate(n.Left)
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func walkrotate(n *Node) *Node {
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//TODO: enable LROT on ARM64 once the old backend is gone
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if Thearch.LinkArch.InFamily(sys.MIPS64, sys.ARM64, sys.PPC64) {
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return n
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}
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@ -3529,16 +3530,6 @@ func walkdiv(n *Node, init *Nodes) *Node {
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goto ret
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}
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// TODO(zhongwei) Test shows that TUINT8, TINT8, TUINT16 and TINT16's "quick division" method
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// on current arm64 backend is slower than hardware div instruction on ARM64 due to unnecessary
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// data movement between registers. It could be enabled when generated code is good enough.
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if Thearch.LinkArch.Family == sys.ARM64 {
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switch Simtype[nl.Type.Etype] {
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case TUINT8, TINT8, TUINT16, TINT16:
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return n
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}
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}
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switch Simtype[nl.Type.Etype] {
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default:
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return n
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@ -523,6 +523,10 @@
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(MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) -> (MOVDstore [off1+off2] {sym} ptr val mem)
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(FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) -> (FMOVSstore [off1+off2] {sym} ptr val mem)
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(FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) -> (FMOVDstore [off1+off2] {sym} ptr val mem)
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(MOVBstorezero [off1] {sym} (ADDconst [off2] ptr) mem) -> (MOVBstorezero [off1+off2] {sym} ptr mem)
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(MOVHstorezero [off1] {sym} (ADDconst [off2] ptr) mem) -> (MOVHstorezero [off1+off2] {sym} ptr mem)
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(MOVWstorezero [off1] {sym} (ADDconst [off2] ptr) mem) -> (MOVWstorezero [off1+off2] {sym} ptr mem)
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(MOVDstorezero [off1] {sym} (ADDconst [off2] ptr) mem) -> (MOVDstorezero [off1+off2] {sym} ptr mem)
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(MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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@ -555,6 +559,20 @@
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(FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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(FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
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(FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
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(MOVBstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVHstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVWstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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(MOVDstorezero [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
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(MOVDstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
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// store zero
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(MOVBstore [off] {sym} ptr (MOVDconst [0]) mem) -> (MOVBstorezero [off] {sym} ptr mem)
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(MOVHstore [off] {sym} ptr (MOVDconst [0]) mem) -> (MOVHstorezero [off] {sym} ptr mem)
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(MOVWstore [off] {sym} ptr (MOVDconst [0]) mem) -> (MOVWstorezero [off] {sym} ptr mem)
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(MOVDstore [off] {sym} ptr (MOVDconst [0]) mem) -> (MOVDstorezero [off] {sym} ptr mem)
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// replace load from same location as preceding store with copy
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(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
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@ -567,6 +585,14 @@
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(FMOVSload [off] {sym} ptr (FMOVSstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
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(FMOVDload [off] {sym} ptr (FMOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
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(MOVBload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVDconst [0])
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(MOVBUload [off] {sym} ptr (MOVBstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVDconst [0])
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(MOVHload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVDconst [0])
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(MOVHUload [off] {sym} ptr (MOVHstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVDconst [0])
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(MOVWload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVDconst [0])
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(MOVWUload [off] {sym} ptr (MOVWstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVDconst [0])
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(MOVDload [off] {sym} ptr (MOVDstorezero [off2] {sym2} ptr2 _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVDconst [0])
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// don't extend after proper load
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(MOVBreg x:(MOVBload _ _)) -> (MOVDreg x)
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(MOVBUreg x:(MOVBUload _ _)) -> (MOVDreg x)
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@ -645,21 +671,46 @@
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(MUL _ (MOVDconst [0])) -> (MOVDconst [0])
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(MUL x (MOVDconst [1])) -> x
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(MUL x (MOVDconst [c])) && isPowerOfTwo(c) -> (SLLconst [log2(c)] x)
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(MUL x (MOVDconst [c])) && isPowerOfTwo(c-1) && c >= 3 -> (ADDshiftLL x x [log2(c-1)])
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(MUL x (MOVDconst [c])) && isPowerOfTwo(c+1) && c >= 7 -> (ADDshiftLL (NEG <x.Type> x) x [log2(c+1)])
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(MUL x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) -> (SLLconst [log2(c/3)] (ADDshiftLL <x.Type> x x [1]))
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(MUL x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) -> (SLLconst [log2(c/5)] (ADDshiftLL <x.Type> x x [2]))
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(MUL x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) -> (SLLconst [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3]))
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(MUL x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) -> (SLLconst [log2(c/9)] (ADDshiftLL <x.Type> x x [3]))
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(MUL (MOVDconst [-1]) x) -> (NEG x)
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(MUL (MOVDconst [0]) _) -> (MOVDconst [0])
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(MUL (MOVDconst [1]) x) -> x
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(MUL (MOVDconst [c]) x) && isPowerOfTwo(c) -> (SLLconst [log2(c)] x)
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(MUL (MOVDconst [c]) x) && isPowerOfTwo(c) -> (SLLconst [log2(c)] x)
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(MUL (MOVDconst [c]) x) && isPowerOfTwo(c-1) && c >= 3 -> (ADDshiftLL x x [log2(c-1)])
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(MUL (MOVDconst [c]) x) && isPowerOfTwo(c+1) && c >= 7 -> (ADDshiftLL (NEG <x.Type> x) x [log2(c+1)])
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(MUL (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo(c/3) -> (SLLconst [log2(c/3)] (ADDshiftLL <x.Type> x x [1]))
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(MUL (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo(c/5) -> (SLLconst [log2(c/5)] (ADDshiftLL <x.Type> x x [2]))
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(MUL (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo(c/7) -> (SLLconst [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3]))
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(MUL (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo(c/9) -> (SLLconst [log2(c/9)] (ADDshiftLL <x.Type> x x [3]))
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(MULW x (MOVDconst [c])) && int32(c)==-1 -> (NEG x)
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(MULW _ (MOVDconst [c])) && int32(c)==0 -> (MOVDconst [0])
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(MULW x (MOVDconst [c])) && int32(c)==1 -> x
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(MULW x (MOVDconst [c])) && isPowerOfTwo(c) -> (SLLconst [log2(c)] x)
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(MULW x (MOVDconst [c])) && isPowerOfTwo(c-1) && int32(c) >= 3 -> (ADDshiftLL x x [log2(c-1)])
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(MULW x (MOVDconst [c])) && isPowerOfTwo(c+1) && int32(c) >= 7 -> (ADDshiftLL (NEG <x.Type> x) x [log2(c+1)])
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(MULW x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) -> (SLLconst [log2(c/3)] (ADDshiftLL <x.Type> x x [1]))
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(MULW x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) -> (SLLconst [log2(c/5)] (ADDshiftLL <x.Type> x x [2]))
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(MULW x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) -> (SLLconst [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3]))
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(MULW x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) -> (SLLconst [log2(c/9)] (ADDshiftLL <x.Type> x x [3]))
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(MULW (MOVDconst [c]) x) && int32(c)==-1 -> (NEG x)
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(MULW (MOVDconst [c]) _) && int32(c)==0 -> (MOVDconst [0])
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(MULW (MOVDconst [c]) x) && int32(c)==1 -> x
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(MULW (MOVDconst [c]) x) && isPowerOfTwo(c) -> (SLLconst [log2(c)] x)
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(MULW (MOVDconst [c]) x) && isPowerOfTwo(c-1) && int32(c) >= 3 -> (ADDshiftLL x x [log2(c-1)])
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(MULW (MOVDconst [c]) x) && isPowerOfTwo(c+1) && int32(c) >= 7 -> (ADDshiftLL (NEG <x.Type> x) x [log2(c+1)])
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(MULW (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) -> (SLLconst [log2(c/3)] (ADDshiftLL <x.Type> x x [1]))
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(MULW (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) -> (SLLconst [log2(c/5)] (ADDshiftLL <x.Type> x x [2]))
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(MULW (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) -> (SLLconst [log2(c/7)] (ADDshiftLL <x.Type> (NEG <x.Type> x) x [3]))
|
||||
(MULW (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) -> (SLLconst [log2(c/9)] (ADDshiftLL <x.Type> x x [3]))
|
||||
|
||||
// div by constant
|
||||
(UDIV x (MOVDconst [1])) -> x
|
||||
|
|
@ -680,6 +731,7 @@
|
|||
(XOR x x) -> (MOVDconst [0])
|
||||
(BIC x x) -> (MOVDconst [0])
|
||||
(AND x (MVN y)) -> (BIC x y)
|
||||
(CSELULT x (MOVDconst [0]) flag) -> (CSELULT0 x flag)
|
||||
|
||||
// remove redundant *const ops
|
||||
(ADDconst [0] x) -> x
|
||||
|
|
@ -903,3 +955,103 @@
|
|||
(CSELULT _ y (FlagLT_UGT)) -> y
|
||||
(CSELULT x _ (FlagGT_ULT)) -> x
|
||||
(CSELULT _ y (FlagGT_UGT)) -> y
|
||||
(CSELULT0 _ (FlagEQ)) -> (MOVDconst [0])
|
||||
(CSELULT0 x (FlagLT_ULT)) -> x
|
||||
(CSELULT0 _ (FlagLT_UGT)) -> (MOVDconst [0])
|
||||
(CSELULT0 x (FlagGT_ULT)) -> x
|
||||
(CSELULT0 _ (FlagGT_UGT)) -> (MOVDconst [0])
|
||||
|
||||
// absorb shifts into ops
|
||||
(ADD x (SLLconst [c] y)) -> (ADDshiftLL x y [c])
|
||||
(ADD (SLLconst [c] y) x) -> (ADDshiftLL x y [c])
|
||||
(ADD x (SRLconst [c] y)) -> (ADDshiftRL x y [c])
|
||||
(ADD (SRLconst [c] y) x) -> (ADDshiftRL x y [c])
|
||||
(ADD x (SRAconst [c] y)) -> (ADDshiftRA x y [c])
|
||||
(ADD (SRAconst [c] y) x) -> (ADDshiftRA x y [c])
|
||||
(SUB x (SLLconst [c] y)) -> (SUBshiftLL x y [c])
|
||||
(SUB x (SRLconst [c] y)) -> (SUBshiftRL x y [c])
|
||||
(SUB x (SRAconst [c] y)) -> (SUBshiftRA x y [c])
|
||||
(AND x (SLLconst [c] y)) -> (ANDshiftLL x y [c])
|
||||
(AND (SLLconst [c] y) x) -> (ANDshiftLL x y [c])
|
||||
(AND x (SRLconst [c] y)) -> (ANDshiftRL x y [c])
|
||||
(AND (SRLconst [c] y) x) -> (ANDshiftRL x y [c])
|
||||
(AND x (SRAconst [c] y)) -> (ANDshiftRA x y [c])
|
||||
(AND (SRAconst [c] y) x) -> (ANDshiftRA x y [c])
|
||||
(OR x (SLLconst [c] y)) -> (ORshiftLL x y [c])
|
||||
(OR (SLLconst [c] y) x) -> (ORshiftLL x y [c])
|
||||
(OR x (SRLconst [c] y)) -> (ORshiftRL x y [c])
|
||||
(OR (SRLconst [c] y) x) -> (ORshiftRL x y [c])
|
||||
(OR x (SRAconst [c] y)) -> (ORshiftRA x y [c])
|
||||
(OR (SRAconst [c] y) x) -> (ORshiftRA x y [c])
|
||||
(XOR x (SLLconst [c] y)) -> (XORshiftLL x y [c])
|
||||
(XOR (SLLconst [c] y) x) -> (XORshiftLL x y [c])
|
||||
(XOR x (SRLconst [c] y)) -> (XORshiftRL x y [c])
|
||||
(XOR (SRLconst [c] y) x) -> (XORshiftRL x y [c])
|
||||
(XOR x (SRAconst [c] y)) -> (XORshiftRA x y [c])
|
||||
(XOR (SRAconst [c] y) x) -> (XORshiftRA x y [c])
|
||||
(BIC x (SLLconst [c] y)) -> (BICshiftLL x y [c])
|
||||
(BIC x (SRLconst [c] y)) -> (BICshiftRL x y [c])
|
||||
(BIC x (SRAconst [c] y)) -> (BICshiftRA x y [c])
|
||||
(CMP x (SLLconst [c] y)) -> (CMPshiftLL x y [c])
|
||||
(CMP (SLLconst [c] y) x) -> (InvertFlags (CMPshiftLL x y [c]))
|
||||
(CMP x (SRLconst [c] y)) -> (CMPshiftRL x y [c])
|
||||
(CMP (SRLconst [c] y) x) -> (InvertFlags (CMPshiftRL x y [c]))
|
||||
(CMP x (SRAconst [c] y)) -> (CMPshiftRA x y [c])
|
||||
(CMP (SRAconst [c] y) x) -> (InvertFlags (CMPshiftRA x y [c]))
|
||||
|
||||
// prefer *const ops to *shift ops
|
||||
(ADDshiftLL (MOVDconst [c]) x [d]) -> (ADDconst [c] (SLLconst <x.Type> x [d]))
|
||||
(ADDshiftRL (MOVDconst [c]) x [d]) -> (ADDconst [c] (SRLconst <x.Type> x [d]))
|
||||
(ADDshiftRA (MOVDconst [c]) x [d]) -> (ADDconst [c] (SRAconst <x.Type> x [d]))
|
||||
(ANDshiftLL (MOVDconst [c]) x [d]) -> (ANDconst [c] (SLLconst <x.Type> x [d]))
|
||||
(ANDshiftRL (MOVDconst [c]) x [d]) -> (ANDconst [c] (SRLconst <x.Type> x [d]))
|
||||
(ANDshiftRA (MOVDconst [c]) x [d]) -> (ANDconst [c] (SRAconst <x.Type> x [d]))
|
||||
(ORshiftLL (MOVDconst [c]) x [d]) -> (ORconst [c] (SLLconst <x.Type> x [d]))
|
||||
(ORshiftRL (MOVDconst [c]) x [d]) -> (ORconst [c] (SRLconst <x.Type> x [d]))
|
||||
(ORshiftRA (MOVDconst [c]) x [d]) -> (ORconst [c] (SRAconst <x.Type> x [d]))
|
||||
(XORshiftLL (MOVDconst [c]) x [d]) -> (XORconst [c] (SLLconst <x.Type> x [d]))
|
||||
(XORshiftRL (MOVDconst [c]) x [d]) -> (XORconst [c] (SRLconst <x.Type> x [d]))
|
||||
(XORshiftRA (MOVDconst [c]) x [d]) -> (XORconst [c] (SRAconst <x.Type> x [d]))
|
||||
(CMPshiftLL (MOVDconst [c]) x [d]) -> (InvertFlags (CMPconst [c] (SLLconst <x.Type> x [d])))
|
||||
(CMPshiftRL (MOVDconst [c]) x [d]) -> (InvertFlags (CMPconst [c] (SRLconst <x.Type> x [d])))
|
||||
(CMPshiftRA (MOVDconst [c]) x [d]) -> (InvertFlags (CMPconst [c] (SRAconst <x.Type> x [d])))
|
||||
|
||||
// constant folding in *shift ops
|
||||
(ADDshiftLL x (MOVDconst [c]) [d]) -> (ADDconst x [int64(uint64(c)<<uint64(d))])
|
||||
(ADDshiftRL x (MOVDconst [c]) [d]) -> (ADDconst x [int64(uint64(c)>>uint64(d))])
|
||||
(ADDshiftRA x (MOVDconst [c]) [d]) -> (ADDconst x [int64(int64(c)>>uint64(d))])
|
||||
(SUBshiftLL x (MOVDconst [c]) [d]) -> (SUBconst x [int64(uint64(c)<<uint64(d))])
|
||||
(SUBshiftRL x (MOVDconst [c]) [d]) -> (SUBconst x [int64(uint64(c)>>uint64(d))])
|
||||
(SUBshiftRA x (MOVDconst [c]) [d]) -> (SUBconst x [int64(int64(c)>>uint64(d))])
|
||||
(ANDshiftLL x (MOVDconst [c]) [d]) -> (ANDconst x [int64(uint64(c)<<uint64(d))])
|
||||
(ANDshiftRL x (MOVDconst [c]) [d]) -> (ANDconst x [int64(uint64(c)>>uint64(d))])
|
||||
(ANDshiftRA x (MOVDconst [c]) [d]) -> (ANDconst x [int64(int64(c)>>uint64(d))])
|
||||
(ORshiftLL x (MOVDconst [c]) [d]) -> (ORconst x [int64(uint64(c)<<uint64(d))])
|
||||
(ORshiftRL x (MOVDconst [c]) [d]) -> (ORconst x [int64(uint64(c)>>uint64(d))])
|
||||
(ORshiftRA x (MOVDconst [c]) [d]) -> (ORconst x [int64(int64(c)>>uint64(d))])
|
||||
(XORshiftLL x (MOVDconst [c]) [d]) -> (XORconst x [int64(uint64(c)<<uint64(d))])
|
||||
(XORshiftRL x (MOVDconst [c]) [d]) -> (XORconst x [int64(uint64(c)>>uint64(d))])
|
||||
(XORshiftRA x (MOVDconst [c]) [d]) -> (XORconst x [int64(int64(c)>>uint64(d))])
|
||||
(BICshiftLL x (MOVDconst [c]) [d]) -> (BICconst x [int64(uint64(c)<<uint64(d))])
|
||||
(BICshiftRL x (MOVDconst [c]) [d]) -> (BICconst x [int64(uint64(c)>>uint64(d))])
|
||||
(BICshiftRA x (MOVDconst [c]) [d]) -> (BICconst x [int64(int64(c)>>uint64(d))])
|
||||
(CMPshiftLL x (MOVDconst [c]) [d]) -> (CMPconst x [int64(uint64(c)<<uint64(d))])
|
||||
(CMPshiftRL x (MOVDconst [c]) [d]) -> (CMPconst x [int64(uint64(c)>>uint64(d))])
|
||||
(CMPshiftRA x (MOVDconst [c]) [d]) -> (CMPconst x [int64(int64(c)>>uint64(d))])
|
||||
|
||||
// simplification with *shift ops
|
||||
(SUBshiftLL x (SLLconst x [c]) [d]) && c==d -> (MOVDconst [0])
|
||||
(SUBshiftRL x (SRLconst x [c]) [d]) && c==d -> (MOVDconst [0])
|
||||
(SUBshiftRA x (SRAconst x [c]) [d]) && c==d -> (MOVDconst [0])
|
||||
(ANDshiftLL x y:(SLLconst x [c]) [d]) && c==d -> y
|
||||
(ANDshiftRL x y:(SRLconst x [c]) [d]) && c==d -> y
|
||||
(ANDshiftRA x y:(SRAconst x [c]) [d]) && c==d -> y
|
||||
(ORshiftLL x y:(SLLconst x [c]) [d]) && c==d -> y
|
||||
(ORshiftRL x y:(SRLconst x [c]) [d]) && c==d -> y
|
||||
(ORshiftRA x y:(SRAconst x [c]) [d]) && c==d -> y
|
||||
(XORshiftLL x (SLLconst x [c]) [d]) && c==d -> (MOVDconst [0])
|
||||
(XORshiftRL x (SRLconst x [c]) [d]) && c==d -> (MOVDconst [0])
|
||||
(XORshiftRA x (SRAconst x [c]) [d]) && c==d -> (MOVDconst [0])
|
||||
(BICshiftLL x (SLLconst x [c]) [d]) && c==d -> (MOVDconst [0])
|
||||
(BICshiftRL x (SRLconst x [c]) [d]) && c==d -> (MOVDconst [0])
|
||||
(BICshiftRA x (SRAconst x [c]) [d]) && c==d -> (MOVDconst [0])
|
||||
|
|
|
|||
|
|
@ -133,11 +133,11 @@ func init() {
|
|||
)
|
||||
// Common regInfo
|
||||
var (
|
||||
gp01 = regInfo{inputs: nil, outputs: []regMask{gp}}
|
||||
gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}}
|
||||
gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}}
|
||||
gp1flags = regInfo{inputs: []regMask{gpg}}
|
||||
//gp1flags1 = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}
|
||||
gp01 = regInfo{inputs: nil, outputs: []regMask{gp}}
|
||||
gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}}
|
||||
gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}}
|
||||
gp1flags = regInfo{inputs: []regMask{gpg}}
|
||||
gp1flags1 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}}
|
||||
gp21 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}}
|
||||
gp2flags = regInfo{inputs: []regMask{gpg, gpg}}
|
||||
gp2flags1 = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp}}
|
||||
|
|
@ -145,8 +145,9 @@ func init() {
|
|||
//gp31 = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}}
|
||||
//gp3flags = regInfo{inputs: []regMask{gp, gp, gp}}
|
||||
//gp3flags1 = regInfo{inputs: []regMask{gp, gp, gp}, outputs: []regMask{gp}}
|
||||
gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}
|
||||
gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}}
|
||||
gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}
|
||||
gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}}
|
||||
gpstore0 = regInfo{inputs: []regMask{gpspsbg}}
|
||||
//gp2load = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}}
|
||||
//gp2store = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}}
|
||||
fp01 = regInfo{inputs: nil, outputs: []regMask{fp}}
|
||||
|
|
@ -228,6 +229,29 @@ func init() {
|
|||
{name: "FCMPS", argLength: 2, reg: fp2flags, asm: "FCMPS", typ: "Flags"}, // arg0 compare to arg1, float32
|
||||
{name: "FCMPD", argLength: 2, reg: fp2flags, asm: "FCMPD", typ: "Flags"}, // arg0 compare to arg1, float64
|
||||
|
||||
// shifted ops
|
||||
{name: "ADDshiftLL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int64"}, // arg0 + arg1<<auxInt
|
||||
{name: "ADDshiftRL", argLength: 2, reg: gp21, asm: "ADD", aux: "Int64"}, // arg0 + arg1>>auxInt, unsigned shift
|
||||
{name: "ADDshiftRA", argLength: 2, reg: gp21, asm: "ADD", aux: "Int64"}, // arg0 + arg1>>auxInt, signed shift
|
||||
{name: "SUBshiftLL", argLength: 2, reg: gp21, asm: "SUB", aux: "Int64"}, // arg0 - arg1<<auxInt
|
||||
{name: "SUBshiftRL", argLength: 2, reg: gp21, asm: "SUB", aux: "Int64"}, // arg0 - arg1>>auxInt, unsigned shift
|
||||
{name: "SUBshiftRA", argLength: 2, reg: gp21, asm: "SUB", aux: "Int64"}, // arg0 - arg1>>auxInt, signed shift
|
||||
{name: "ANDshiftLL", argLength: 2, reg: gp21, asm: "AND", aux: "Int64"}, // arg0 & (arg1<<auxInt)
|
||||
{name: "ANDshiftRL", argLength: 2, reg: gp21, asm: "AND", aux: "Int64"}, // arg0 & (arg1>>auxInt), unsigned shift
|
||||
{name: "ANDshiftRA", argLength: 2, reg: gp21, asm: "AND", aux: "Int64"}, // arg0 & (arg1>>auxInt), signed shift
|
||||
{name: "ORshiftLL", argLength: 2, reg: gp21, asm: "ORR", aux: "Int64"}, // arg0 | arg1<<auxInt
|
||||
{name: "ORshiftRL", argLength: 2, reg: gp21, asm: "ORR", aux: "Int64"}, // arg0 | arg1>>auxInt, unsigned shift
|
||||
{name: "ORshiftRA", argLength: 2, reg: gp21, asm: "ORR", aux: "Int64"}, // arg0 | arg1>>auxInt, signed shift
|
||||
{name: "XORshiftLL", argLength: 2, reg: gp21, asm: "EOR", aux: "Int64"}, // arg0 ^ arg1<<auxInt
|
||||
{name: "XORshiftRL", argLength: 2, reg: gp21, asm: "EOR", aux: "Int64"}, // arg0 ^ arg1>>auxInt, unsigned shift
|
||||
{name: "XORshiftRA", argLength: 2, reg: gp21, asm: "EOR", aux: "Int64"}, // arg0 ^ arg1>>auxInt, signed shift
|
||||
{name: "BICshiftLL", argLength: 2, reg: gp21, asm: "BIC", aux: "Int64"}, // arg0 &^ (arg1<<auxInt)
|
||||
{name: "BICshiftRL", argLength: 2, reg: gp21, asm: "BIC", aux: "Int64"}, // arg0 &^ (arg1>>auxInt), unsigned shift
|
||||
{name: "BICshiftRA", argLength: 2, reg: gp21, asm: "BIC", aux: "Int64"}, // arg0 &^ (arg1>>auxInt), signed shift
|
||||
{name: "CMPshiftLL", argLength: 2, reg: gp2flags, asm: "CMP", aux: "Int64", typ: "Flags"}, // arg0 compare to arg1<<auxInt
|
||||
{name: "CMPshiftRL", argLength: 2, reg: gp2flags, asm: "CMP", aux: "Int64", typ: "Flags"}, // arg0 compare to arg1>>auxInt, unsigned shift
|
||||
{name: "CMPshiftRA", argLength: 2, reg: gp2flags, asm: "CMP", aux: "Int64", typ: "Flags"}, // arg0 compare to arg1>>auxInt, signed shift
|
||||
|
||||
// moves
|
||||
{name: "MOVDconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVD", typ: "UInt64", rematerializeable: true}, // 32 low bits of auxint
|
||||
{name: "FMOVSconst", argLength: 0, reg: fp01, aux: "Float64", asm: "FMOVS", typ: "Float32", rematerializeable: true}, // auxint as 64-bit float, convert to 32-bit float
|
||||
|
|
@ -252,6 +276,11 @@ func init() {
|
|||
{name: "FMOVSstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "FMOVS", typ: "Mem"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
|
||||
{name: "FMOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "FMOVD", typ: "Mem"}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
|
||||
|
||||
{name: "MOVBstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVB", typ: "Mem"}, // store 1 byte of zero to arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVHstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVH", typ: "Mem"}, // store 2 bytes of zero to arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVWstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVW", typ: "Mem"}, // store 4 bytes of zero to arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVDstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVD", typ: "Mem"}, // store 8 bytes of zero to arg0 + auxInt + aux. ar12=mem.
|
||||
|
||||
// conversions
|
||||
{name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"}, // move from arg0, sign-extended from byte
|
||||
{name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte
|
||||
|
|
@ -283,7 +312,8 @@ func init() {
|
|||
{name: "FCVTDS", argLength: 1, reg: fp11, asm: "FCVTDS"}, // float64 -> float32
|
||||
|
||||
// conditional instructions
|
||||
{name: "CSELULT", argLength: 3, reg: gp2flags1, asm: "CSEL"}, // returns arg0 if flags indicates unsigned LT, arg1 otherwise, arg2=flags
|
||||
{name: "CSELULT", argLength: 3, reg: gp2flags1, asm: "CSEL"}, // returns arg0 if flags indicates unsigned LT, arg1 otherwise, arg2=flags
|
||||
{name: "CSELULT0", argLength: 2, reg: gp1flags1, asm: "CSEL"}, // returns arg0 if flags indicates unsigned LT, 0 otherwise, arg1=flags
|
||||
|
||||
// function calls
|
||||
{name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff", clobberFlags: true}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
|
||||
|
|
|
|||
|
|
@ -859,6 +859,27 @@ const (
|
|||
OpARM64CMNWconst
|
||||
OpARM64FCMPS
|
||||
OpARM64FCMPD
|
||||
OpARM64ADDshiftLL
|
||||
OpARM64ADDshiftRL
|
||||
OpARM64ADDshiftRA
|
||||
OpARM64SUBshiftLL
|
||||
OpARM64SUBshiftRL
|
||||
OpARM64SUBshiftRA
|
||||
OpARM64ANDshiftLL
|
||||
OpARM64ANDshiftRL
|
||||
OpARM64ANDshiftRA
|
||||
OpARM64ORshiftLL
|
||||
OpARM64ORshiftRL
|
||||
OpARM64ORshiftRA
|
||||
OpARM64XORshiftLL
|
||||
OpARM64XORshiftRL
|
||||
OpARM64XORshiftRA
|
||||
OpARM64BICshiftLL
|
||||
OpARM64BICshiftRL
|
||||
OpARM64BICshiftRA
|
||||
OpARM64CMPshiftLL
|
||||
OpARM64CMPshiftRL
|
||||
OpARM64CMPshiftRA
|
||||
OpARM64MOVDconst
|
||||
OpARM64FMOVSconst
|
||||
OpARM64FMOVDconst
|
||||
|
|
@ -878,6 +899,10 @@ const (
|
|||
OpARM64MOVDstore
|
||||
OpARM64FMOVSstore
|
||||
OpARM64FMOVDstore
|
||||
OpARM64MOVBstorezero
|
||||
OpARM64MOVHstorezero
|
||||
OpARM64MOVWstorezero
|
||||
OpARM64MOVDstorezero
|
||||
OpARM64MOVBreg
|
||||
OpARM64MOVBUreg
|
||||
OpARM64MOVHreg
|
||||
|
|
@ -905,6 +930,7 @@ const (
|
|||
OpARM64FCVTSD
|
||||
OpARM64FCVTDS
|
||||
OpARM64CSELULT
|
||||
OpARM64CSELULT0
|
||||
OpARM64CALLstatic
|
||||
OpARM64CALLclosure
|
||||
OpARM64CALLdefer
|
||||
|
|
@ -10596,6 +10622,312 @@ var opcodeTable = [...]opInfo{
|
|||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ADDshiftLL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.AADD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ADDshiftRL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.AADD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ADDshiftRA",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.AADD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SUBshiftLL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.ASUB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SUBshiftRL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.ASUB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SUBshiftRA",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.ASUB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ANDshiftLL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.AAND,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ANDshiftRL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.AAND,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ANDshiftRA",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.AAND,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ORshiftLL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.AORR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ORshiftRL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.AORR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ORshiftRA",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.AORR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "XORshiftLL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.AEOR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "XORshiftRL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.AEOR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "XORshiftRA",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.AEOR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "BICshiftLL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.ABIC,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "BICshiftRL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.ABIC,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "BICshiftRA",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.ABIC,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMPshiftLL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.ACMP,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMPshiftRL",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.ACMP,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMPshiftRA",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
asm: arm64.ACMP,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
{1, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVDconst",
|
||||
auxType: auxInt64,
|
||||
|
|
@ -10845,6 +11177,50 @@ var opcodeTable = [...]opInfo{
|
|||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVBstorezero",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: arm64.AMOVB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVHstorezero",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: arm64.AMOVH,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVWstorezero",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: arm64.AMOVW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVDstorezero",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: arm64.AMOVD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4611686019232432127}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g SP SB
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVBreg",
|
||||
argLen: 1,
|
||||
|
|
@ -11197,6 +11573,19 @@ var opcodeTable = [...]opInfo{
|
|||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CSELULT0",
|
||||
argLen: 2,
|
||||
asm: arm64.ACSEL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 268173311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 133955583}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CALLstatic",
|
||||
auxType: auxSymOff,
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -714,3 +714,10 @@ const (
|
|||
AB = obj.AJMP
|
||||
ABL = obj.ACALL
|
||||
)
|
||||
|
||||
const (
|
||||
// shift types
|
||||
SHIFT_LL = 0 << 22
|
||||
SHIFT_LR = 1 << 22
|
||||
SHIFT_AR = 2 << 22
|
||||
)
|
||||
|
|
|
|||
|
|
@ -112,13 +112,17 @@ import (
|
|||
// val = int32(y)
|
||||
//
|
||||
// reg<<shift, reg>>shift, reg->shift, reg@>shift
|
||||
// Shifted register value, for ARM.
|
||||
// Shifted register value, for ARM and ARM64.
|
||||
// In this form, reg must be a register and shift can be a register or an integer constant.
|
||||
// Encoding:
|
||||
// type = TYPE_SHIFT
|
||||
// On ARM:
|
||||
// offset = (reg&15) | shifttype<<5 | count
|
||||
// shifttype = 0, 1, 2, 3 for <<, >>, ->, @>
|
||||
// count = (reg&15)<<8 | 1<<4 for a register shift count, (n&31)<<7 for an integer constant.
|
||||
// On ARM64:
|
||||
// offset = (reg&31)<<16 | shifttype<<22 | (count&63)<<10
|
||||
// shifttype = 0, 1, 2 for <<, >>, ->
|
||||
//
|
||||
// (reg, reg)
|
||||
// A destination register pair. When used as the last argument of an instruction,
|
||||
|
|
|
|||
|
|
@ -286,14 +286,23 @@ func Dconv(p *Prog, a *Addr) string {
|
|||
|
||||
case TYPE_SHIFT:
|
||||
v := int(a.Offset)
|
||||
op := "<<>>->@>"[((v>>5)&3)<<1:]
|
||||
if v&(1<<4) != 0 {
|
||||
str = fmt.Sprintf("R%d%c%cR%d", v&15, op[0], op[1], (v>>8)&15)
|
||||
} else {
|
||||
str = fmt.Sprintf("R%d%c%c%d", v&15, op[0], op[1], (v>>7)&31)
|
||||
}
|
||||
if a.Reg != 0 {
|
||||
str += fmt.Sprintf("(%v)", Rconv(int(a.Reg)))
|
||||
ops := "<<>>->@>"
|
||||
switch goarch := Getgoarch(); goarch {
|
||||
case "arm":
|
||||
op := ops[((v>>5)&3)<<1:]
|
||||
if v&(1<<4) != 0 {
|
||||
str = fmt.Sprintf("R%d%c%cR%d", v&15, op[0], op[1], (v>>8)&15)
|
||||
} else {
|
||||
str = fmt.Sprintf("R%d%c%c%d", v&15, op[0], op[1], (v>>7)&31)
|
||||
}
|
||||
if a.Reg != 0 {
|
||||
str += fmt.Sprintf("(%v)", Rconv(int(a.Reg)))
|
||||
}
|
||||
case "arm64":
|
||||
op := ops[((v>>22)&3)<<1:]
|
||||
str = fmt.Sprintf("R%d%c%c%d", (v>>16)&31, op[0], op[1], (v>>10)&63)
|
||||
default:
|
||||
panic("TYPE_SHIFT is not supported on " + goarch)
|
||||
}
|
||||
|
||||
case TYPE_REGREG:
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
// +build !amd64,!arm,!amd64p32,!386
|
||||
// +build !amd64,!arm,!amd64p32,!386,!arm64
|
||||
// errorcheck -0 -l -live -wb=0
|
||||
|
||||
// Copyright 2014 The Go Authors. All rights reserved.
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
// +build amd64 arm amd64p32 386
|
||||
// +build amd64 arm amd64p32 386 arm64
|
||||
// errorcheck -0 -l -live -wb=0
|
||||
|
||||
// Copyright 2014 The Go Authors. All rights reserved.
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
// Fails on ppc64x because of incomplete optimization.
|
||||
// See issues 9058.
|
||||
// Same reason for mips64x and s390x.
|
||||
// +build !ppc64,!ppc64le,!mips64,!mips64le,!amd64,!s390x,!arm,!amd64p32,!386
|
||||
// +build !ppc64,!ppc64le,!mips64,!mips64le,!amd64,!s390x,!arm,!amd64p32,!386,!arm64
|
||||
|
||||
// Copyright 2013 The Go Authors. All rights reserved.
|
||||
// Use of this source code is governed by a BSD-style
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
// errorcheck -0 -d=nil
|
||||
// +build amd64 arm amd64p32 386
|
||||
// +build amd64 arm amd64p32 386 arm64
|
||||
|
||||
// Copyright 2013 The Go Authors. All rights reserved.
|
||||
// Use of this source code is governed by a BSD-style
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
// +build !amd64,!arm,!amd64p32,!386
|
||||
// +build !amd64,!arm,!amd64p32,!386,!arm64
|
||||
// errorcheck -0 -d=append,slice
|
||||
|
||||
// Copyright 2015 The Go Authors. All rights reserved.
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue