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[dev.ssa] cmd/compile: implement the following for SSA on ARM
- generic Ops: Phi, CALL variants, NilCheck - generic Blocks: Plain, Check - 32-bit arithmetics - CMP and conditional branches - load/store - zero/sign-extensions (8 to 16, 8 to 32, 16 to 32) Progress on SSA backend for ARM. Still not complete. Now "errors" package compiles and tests passed. Updates #15365. Change-Id: If126fd17f8695cbf55d64085bb3f1a4a53205701 Reviewed-on: https://go-review.googlesource.com/22856 Reviewed-by: Keith Randall <khr@golang.org>
This commit is contained in:
Cherry Zhang
parent
fdc4a964d2
commit
e2848de9ef
6 changed files with 2754 additions and 72 deletions
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@ -16,7 +16,21 @@ var ssaRegToReg = []int16{
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arm.REG_R1,
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arm.REG_R2,
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arm.REG_R3,
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arm.REG_R4,
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arm.REG_R5,
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arm.REG_R6,
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arm.REG_R7,
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arm.REG_R8,
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arm.REG_R9,
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arm.REG_R10,
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arm.REG_R11,
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arm.REG_R12,
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arm.REGSP, // aka R13
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arm.REG_R14,
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arm.REG_R15,
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arm.REG_CPSR, // flag
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0, // SB isn't a real register. We fill an Addr.Reg field with 0 in this case.
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}
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func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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@ -45,7 +59,18 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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}
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpPhi:
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// just check to make sure regalloc and stackalloc did it right
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if v.Type.IsMemory() {
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return
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}
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f := v.Block.Func
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loc := f.RegAlloc[v.ID]
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for _, a := range v.Args {
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if aloc := f.RegAlloc[a.ID]; aloc != loc { // TODO: .Equal() instead?
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v.Fatalf("phi arg at different location than phi: %v @ %v, but arg %v @ %v\n%s\n", v, loc, a, aloc, v.Block.Func)
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}
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}
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case ssa.OpStoreReg:
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// TODO: by type
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p := gc.Prog(arm.AMOVW)
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@ -62,14 +87,20 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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} else {
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p.To.Name = obj.NAME_AUTO
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}
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case ssa.OpARMADD:
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case ssa.OpARMADD,
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ssa.OpARMSUB,
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ssa.OpARMRSB,
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ssa.OpARMAND,
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ssa.OpARMOR,
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ssa.OpARMXOR,
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ssa.OpARMBIC:
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r := gc.SSARegNum(v)
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r1 := gc.SSARegNum(v.Args[0])
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r2 := gc.SSARegNum(v.Args[1])
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = r1
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p.Reg = r2
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p.From.Reg = r2
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p.Reg = r1
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpARMADDconst:
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@ -101,6 +132,13 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Reg = gc.SSARegNum(v)
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break
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}
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fallthrough
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case ssa.OpARMSUBconst,
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ssa.OpARMRSBconst,
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ssa.OpARMANDconst,
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ssa.OpARMORconst,
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ssa.OpARMXORconst,
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ssa.OpARMBICconst:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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@ -113,27 +151,57 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpARMCMP:
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case ssa.OpARMCMP,
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ssa.OpARMCMN,
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ssa.OpARMTST,
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ssa.OpARMTEQ:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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// Special layout in ARM assembly
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// Comparing to x86, the operands of ARM's CMP are reversed.
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p.From.Reg = gc.SSARegNum(v.Args[1])
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p.Reg = gc.SSARegNum(v.Args[0])
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case ssa.OpARMMOVWload:
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case ssa.OpARMCMPconst,
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ssa.OpARMCMNconst,
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ssa.OpARMTSTconst,
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ssa.OpARMTEQconst:
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// Special layout in ARM assembly
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.Reg = gc.SSARegNum(v.Args[0])
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case ssa.OpARMMOVBload,
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ssa.OpARMMOVBUload,
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ssa.OpARMMOVHload,
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ssa.OpARMMOVHUload,
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ssa.OpARMMOVWload:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = gc.SSARegNum(v.Args[0])
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpARMMOVWstore:
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case ssa.OpARMMOVBstore,
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ssa.OpARMMOVHstore,
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ssa.OpARMMOVWstore:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = gc.SSARegNum(v.Args[1])
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p.To.Type = obj.TYPE_MEM
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p.To.Reg = gc.SSARegNum(v.Args[0])
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gc.AddAux(&p.To, v)
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case ssa.OpARMMOVBreg,
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ssa.OpARMMOVBUreg,
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ssa.OpARMMOVHreg,
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ssa.OpARMMOVHUreg:
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if v.Type.IsMemory() {
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v.Fatalf("memory operand for %s", v.LongString())
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}
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = gc.SSARegNum(v.Args[0])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpARMCALLstatic:
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// TODO: deferreturn
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p := gc.Prog(obj.ACALL)
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@ -143,37 +211,126 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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if gc.Maxarg < v.AuxInt {
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gc.Maxarg = v.AuxInt
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}
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case ssa.OpARMCALLclosure:
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p := gc.Prog(obj.ACALL)
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p.To.Type = obj.TYPE_MEM
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p.To.Offset = 0
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p.To.Reg = gc.SSARegNum(v.Args[0])
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if gc.Maxarg < v.AuxInt {
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gc.Maxarg = v.AuxInt
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}
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case ssa.OpARMCALLdefer:
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p := gc.Prog(obj.ACALL)
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p.To.Type = obj.TYPE_MEM
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p.To.Name = obj.NAME_EXTERN
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p.To.Sym = gc.Linksym(gc.Deferproc.Sym)
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if gc.Maxarg < v.AuxInt {
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gc.Maxarg = v.AuxInt
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}
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case ssa.OpARMCALLgo:
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p := gc.Prog(obj.ACALL)
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p.To.Type = obj.TYPE_MEM
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p.To.Name = obj.NAME_EXTERN
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p.To.Sym = gc.Linksym(gc.Newproc.Sym)
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if gc.Maxarg < v.AuxInt {
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gc.Maxarg = v.AuxInt
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}
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case ssa.OpARMCALLinter:
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p := gc.Prog(obj.ACALL)
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p.To.Type = obj.TYPE_MEM
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p.To.Offset = 0
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p.To.Reg = gc.SSARegNum(v.Args[0])
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if gc.Maxarg < v.AuxInt {
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gc.Maxarg = v.AuxInt
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}
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case ssa.OpARMLoweredNilCheck:
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// Issue a load which will fault if arg is nil.
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p := gc.Prog(arm.AMOVB)
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = gc.SSARegNum(v.Args[0])
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = arm.REGTMP
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if gc.Debug_checknil != 0 && v.Line > 1 { // v.Line==1 in generated wrappers
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gc.Warnl(v.Line, "generated nil check")
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}
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case ssa.OpVarDef:
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gc.Gvardef(v.Aux.(*gc.Node))
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case ssa.OpVarKill:
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gc.Gvarkill(v.Aux.(*gc.Node))
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case ssa.OpVarLive:
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gc.Gvarlive(v.Aux.(*gc.Node))
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case ssa.OpARMLessThan:
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case ssa.OpARMEqual,
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ssa.OpARMNotEqual,
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ssa.OpARMLessThan,
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ssa.OpARMLessEqual,
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ssa.OpARMGreaterThan,
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ssa.OpARMGreaterEqual,
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ssa.OpARMLessThanU,
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ssa.OpARMLessEqualU,
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ssa.OpARMGreaterThanU,
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ssa.OpARMGreaterEqualU:
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v.Fatalf("pseudo-op made it to output: %s", v.LongString())
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default:
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v.Unimplementedf("genValue not implemented: %s", v.LongString())
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}
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}
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var blockJump = map[ssa.BlockKind]struct {
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asm, invasm obj.As
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}{
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ssa.BlockARMEQ: {arm.ABEQ, arm.ABNE},
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ssa.BlockARMNE: {arm.ABNE, arm.ABEQ},
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ssa.BlockARMLT: {arm.ABLT, arm.ABGE},
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ssa.BlockARMGE: {arm.ABGE, arm.ABLT},
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ssa.BlockARMLE: {arm.ABLE, arm.ABGT},
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ssa.BlockARMGT: {arm.ABGT, arm.ABLE},
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ssa.BlockARMULT: {arm.ABCS, arm.ABCC},
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ssa.BlockARMUGE: {arm.ABCC, arm.ABCS},
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ssa.BlockARMUGT: {arm.ABHI, arm.ABLS},
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ssa.BlockARMULE: {arm.ABLS, arm.ABHI},
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}
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func ssaGenBlock(s *gc.SSAGenState, b, next *ssa.Block) {
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s.SetLineno(b.Line)
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switch b.Kind {
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case ssa.BlockCall:
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case ssa.BlockPlain, ssa.BlockCall, ssa.BlockCheck:
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if b.Succs[0].Block() != next {
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p := gc.Prog(obj.AJMP)
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p.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
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}
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case ssa.BlockRet:
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gc.Prog(obj.ARET)
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case ssa.BlockARMLT:
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p := gc.Prog(arm.ABLT)
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p.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
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p = gc.Prog(obj.AJMP)
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p.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[1].Block()})
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case ssa.BlockARMEQ, ssa.BlockARMNE,
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ssa.BlockARMLT, ssa.BlockARMGE,
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ssa.BlockARMLE, ssa.BlockARMGT,
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ssa.BlockARMULT, ssa.BlockARMUGT,
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ssa.BlockARMULE, ssa.BlockARMUGE:
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jmp := blockJump[b.Kind]
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var p *obj.Prog
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switch next {
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case b.Succs[0].Block():
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p = gc.Prog(jmp.invasm)
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p.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[1].Block()})
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case b.Succs[1].Block():
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p = gc.Prog(jmp.asm)
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p.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
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default:
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p = gc.Prog(jmp.asm)
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p.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
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q := gc.Prog(obj.AJMP)
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q.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{P: q, B: b.Succs[1].Block()})
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}
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default:
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b.Unimplementedf("branch not implemented: %s. Control: %s", b.LongString(), b.Control.LongString())
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}
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}
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@ -3,30 +3,138 @@
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// license that can be found in the LICENSE file.
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(Add32 x y) -> (ADD x y)
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(Sub32 x y) -> (SUB x y)
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(And32 x y) -> (AND x y)
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(Or32 x y) -> (OR x y)
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(Xor32 x y) -> (XOR x y)
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(Const8 [val]) -> (MOVWconst [val])
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(Const16 [val]) -> (MOVWconst [val])
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(Const32 [val]) -> (MOVWconst [val])
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(ConstNil) -> (MOVWconst [0])
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(ConstBool [b]) -> (MOVWconst [b])
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(Trunc16to8 x) -> x
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(Trunc32to8 x) -> x
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(Trunc32to16 x) -> x
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(ZeroExt8to16 x) -> (MOVBUreg x)
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(ZeroExt8to32 x) -> (MOVBUreg x)
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(ZeroExt16to32 x) -> (MOVHUreg x)
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(SignExt8to16 x) -> (MOVBreg x)
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(SignExt8to32 x) -> (MOVBreg x)
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(SignExt16to32 x) -> (MOVHreg x)
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(Eq8 x y) -> (Equal (CMP (ZeroExt8to32 x) (ZeroExt8to32 y)))
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(Eq16 x y) -> (Equal (CMP (ZeroExt16to32 x) (ZeroExt16to32 y)))
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(Eq32 x y) -> (Equal (CMP x y))
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(Neq8 x y) -> (NotEqual (CMP (ZeroExt8to32 x) (ZeroExt8to32 y)))
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(Neq16 x y) -> (NotEqual (CMP (ZeroExt16to32 x) (ZeroExt16to32 y)))
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(Neq32 x y) -> (NotEqual (CMP x y))
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(Less8 x y) -> (LessThan (CMP (SignExt8to32 x) (SignExt8to32 y)))
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(Less16 x y) -> (LessThan (CMP (SignExt16to32 x) (SignExt16to32 y)))
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(Less32 x y) -> (LessThan (CMP x y))
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(Less8U x y) -> (LessThanU (CMP (ZeroExt8to32 x) (ZeroExt8to32 y)))
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(Less16U x y) -> (LessThanU (CMP (ZeroExt16to32 x) (ZeroExt16to32 y)))
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(Less32U x y) -> (LessThanU (CMP x y))
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(Leq8 x y) -> (LessEqual (CMP (SignExt8to32 x) (SignExt8to32 y)))
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(Leq16 x y) -> (LessEqual (CMP (SignExt16to32 x) (SignExt16to32 y)))
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(Leq32 x y) -> (LessEqual (CMP x y))
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(Leq8U x y) -> (LessEqualU (CMP (ZeroExt8to32 x) (ZeroExt8to32 y)))
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(Leq16U x y) -> (LessEqualU (CMP (ZeroExt16to32 x) (ZeroExt16to32 y)))
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(Leq32U x y) -> (LessEqualU (CMP x y))
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(Greater8 x y) -> (GreaterThan (CMP (SignExt8to32 x) (SignExt8to32 y)))
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(Greater16 x y) -> (GreaterThan (CMP (SignExt16to32 x) (SignExt16to32 y)))
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(Greater32 x y) -> (GreaterThan (CMP x y))
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(Greater8U x y) -> (GreaterThanU (CMP (ZeroExt8to32 x) (ZeroExt8to32 y)))
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(Greater16U x y) -> (GreaterThanU (CMP (ZeroExt16to32 x) (ZeroExt16to32 y)))
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(Greater32U x y) -> (GreaterThanU (CMP x y))
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(Geq8 x y) -> (GreaterEqual (CMP (SignExt8to32 x) (SignExt8to32 y)))
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(Geq16 x y) -> (GreaterEqual (CMP (SignExt16to32 x) (SignExt16to32 y)))
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(Geq32 x y) -> (GreaterEqual (CMP x y))
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(Geq8U x y) -> (GreaterEqualU (CMP (ZeroExt8to32 x) (ZeroExt8to32 y)))
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(Geq16U x y) -> (GreaterEqualU (CMP (ZeroExt16to32 x) (ZeroExt16to32 y)))
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(Geq32U x y) -> (GreaterEqualU (CMP x y))
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(OffPtr [off] ptr) -> (ADD (MOVWconst <config.Frontend().TypeInt32()> [off]) ptr)
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(Addr {sym} base) -> (ADDconst {sym} base)
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(Load <t> ptr mem) && is32BitInt(t) -> (MOVWload ptr mem)
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(Load <t> ptr mem) && t.IsBoolean() -> (MOVBUload ptr mem)
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(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) -> (MOVBload ptr mem)
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(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) -> (MOVBUload ptr mem)
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(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) -> (MOVHload ptr mem)
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(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) -> (MOVHUload ptr mem)
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(Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) -> (MOVWload ptr mem)
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(Store [1] ptr val mem) -> (MOVBstore ptr val mem)
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(Store [2] ptr val mem) -> (MOVHstore ptr val mem)
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(Store [4] ptr val mem) -> (MOVWstore ptr val mem)
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(StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem)
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(ClosureCall [argwid] entry closure mem) -> (CALLclosure [argwid] entry closure mem)
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(DeferCall [argwid] mem) -> (CALLdefer [argwid] mem)
|
||||
(GoCall [argwid] mem) -> (CALLgo [argwid] mem)
|
||||
(InterCall [argwid] entry mem) -> (CALLinter [argwid] entry mem)
|
||||
|
||||
// Absorb LessThan into blocks.
|
||||
// checks
|
||||
(NilCheck ptr mem) -> (LoweredNilCheck ptr mem)
|
||||
|
||||
// Absorb pseudo-ops into blocks.
|
||||
(If (Equal cc) yes no) -> (EQ cc yes no)
|
||||
(If (NotEqual cc) yes no) -> (NE cc yes no)
|
||||
(If (LessThan cc) yes no) -> (LT cc yes no)
|
||||
(If (LessThanU cc) yes no) -> (ULT cc yes no)
|
||||
(If (LessEqual cc) yes no) -> (LE cc yes no)
|
||||
(If (LessEqualU cc) yes no) -> (ULE cc yes no)
|
||||
(If (GreaterThan cc) yes no) -> (GT cc yes no)
|
||||
(If (GreaterThanU cc) yes no) -> (UGT cc yes no)
|
||||
(If (GreaterEqual cc) yes no) -> (GE cc yes no)
|
||||
(If (GreaterEqualU cc) yes no) -> (UGE cc yes no)
|
||||
|
||||
(If cond yes no) -> (NE (CMPconst [0] cond) yes no)
|
||||
|
||||
// Absorb boolean tests into block
|
||||
(NE (CMPconst [0] (Equal cc)) yes no) -> (EQ cc yes no)
|
||||
(NE (CMPconst [0] (NotEqual cc)) yes no) -> (NE cc yes no)
|
||||
(NE (CMPconst [0] (LessThan cc)) yes no) -> (LT cc yes no)
|
||||
(NE (CMPconst [0] (LessThanU cc)) yes no) -> (ULT cc yes no)
|
||||
(NE (CMPconst [0] (LessEqual cc)) yes no) -> (LE cc yes no)
|
||||
(NE (CMPconst [0] (LessEqualU cc)) yes no) -> (ULE cc yes no)
|
||||
(NE (CMPconst [0] (GreaterThan cc)) yes no) -> (GT cc yes no)
|
||||
(NE (CMPconst [0] (GreaterThanU cc)) yes no) -> (UGT cc yes no)
|
||||
(NE (CMPconst [0] (GreaterEqual cc)) yes no) -> (GE cc yes no)
|
||||
(NE (CMPconst [0] (GreaterEqualU cc)) yes no) -> (UGE cc yes no)
|
||||
|
||||
// Optimizations
|
||||
|
||||
(ADD (MOVWconst [c]) x) -> (ADDconst [c] x)
|
||||
(ADD x (MOVWconst [c])) -> (ADDconst [c] x)
|
||||
|
||||
(MOVBload [off1] {sym1} (ADDconst [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
|
||||
(MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVBUload [off1] {sym1} (ADDconst [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
|
||||
(MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVHload [off1] {sym1} (ADDconst [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
|
||||
(MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVHUload [off1] {sym1} (ADDconst [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
|
||||
(MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVWload [off1] {sym1} (ADDconst [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) ->
|
||||
(MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
|
||||
|
||||
(MOVBstore [off1] {sym1} (ADDconst [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
|
||||
(MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
|
||||
(MOVHstore [off1] {sym1} (ADDconst [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
|
||||
(MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
|
||||
(MOVWstore [off1] {sym1} (ADDconst [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) ->
|
||||
(MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
|
||||
|
|
|
|||
|
|
@ -6,32 +6,150 @@
|
|||
|
||||
package main
|
||||
|
||||
import "strings"
|
||||
|
||||
// Notes:
|
||||
// - Integer types live in the low portion of registers. Upper portions are junk.
|
||||
// - Boolean types use the low-order byte of a register. 0=false, 1=true.
|
||||
// Upper bytes are junk.
|
||||
// - *const instructions may use a constant larger than the instuction can encode.
|
||||
// In this case the assembler expands to multiple instructions and uses tmp
|
||||
// register (R11).
|
||||
|
||||
// Suffixes encode the bit width of various instructions.
|
||||
// W (word) = 32 bit
|
||||
// H (half word) = 16 bit
|
||||
// HU = 16 bit unsigned
|
||||
// B (byte) = 8 bit
|
||||
// BU = 8 bit unsigned
|
||||
|
||||
var regNamesARM = []string{
|
||||
"R0",
|
||||
"R1",
|
||||
"R2",
|
||||
"R3",
|
||||
"R4",
|
||||
"R5",
|
||||
"R6",
|
||||
"R7",
|
||||
"R8",
|
||||
"R9",
|
||||
"R10", // g
|
||||
"R11", // tmp
|
||||
"R12",
|
||||
"SP", // aka R13
|
||||
"R14", // link
|
||||
"R15", // pc
|
||||
|
||||
// pseudo-registers
|
||||
"FLAGS",
|
||||
"SB",
|
||||
}
|
||||
|
||||
func init() {
|
||||
// Make map from reg names to reg integers.
|
||||
if len(regNamesARM) > 64 {
|
||||
panic("too many registers")
|
||||
}
|
||||
num := map[string]int{}
|
||||
for i, name := range regNamesARM {
|
||||
num[name] = i
|
||||
}
|
||||
buildReg := func(s string) regMask {
|
||||
m := regMask(0)
|
||||
for _, r := range strings.Split(s, " ") {
|
||||
if n, ok := num[r]; ok {
|
||||
m |= regMask(1) << uint(n)
|
||||
continue
|
||||
}
|
||||
panic("register " + r + " not found")
|
||||
}
|
||||
return m
|
||||
}
|
||||
|
||||
// Common individual register masks
|
||||
var (
|
||||
gp01 = regInfo{inputs: []regMask{}, outputs: []regMask{31}}
|
||||
gp11 = regInfo{inputs: []regMask{31}, outputs: []regMask{31}}
|
||||
gp21 = regInfo{inputs: []regMask{31, 31}, outputs: []regMask{31}}
|
||||
gp2flags = regInfo{inputs: []regMask{31, 31}, outputs: []regMask{32}}
|
||||
gpload = regInfo{inputs: []regMask{31}, outputs: []regMask{31}}
|
||||
gpstore = regInfo{inputs: []regMask{31, 31}, outputs: []regMask{}}
|
||||
flagsgp = regInfo{inputs: []regMask{32}, outputs: []regMask{31}}
|
||||
callerSave = regMask(15)
|
||||
gp = buildReg("R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12")
|
||||
gpsp = gp | buildReg("SP")
|
||||
gpspsb = gpsp | buildReg("SB")
|
||||
flags = buildReg("FLAGS")
|
||||
callerSave = gp
|
||||
)
|
||||
// Common regInfo
|
||||
var (
|
||||
gp01 = regInfo{inputs: []regMask{}, outputs: []regMask{gp}}
|
||||
gp11 = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}
|
||||
gp11sb = regInfo{inputs: []regMask{gpspsb}, outputs: []regMask{gp}}
|
||||
gp11flags = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp | flags}}
|
||||
gp21 = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp}}
|
||||
gp2flags = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp | flags}}
|
||||
gpload = regInfo{inputs: []regMask{gpspsb}, outputs: []regMask{gp}}
|
||||
gpstore = regInfo{inputs: []regMask{gpspsb, gp}, outputs: []regMask{}}
|
||||
flagsgp = regInfo{inputs: []regMask{gp | flags}, outputs: []regMask{gp}}
|
||||
)
|
||||
ops := []opData{
|
||||
{name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1
|
||||
{name: "ADDconst", argLength: 1, reg: gp11, asm: "ADD", aux: "SymOff"}, // arg0 + auxInt + aux.(*gc.Sym)
|
||||
// binary ops
|
||||
{name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1
|
||||
{name: "ADDconst", argLength: 1, reg: gp11sb, asm: "ADD", aux: "SymOff"}, // arg0 + auxInt + aux.(*gc.Sym)
|
||||
{name: "SUB", argLength: 2, reg: gp21, asm: "SUB"}, // arg0 - arg1
|
||||
{name: "SUBconst", argLength: 1, reg: gp11, asm: "SUB", aux: "Int32"}, // arg0 - auxInt
|
||||
{name: "RSB", argLength: 2, reg: gp21, asm: "RSB"}, // arg1 - arg0
|
||||
{name: "RSBconst", argLength: 1, reg: gp11, asm: "RSB", aux: "Int32"}, // auxInt - arg0
|
||||
|
||||
{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1
|
||||
{name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int32"}, // arg0 & auxInt
|
||||
{name: "OR", argLength: 2, reg: gp21, asm: "ORR", commutative: true}, // arg0 | arg1
|
||||
{name: "ORconst", argLength: 1, reg: gp11, asm: "ORR", aux: "Int32"}, // arg0 | auxInt
|
||||
{name: "XOR", argLength: 2, reg: gp21, asm: "EOR", commutative: true}, // arg0 ^ arg1
|
||||
{name: "XORconst", argLength: 1, reg: gp11, asm: "EOR", aux: "Int32"}, // arg0 ^ auxInt
|
||||
{name: "BIC", argLength: 2, reg: gp21, asm: "BIC"}, // arg0 &^ arg1
|
||||
{name: "BICconst", argLength: 1, reg: gp11, asm: "BIC", aux: "Int32"}, // arg0 &^ auxInt
|
||||
|
||||
{name: "CMP", argLength: 2, reg: gp2flags, asm: "CMP", typ: "Flags"}, // arg0 compare to arg1
|
||||
{name: "CMPconst", argLength: 1, reg: gp11flags, asm: "CMP", aux: "Int32", typ: "Flags"}, // arg0 compare to auxInt
|
||||
{name: "CMN", argLength: 2, reg: gp2flags, asm: "CMN", typ: "Flags"}, // arg0 compare to -arg1
|
||||
{name: "CMNconst", argLength: 1, reg: gp11flags, asm: "CMN", aux: "Int32", typ: "Flags"}, // arg0 compare to -auxInt
|
||||
{name: "TST", argLength: 2, reg: gp2flags, asm: "TST", typ: "Flags", commutative: true}, // arg0 & arg1 compare to 0
|
||||
{name: "TSTconst", argLength: 1, reg: gp11flags, asm: "TST", aux: "Int32", typ: "Flags"}, // arg0 & auxInt compare to 0
|
||||
{name: "TEQ", argLength: 2, reg: gp2flags, asm: "TEQ", typ: "Flags", commutative: true}, // arg0 ^ arg1 compare to 0
|
||||
{name: "TEQconst", argLength: 1, reg: gp11flags, asm: "TEQ", aux: "Int32", typ: "Flags"}, // arg0 ^ auxInt compare to 0
|
||||
|
||||
{name: "MOVWconst", argLength: 0, reg: gp01, aux: "Int32", asm: "MOVW", rematerializeable: true}, // 32 low bits of auxint
|
||||
|
||||
{name: "CMP", argLength: 2, reg: gp2flags, asm: "CMP", typ: "Flags"}, // arg0 compare to arg1
|
||||
|
||||
{name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
|
||||
{name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB"}, // store 1 byte of arg1 to arg0 + auxInt + aux. arg2=mem.
|
||||
{name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH"}, // store 2 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
|
||||
{name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
|
||||
|
||||
{name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff"}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
|
||||
{name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVBS"}, // move from arg0, sign-extended from byte
|
||||
{name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte
|
||||
{name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVHS"}, // move from arg0, sign-extended from half
|
||||
{name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half
|
||||
|
||||
{name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "SymOff"}, // call static function aux.(*gc.Sym). arg0=mem, auxint=argsize, returns mem
|
||||
{name: "CALLclosure", argLength: 3, reg: regInfo{[]regMask{gpsp, buildReg("R7"), 0}, callerSave, nil}, aux: "Int64"}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
|
||||
{name: "CALLdefer", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call deferproc. arg0=mem, auxint=argsize, returns mem
|
||||
{name: "CALLgo", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "Int64"}, // call newproc. arg0=mem, auxint=argsize, returns mem
|
||||
{name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "Int64"}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
|
||||
|
||||
// pseudo-ops
|
||||
{name: "LessThan", argLength: 1, reg: flagsgp}, // bool, 1 flags encode x<y 0 otherwise.
|
||||
{name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpsp}, clobbers: flags}}, // panic if arg0 is nil. arg1=mem.
|
||||
|
||||
{name: "Equal", argLength: 1, reg: flagsgp}, // bool, true flags encode x==y false otherwise.
|
||||
{name: "NotEqual", argLength: 1, reg: flagsgp}, // bool, true flags encode x!=y false otherwise.
|
||||
{name: "LessThan", argLength: 1, reg: flagsgp}, // bool, true flags encode signed x<y false otherwise.
|
||||
{name: "LessEqual", argLength: 1, reg: flagsgp}, // bool, true flags encode signed x<=y false otherwise.
|
||||
{name: "GreaterThan", argLength: 1, reg: flagsgp}, // bool, true flags encode signed x>y false otherwise.
|
||||
{name: "GreaterEqual", argLength: 1, reg: flagsgp}, // bool, true flags encode signed x>=y false otherwise.
|
||||
{name: "LessThanU", argLength: 1, reg: flagsgp}, // bool, true flags encode unsigned x<y false otherwise.
|
||||
{name: "LessEqualU", argLength: 1, reg: flagsgp}, // bool, true flags encode unsigned x<=y false otherwise.
|
||||
{name: "GreaterThanU", argLength: 1, reg: flagsgp}, // bool, true flags encode unsigned x>y false otherwise.
|
||||
{name: "GreaterEqualU", argLength: 1, reg: flagsgp}, // bool, true flags encode unsigned x>=y false otherwise.
|
||||
}
|
||||
|
||||
blocks := []blockData{
|
||||
|
|
@ -47,22 +165,12 @@ func init() {
|
|||
{name: "UGE"},
|
||||
}
|
||||
|
||||
regNames := []string{
|
||||
"R0",
|
||||
"R1",
|
||||
"R2",
|
||||
"R3",
|
||||
"SP",
|
||||
"FLAGS",
|
||||
"SB",
|
||||
}
|
||||
|
||||
archs = append(archs, arch{
|
||||
name: "ARM",
|
||||
pkg: "cmd/internal/obj/arm",
|
||||
genfile: "../../arm/ssa.go",
|
||||
ops: ops,
|
||||
blocks: blocks,
|
||||
regnames: regNames,
|
||||
regnames: regNamesARM,
|
||||
})
|
||||
}
|
||||
|
|
|
|||
|
|
@ -326,15 +326,15 @@ var genericOps = []opData{
|
|||
|
||||
// Conversions: signed extensions, zero (unsigned) extensions, truncations
|
||||
{name: "SignExt8to16", argLength: 1, typ: "Int16"},
|
||||
{name: "SignExt8to32", argLength: 1},
|
||||
{name: "SignExt8to32", argLength: 1, typ: "Int32"},
|
||||
{name: "SignExt8to64", argLength: 1},
|
||||
{name: "SignExt16to32", argLength: 1},
|
||||
{name: "SignExt16to32", argLength: 1, typ: "Int32"},
|
||||
{name: "SignExt16to64", argLength: 1},
|
||||
{name: "SignExt32to64", argLength: 1},
|
||||
{name: "ZeroExt8to16", argLength: 1, typ: "UInt16"},
|
||||
{name: "ZeroExt8to32", argLength: 1},
|
||||
{name: "ZeroExt8to32", argLength: 1, typ: "UInt32"},
|
||||
{name: "ZeroExt8to64", argLength: 1},
|
||||
{name: "ZeroExt16to32", argLength: 1},
|
||||
{name: "ZeroExt16to32", argLength: 1, typ: "UInt32"},
|
||||
{name: "ZeroExt16to64", argLength: 1},
|
||||
{name: "ZeroExt32to64", argLength: 1},
|
||||
{name: "Trunc16to8", argLength: 1},
|
||||
|
|
|
|||
|
|
@ -325,12 +325,55 @@ const (
|
|||
|
||||
OpARMADD
|
||||
OpARMADDconst
|
||||
OpARMMOVWconst
|
||||
OpARMSUB
|
||||
OpARMSUBconst
|
||||
OpARMRSB
|
||||
OpARMRSBconst
|
||||
OpARMAND
|
||||
OpARMANDconst
|
||||
OpARMOR
|
||||
OpARMORconst
|
||||
OpARMXOR
|
||||
OpARMXORconst
|
||||
OpARMBIC
|
||||
OpARMBICconst
|
||||
OpARMCMP
|
||||
OpARMCMPconst
|
||||
OpARMCMN
|
||||
OpARMCMNconst
|
||||
OpARMTST
|
||||
OpARMTSTconst
|
||||
OpARMTEQ
|
||||
OpARMTEQconst
|
||||
OpARMMOVWconst
|
||||
OpARMMOVBload
|
||||
OpARMMOVBUload
|
||||
OpARMMOVHload
|
||||
OpARMMOVHUload
|
||||
OpARMMOVWload
|
||||
OpARMMOVBstore
|
||||
OpARMMOVHstore
|
||||
OpARMMOVWstore
|
||||
OpARMMOVBreg
|
||||
OpARMMOVBUreg
|
||||
OpARMMOVHreg
|
||||
OpARMMOVHUreg
|
||||
OpARMCALLstatic
|
||||
OpARMCALLclosure
|
||||
OpARMCALLdefer
|
||||
OpARMCALLgo
|
||||
OpARMCALLinter
|
||||
OpARMLoweredNilCheck
|
||||
OpARMEqual
|
||||
OpARMNotEqual
|
||||
OpARMLessThan
|
||||
OpARMLessEqual
|
||||
OpARMGreaterThan
|
||||
OpARMGreaterEqual
|
||||
OpARMLessThanU
|
||||
OpARMLessEqualU
|
||||
OpARMGreaterThanU
|
||||
OpARMGreaterEqualU
|
||||
|
||||
OpAdd8
|
||||
OpAdd16
|
||||
|
|
@ -3804,11 +3847,11 @@ var opcodeTable = [...]opInfo{
|
|||
asm: arm.AADD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 31}, // R0 R1 R2 R3 SP
|
||||
{1, 31}, // R0 R1 R2 R3 SP
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
31, // R0 R1 R2 R3 SP
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -3819,10 +3862,295 @@ var opcodeTable = [...]opInfo{
|
|||
asm: arm.AADD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 31}, // R0 R1 R2 R3 SP
|
||||
{0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
|
||||
},
|
||||
outputs: []regMask{
|
||||
31, // R0 R1 R2 R3 SP
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SUB",
|
||||
argLen: 2,
|
||||
asm: arm.ASUB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SUBconst",
|
||||
auxType: auxInt32,
|
||||
argLen: 1,
|
||||
asm: arm.ASUB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "RSB",
|
||||
argLen: 2,
|
||||
asm: arm.ARSB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "RSBconst",
|
||||
auxType: auxInt32,
|
||||
argLen: 1,
|
||||
asm: arm.ARSB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "AND",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
asm: arm.AAND,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ANDconst",
|
||||
auxType: auxInt32,
|
||||
argLen: 1,
|
||||
asm: arm.AAND,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "OR",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
asm: arm.AORR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ORconst",
|
||||
auxType: auxInt32,
|
||||
argLen: 1,
|
||||
asm: arm.AORR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "XOR",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
asm: arm.AEOR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "XORconst",
|
||||
auxType: auxInt32,
|
||||
argLen: 1,
|
||||
asm: arm.AEOR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "BIC",
|
||||
argLen: 2,
|
||||
asm: arm.ABIC,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "BICconst",
|
||||
auxType: auxInt32,
|
||||
argLen: 1,
|
||||
asm: arm.ABIC,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMP",
|
||||
argLen: 2,
|
||||
asm: arm.ACMP,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
70655, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMPconst",
|
||||
auxType: auxInt32,
|
||||
argLen: 1,
|
||||
asm: arm.ACMP,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
70655, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMN",
|
||||
argLen: 2,
|
||||
asm: arm.ACMN,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
70655, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMNconst",
|
||||
auxType: auxInt32,
|
||||
argLen: 1,
|
||||
asm: arm.ACMN,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
70655, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "TST",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
asm: arm.ATST,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
70655, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "TSTconst",
|
||||
auxType: auxInt32,
|
||||
argLen: 1,
|
||||
asm: arm.ATST,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
70655, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "TEQ",
|
||||
argLen: 2,
|
||||
commutative: true,
|
||||
asm: arm.ATEQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
70655, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "TEQconst",
|
||||
auxType: auxInt32,
|
||||
argLen: 1,
|
||||
asm: arm.ATEQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
70655, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -3834,21 +4162,63 @@ var opcodeTable = [...]opInfo{
|
|||
asm: arm.AMOVW,
|
||||
reg: regInfo{
|
||||
outputs: []regMask{
|
||||
31, // R0 R1 R2 R3 SP
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMP",
|
||||
argLen: 2,
|
||||
asm: arm.ACMP,
|
||||
name: "MOVBload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: arm.AMOVB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 31}, // R0 R1 R2 R3 SP
|
||||
{1, 31}, // R0 R1 R2 R3 SP
|
||||
{0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
|
||||
},
|
||||
outputs: []regMask{
|
||||
32, // FLAGS
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVBUload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: arm.AMOVBU,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVHload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: arm.AMOVH,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVHUload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: arm.AMOVHU,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -3859,10 +4229,34 @@ var opcodeTable = [...]opInfo{
|
|||
asm: arm.AMOVW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 31}, // R0 R1 R2 R3 SP
|
||||
{0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
|
||||
},
|
||||
outputs: []regMask{
|
||||
31, // R0 R1 R2 R3 SP
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVBstore",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
asm: arm.AMOVB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVHstore",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
asm: arm.AMOVH,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -3873,8 +4267,60 @@ var opcodeTable = [...]opInfo{
|
|||
asm: arm.AMOVW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 31}, // R0 R1 R2 R3 SP
|
||||
{1, 31}, // R0 R1 R2 R3 SP
|
||||
{1, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
{0, 144383}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP SB
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVBreg",
|
||||
argLen: 1,
|
||||
asm: arm.AMOVBS,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVBUreg",
|
||||
argLen: 1,
|
||||
asm: arm.AMOVBU,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVHreg",
|
||||
argLen: 1,
|
||||
asm: arm.AMOVHS,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVHUreg",
|
||||
argLen: 1,
|
||||
asm: arm.AMOVHU,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -3883,7 +4329,80 @@ var opcodeTable = [...]opInfo{
|
|||
auxType: auxSymOff,
|
||||
argLen: 1,
|
||||
reg: regInfo{
|
||||
clobbers: 15, // R0 R1 R2 R3
|
||||
clobbers: 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CALLclosure",
|
||||
auxType: auxInt64,
|
||||
argLen: 3,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 128}, // R7
|
||||
{0, 13311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP
|
||||
},
|
||||
clobbers: 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CALLdefer",
|
||||
auxType: auxInt64,
|
||||
argLen: 1,
|
||||
reg: regInfo{
|
||||
clobbers: 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CALLgo",
|
||||
auxType: auxInt64,
|
||||
argLen: 1,
|
||||
reg: regInfo{
|
||||
clobbers: 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CALLinter",
|
||||
auxType: auxInt64,
|
||||
argLen: 2,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 5119}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
clobbers: 5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "LoweredNilCheck",
|
||||
argLen: 2,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 13311}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP
|
||||
},
|
||||
clobbers: 65536, // FLAGS
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "Equal",
|
||||
argLen: 1,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 70655}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "NotEqual",
|
||||
argLen: 1,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 70655}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
|
|
@ -3891,10 +4410,94 @@ var opcodeTable = [...]opInfo{
|
|||
argLen: 1,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 32}, // FLAGS
|
||||
{0, 70655}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
outputs: []regMask{
|
||||
31, // R0 R1 R2 R3 SP
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "LessEqual",
|
||||
argLen: 1,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 70655}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "GreaterThan",
|
||||
argLen: 1,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 70655}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "GreaterEqual",
|
||||
argLen: 1,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 70655}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "LessThanU",
|
||||
argLen: 1,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 70655}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "LessEqualU",
|
||||
argLen: 1,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 70655}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "GreaterThanU",
|
||||
argLen: 1,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 70655}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "GreaterEqualU",
|
||||
argLen: 1,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 70655}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 FLAGS
|
||||
},
|
||||
outputs: []regMask{
|
||||
5119, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12
|
||||
},
|
||||
},
|
||||
},
|
||||
|
|
@ -5429,7 +6032,18 @@ var registersARM = [...]Register{
|
|||
{1, "R1"},
|
||||
{2, "R2"},
|
||||
{3, "R3"},
|
||||
{4, "SP"},
|
||||
{5, "FLAGS"},
|
||||
{6, "SB"},
|
||||
{4, "R4"},
|
||||
{5, "R5"},
|
||||
{6, "R6"},
|
||||
{7, "R7"},
|
||||
{8, "R8"},
|
||||
{9, "R9"},
|
||||
{10, "R10"},
|
||||
{11, "R11"},
|
||||
{12, "R12"},
|
||||
{13, "SP"},
|
||||
{14, "R14"},
|
||||
{15, "R15"},
|
||||
{16, "FLAGS"},
|
||||
{17, "SB"},
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
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Add table
Add a link
Reference in a new issue