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[dev.simd] cmd/compile: make simd regmask naming more like existing conventions

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Paired with simdgen CL 682937

Change-Id: Ia826f643ece23bf4c7903dffe2fc15e39fbd5577
Reviewed-on: https://go-review.googlesource.com/c/go/+/683115
Reviewed-by: Junyang Shao <shaojunyang@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
This commit is contained in:
David Chase 2025-06-20 17:09:32 -04:00
parent 1fa4bcfcda
commit e32488003d
3 changed files with 370 additions and 370 deletions
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14
src/cmd/compile/internal/amd64/simdssa.go
View file

@ -509,7 +509,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPXORQMasked128,
ssa.OpAMD64VPXORQMasked256,
ssa.OpAMD64VPXORQMasked512:
p = simdFp2k1fp1(s, v)
p = simdFp2kfp(s, v)
case ssa.OpAMD64VPABSBMasked128,
ssa.OpAMD64VPABSBMasked256,
@ -553,7 +553,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VSQRTPDMasked128,
ssa.OpAMD64VSQRTPDMasked256,
ssa.OpAMD64VSQRTPDMasked512:
p = simdFp1k1fp1(s, v)
p = simdFpkfp(s, v)
case ssa.OpAMD64VROUNDPS128,
ssa.OpAMD64VROUNDPS256,
@ -585,7 +585,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VREDUCEPDMasked128,
ssa.OpAMD64VREDUCEPDMasked256,
ssa.OpAMD64VREDUCEPDMasked512:
p = simdFp1k1fp1Imm8(s, v)
p = simdFpkfpImm8(s, v)
case ssa.OpAMD64VDPPD128,
ssa.OpAMD64VCMPPS128,
@ -620,7 +620,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPCMPD128,
ssa.OpAMD64VPCMPD256,
ssa.OpAMD64VPCMPQ256:
p = simdFp2k1Imm8(s, v)
p = simdFp2kImm8(s, v)
case ssa.OpAMD64VCMPPSMasked128,
ssa.OpAMD64VCMPPSMasked256,
@ -652,7 +652,7 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPCMPUQMasked128,
ssa.OpAMD64VPCMPUQMasked256,
ssa.OpAMD64VPCMPUQMasked512:
p = simdFp2k1k1Imm8(s, v)
p = simdFp2kkImm8(s, v)
case ssa.OpAMD64VFMADD213PS128,
ssa.OpAMD64VFMADD213PS256,
@ -716,13 +716,13 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPDPBUSDMasked128,
ssa.OpAMD64VPDPBUSDMasked256,
ssa.OpAMD64VPDPBUSDMasked512:
p = simdFp3k1fp1ResultInArg0(s, v)
p = simdFp3kfpResultInArg0(s, v)
case ssa.OpAMD64VPINSRB128,
ssa.OpAMD64VPINSRW128,
ssa.OpAMD64VPINSRD128,
ssa.OpAMD64VPINSRQ128:
p = simdFp1gp1fp1Imm8(s, v)
p = simdFpgpfpImm8(s, v)
default:
// Unknown reg shape

22
src/cmd/compile/internal/amd64/ssa.go
View file

@ -1541,13 +1541,13 @@ func simdFp21(s *ssagen.State, v *ssa.Value) *obj.Prog {
}
// Example instruction: VPCMPEQW Z26, Z30, K4
func simdFp2k1(s *ssagen.State, v *ssa.Value) *obj.Prog {
func simdFp2k(s *ssagen.State, v *ssa.Value) *obj.Prog {
// simdReg handles mask and vector registers altogether
return simdFp21(s, v)
}
// Example instruction: VPMINUQ X21, X3, K3, X31
func simdFp2k1fp1(s *ssagen.State, v *ssa.Value) *obj.Prog {
func simdFp2kfp(s *ssagen.State, v *ssa.Value) *obj.Prog {
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_REG
p.From.Reg = simdReg(v.Args[1])
@ -1564,12 +1564,12 @@ func simdFp2k1fp1(s *ssagen.State, v *ssa.Value) *obj.Prog {
}
// Example instruction: VPCMPEQW Z26, Z30, K1, K4
func simdFp2k1k1(s *ssagen.State, v *ssa.Value) *obj.Prog {
return simdFp2k1fp1(s, v)
func simdFp2kk(s *ssagen.State, v *ssa.Value) *obj.Prog {
return simdFp2kfp(s, v)
}
// Example instruction: VPOPCNTB X14, K4, X16
func simdFp1k1fp1(s *ssagen.State, v *ssa.Value) *obj.Prog {
func simdFpkfp(s *ssagen.State, v *ssa.Value) *obj.Prog {
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_REG
p.From.Reg = simdReg(v.Args[0])
@ -1595,7 +1595,7 @@ func simdFp11Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
}
// Example instruction: VREDUCEPD $126, X1, K3, X31
func simdFp1k1fp1Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
func simdFpkfpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
p := s.Prog(v.Op.Asm())
imm := v.AuxInt
if imm < 0 || imm > 255 {
@ -1627,7 +1627,7 @@ func simdFp21Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
}
// Example instruction: VPINSRB $3, DX, X0, X0
func simdFp1gp1fp1Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
func simdFpgpfpImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
p := s.Prog(v.Op.Asm())
imm := v.AuxInt
if imm < 0 || imm > 255 {
@ -1643,12 +1643,12 @@ func simdFp1gp1fp1Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
}
// Example instruction: VPCMPD $1, Z1, Z2, K1
func simdFp2k1Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
func simdFp2kImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
return simdFp21Imm8(s, v)
}
// Example instruction: VPCMPD $1, Z1, Z2, K2, K1
func simdFp2k1k1Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
func simdFp2kkImm8(s *ssagen.State, v *ssa.Value) *obj.Prog {
p := s.Prog(v.Op.Asm())
imm := v.AuxInt
if imm < 0 || imm > 255 {
@ -1676,7 +1676,7 @@ func simdFp31ResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog {
}
// Example instruction: VFMADD213PD Z2, Z1, K1, Z0
func simdFp3k1fp1ResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog {
func simdFp3kfpResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog {
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_REG
p.From.Reg = simdReg(v.Args[2])
@ -1700,7 +1700,7 @@ func simdFp31(s *ssagen.State, v *ssa.Value) *obj.Prog {
}
// Currently unused
func simdFp3k1fp1(s *ssagen.State, v *ssa.Value) *obj.Prog {
func simdFp3kfp(s *ssagen.State, v *ssa.Value) *obj.Prog {
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_REG
p.From.Reg = simdReg(v.Args[2])

704
src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
View file

@ -1,7 +1,7 @@
// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT.
package main
func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1, fp1gp1fp1 regInfo) []opData {
func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp regInfo) []opData {
return []opData{
{name: "VADDPS512", argLength: 2, reg: fp21, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDPS512", argLength: 2, reg: fp21, asm: "VANDPS", commutative: true, typ: "Vec512", resultInArg0: false},
@ -12,23 +12,23 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VFMADD213PS512", argLength: 3, reg: fp31, asm: "VFMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMADDSUB213PS512", argLength: 3, reg: fp31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMSUBADD213PS512", argLength: 3, reg: fp31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VADDPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VANDPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDNPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VANDNPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRCP14PSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRSQRT14PSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VDIVPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VFMADD213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMADDSUB213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMSUBADD213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VMAXPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMAXPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMINPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMULPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSCALEFPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VSCALEFPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VORPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VORPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSQRTPSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VSQRTPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VSUBPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VSUBPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VXORPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VXORPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VADDPSMasked512", argLength: 3, reg: fp2kfp, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDPSMasked512", argLength: 3, reg: fp2kfp, asm: "VANDPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDNPSMasked512", argLength: 3, reg: fp2kfp, asm: "VANDNPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRCP14PSMasked512", argLength: 2, reg: fpkfp, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRSQRT14PSMasked512", argLength: 2, reg: fpkfp, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VDIVPSMasked512", argLength: 3, reg: fp2kfp, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VFMADD213PSMasked512", argLength: 4, reg: fp3kfp, asm: "VFMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMADDSUB213PSMasked512", argLength: 4, reg: fp3kfp, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMSUBADD213PSMasked512", argLength: 4, reg: fp3kfp, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VMAXPSMasked512", argLength: 3, reg: fp2kfp, asm: "VMAXPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMINPSMasked512", argLength: 3, reg: fp2kfp, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMULPSMasked512", argLength: 3, reg: fp2kfp, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSCALEFPSMasked512", argLength: 3, reg: fp2kfp, asm: "VSCALEFPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VORPSMasked512", argLength: 3, reg: fp2kfp, asm: "VORPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSQRTPSMasked512", argLength: 2, reg: fpkfp, asm: "VSQRTPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VSUBPSMasked512", argLength: 3, reg: fp2kfp, asm: "VSUBPS", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VXORPSMasked512", argLength: 3, reg: fp2kfp, asm: "VXORPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMAXPS512", argLength: 2, reg: fp21, asm: "VMAXPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMINPS512", argLength: 2, reg: fp21, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMULPS512", argLength: 2, reg: fp21, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false},
@ -47,23 +47,23 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VFMADD213PS128", argLength: 3, reg: fp31, asm: "VFMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMADDSUB213PS128", argLength: 3, reg: fp31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMSUBADD213PS128", argLength: 3, reg: fp31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VADDPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VADDPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VANDPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDNPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VANDNPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRCP14PSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRSQRT14PSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VDIVPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VFMADD213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMADDSUB213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMSUBADD213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VMAXPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMAXPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMINPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMULPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSCALEFPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VSCALEFPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VORPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VORPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSQRTPSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VSUBPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VXORPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VXORPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VADDPSMasked128", argLength: 3, reg: fp2kfp, asm: "VADDPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDPSMasked128", argLength: 3, reg: fp2kfp, asm: "VANDPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDNPSMasked128", argLength: 3, reg: fp2kfp, asm: "VANDNPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRCP14PSMasked128", argLength: 2, reg: fpkfp, asm: "VRCP14PS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRSQRT14PSMasked128", argLength: 2, reg: fpkfp, asm: "VRSQRT14PS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VDIVPSMasked128", argLength: 3, reg: fp2kfp, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VFMADD213PSMasked128", argLength: 4, reg: fp3kfp, asm: "VFMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMADDSUB213PSMasked128", argLength: 4, reg: fp3kfp, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMSUBADD213PSMasked128", argLength: 4, reg: fp3kfp, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VMAXPSMasked128", argLength: 3, reg: fp2kfp, asm: "VMAXPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMINPSMasked128", argLength: 3, reg: fp2kfp, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMULPSMasked128", argLength: 3, reg: fp2kfp, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSCALEFPSMasked128", argLength: 3, reg: fp2kfp, asm: "VSCALEFPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VORPSMasked128", argLength: 3, reg: fp2kfp, asm: "VORPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSQRTPSMasked128", argLength: 2, reg: fpkfp, asm: "VSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VSUBPSMasked128", argLength: 3, reg: fp2kfp, asm: "VSUBPS", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VXORPSMasked128", argLength: 3, reg: fp2kfp, asm: "VXORPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMAXPS128", argLength: 2, reg: fp21, asm: "VMAXPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMINPS128", argLength: 2, reg: fp21, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMULPS128", argLength: 2, reg: fp21, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false},
@ -84,23 +84,23 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VFMADD213PS256", argLength: 3, reg: fp31, asm: "VFMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMADDSUB213PS256", argLength: 3, reg: fp31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMSUBADD213PS256", argLength: 3, reg: fp31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VADDPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VADDPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VANDPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDNPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VANDNPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRCP14PSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRSQRT14PSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VDIVPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VDIVPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VFMADD213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMADDSUB213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMSUBADD213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VMAXPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMAXPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMINPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMULPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSCALEFPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VSCALEFPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VORPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VORPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSQRTPSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VSUBPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VXORPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VXORPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VADDPSMasked256", argLength: 3, reg: fp2kfp, asm: "VADDPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDPSMasked256", argLength: 3, reg: fp2kfp, asm: "VANDPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDNPSMasked256", argLength: 3, reg: fp2kfp, asm: "VANDNPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRCP14PSMasked256", argLength: 2, reg: fpkfp, asm: "VRCP14PS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRSQRT14PSMasked256", argLength: 2, reg: fpkfp, asm: "VRSQRT14PS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VDIVPSMasked256", argLength: 3, reg: fp2kfp, asm: "VDIVPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VFMADD213PSMasked256", argLength: 4, reg: fp3kfp, asm: "VFMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMADDSUB213PSMasked256", argLength: 4, reg: fp3kfp, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMSUBADD213PSMasked256", argLength: 4, reg: fp3kfp, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VMAXPSMasked256", argLength: 3, reg: fp2kfp, asm: "VMAXPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMINPSMasked256", argLength: 3, reg: fp2kfp, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMULPSMasked256", argLength: 3, reg: fp2kfp, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSCALEFPSMasked256", argLength: 3, reg: fp2kfp, asm: "VSCALEFPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VORPSMasked256", argLength: 3, reg: fp2kfp, asm: "VORPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSQRTPSMasked256", argLength: 2, reg: fpkfp, asm: "VSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VSUBPSMasked256", argLength: 3, reg: fp2kfp, asm: "VSUBPS", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VXORPSMasked256", argLength: 3, reg: fp2kfp, asm: "VXORPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMAXPS256", argLength: 2, reg: fp21, asm: "VMAXPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMINPS256", argLength: 2, reg: fp21, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMULPS256", argLength: 2, reg: fp21, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false},
@ -121,23 +121,23 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VFMADD213PD128", argLength: 3, reg: fp31, asm: "VFMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMADDSUB213PD128", argLength: 3, reg: fp31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMSUBADD213PD128", argLength: 3, reg: fp31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VADDPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VANDPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDNPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VANDNPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRCP14PDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRSQRT14PDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VDIVPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VFMADD213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMADDSUB213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMSUBADD213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VMAXPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMAXPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMINPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMULPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSCALEFPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VSCALEFPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VORPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VORPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSQRTPDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VSQRTPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VSUBPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VXORPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VXORPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VADDPDMasked128", argLength: 3, reg: fp2kfp, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDPDMasked128", argLength: 3, reg: fp2kfp, asm: "VANDPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VANDNPDMasked128", argLength: 3, reg: fp2kfp, asm: "VANDNPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRCP14PDMasked128", argLength: 2, reg: fpkfp, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRSQRT14PDMasked128", argLength: 2, reg: fpkfp, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VDIVPDMasked128", argLength: 3, reg: fp2kfp, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VFMADD213PDMasked128", argLength: 4, reg: fp3kfp, asm: "VFMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMADDSUB213PDMasked128", argLength: 4, reg: fp3kfp, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VFMSUBADD213PDMasked128", argLength: 4, reg: fp3kfp, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VMAXPDMasked128", argLength: 3, reg: fp2kfp, asm: "VMAXPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMINPDMasked128", argLength: 3, reg: fp2kfp, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMULPDMasked128", argLength: 3, reg: fp2kfp, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSCALEFPDMasked128", argLength: 3, reg: fp2kfp, asm: "VSCALEFPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VORPDMasked128", argLength: 3, reg: fp2kfp, asm: "VORPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VSQRTPDMasked128", argLength: 2, reg: fpkfp, asm: "VSQRTPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VSUBPDMasked128", argLength: 3, reg: fp2kfp, asm: "VSUBPD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VXORPDMasked128", argLength: 3, reg: fp2kfp, asm: "VXORPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMAXPD128", argLength: 2, reg: fp21, asm: "VMAXPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMINPD128", argLength: 2, reg: fp21, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VMULPD128", argLength: 2, reg: fp21, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false},
@ -158,23 +158,23 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VFMADD213PD256", argLength: 3, reg: fp31, asm: "VFMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMADDSUB213PD256", argLength: 3, reg: fp31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMSUBADD213PD256", argLength: 3, reg: fp31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VADDPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VANDPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDNPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VANDNPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRCP14PDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRSQRT14PDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VDIVPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VFMADD213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMADDSUB213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMSUBADD213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VMAXPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMAXPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMINPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMULPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSCALEFPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VSCALEFPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VORPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VORPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSQRTPDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VSQRTPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VSUBPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VXORPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VXORPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VADDPDMasked256", argLength: 3, reg: fp2kfp, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDPDMasked256", argLength: 3, reg: fp2kfp, asm: "VANDPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VANDNPDMasked256", argLength: 3, reg: fp2kfp, asm: "VANDNPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRCP14PDMasked256", argLength: 2, reg: fpkfp, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRSQRT14PDMasked256", argLength: 2, reg: fpkfp, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VDIVPDMasked256", argLength: 3, reg: fp2kfp, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VFMADD213PDMasked256", argLength: 4, reg: fp3kfp, asm: "VFMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMADDSUB213PDMasked256", argLength: 4, reg: fp3kfp, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VFMSUBADD213PDMasked256", argLength: 4, reg: fp3kfp, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VMAXPDMasked256", argLength: 3, reg: fp2kfp, asm: "VMAXPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMINPDMasked256", argLength: 3, reg: fp2kfp, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMULPDMasked256", argLength: 3, reg: fp2kfp, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSCALEFPDMasked256", argLength: 3, reg: fp2kfp, asm: "VSCALEFPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VORPDMasked256", argLength: 3, reg: fp2kfp, asm: "VORPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VSQRTPDMasked256", argLength: 2, reg: fpkfp, asm: "VSQRTPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VSUBPDMasked256", argLength: 3, reg: fp2kfp, asm: "VSUBPD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VXORPDMasked256", argLength: 3, reg: fp2kfp, asm: "VXORPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMAXPD256", argLength: 2, reg: fp21, asm: "VMAXPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMINPD256", argLength: 2, reg: fp21, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VMULPD256", argLength: 2, reg: fp21, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false},
@ -194,23 +194,23 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VFMADD213PD512", argLength: 3, reg: fp31, asm: "VFMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMADDSUB213PD512", argLength: 3, reg: fp31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMSUBADD213PD512", argLength: 3, reg: fp31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VADDPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VADDPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VANDPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDNPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VANDNPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRCP14PDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRSQRT14PDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VDIVPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VFMADD213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMADDSUB213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMSUBADD213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VMAXPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMAXPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMINPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMINPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMULPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMULPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSCALEFPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VSCALEFPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VORPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VORPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSQRTPDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VSQRTPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VSUBPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VSUBPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VXORPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VXORPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VADDPDMasked512", argLength: 3, reg: fp2kfp, asm: "VADDPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDPDMasked512", argLength: 3, reg: fp2kfp, asm: "VANDPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VANDNPDMasked512", argLength: 3, reg: fp2kfp, asm: "VANDNPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRCP14PDMasked512", argLength: 2, reg: fpkfp, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRSQRT14PDMasked512", argLength: 2, reg: fpkfp, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VDIVPDMasked512", argLength: 3, reg: fp2kfp, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VFMADD213PDMasked512", argLength: 4, reg: fp3kfp, asm: "VFMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMADDSUB213PDMasked512", argLength: 4, reg: fp3kfp, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VFMSUBADD213PDMasked512", argLength: 4, reg: fp3kfp, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VMAXPDMasked512", argLength: 3, reg: fp2kfp, asm: "VMAXPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMINPDMasked512", argLength: 3, reg: fp2kfp, asm: "VMINPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMULPDMasked512", argLength: 3, reg: fp2kfp, asm: "VMULPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSCALEFPDMasked512", argLength: 3, reg: fp2kfp, asm: "VSCALEFPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VORPDMasked512", argLength: 3, reg: fp2kfp, asm: "VORPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VSQRTPDMasked512", argLength: 2, reg: fpkfp, asm: "VSQRTPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VSUBPDMasked512", argLength: 3, reg: fp2kfp, asm: "VSUBPD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VXORPDMasked512", argLength: 3, reg: fp2kfp, asm: "VXORPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMAXPD512", argLength: 2, reg: fp21, asm: "VMAXPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMINPD512", argLength: 2, reg: fp21, asm: "VMINPD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VMULPD512", argLength: 2, reg: fp21, asm: "VMULPD", commutative: true, typ: "Vec512", resultInArg0: false},
@ -223,17 +223,17 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VPADDW256", argLength: 2, reg: fp21, asm: "VPADDW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPCMPEQW256", argLength: 2, reg: fp21, asm: "VPCMPEQW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPCMPGTW256", argLength: 2, reg: fp21, asm: "VPCMPGTW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPABSWMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPABSW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPADDWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPADDW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXSWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINSWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULHWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULHW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULLWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULLW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMADDWDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMADDWD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPOPCNTWMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPADDSWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPADDSW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPSUBSWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSUBWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPABSWMasked256", argLength: 2, reg: fpkfp, asm: "VPABSW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPADDWMasked256", argLength: 3, reg: fp2kfp, asm: "VPADDW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXSWMasked256", argLength: 3, reg: fp2kfp, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINSWMasked256", argLength: 3, reg: fp2kfp, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULHWMasked256", argLength: 3, reg: fp2kfp, asm: "VPMULHW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULLWMasked256", argLength: 3, reg: fp2kfp, asm: "VPMULLW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMADDWDMasked256", argLength: 3, reg: fp2kfp, asm: "VPMADDWD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPOPCNTWMasked256", argLength: 2, reg: fpkfp, asm: "VPOPCNTW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPADDSWMasked256", argLength: 3, reg: fp2kfp, asm: "VPADDSW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPSUBSWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSUBWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMAXSW256", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINSW256", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULHW256", argLength: 2, reg: fp21, asm: "VPMULHW", commutative: true, typ: "Vec256", resultInArg0: false},
@ -250,17 +250,17 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VPSUBW256", argLength: 2, reg: fp21, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPABSW512", argLength: 1, reg: fp11, asm: "VPABSW", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDW512", argLength: 2, reg: fp21, asm: "VPADDW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPABSWMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPABSW", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPADDW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULHWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULHW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULLWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULLW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMADDWDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMADDWD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPOPCNTWMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDSWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPSUBSWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPSUBWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPABSWMasked512", argLength: 2, reg: fpkfp, asm: "VPABSW", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDWMasked512", argLength: 3, reg: fp2kfp, asm: "VPADDW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSWMasked512", argLength: 3, reg: fp2kfp, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSWMasked512", argLength: 3, reg: fp2kfp, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULHWMasked512", argLength: 3, reg: fp2kfp, asm: "VPMULHW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULLWMasked512", argLength: 3, reg: fp2kfp, asm: "VPMULLW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMADDWDMasked512", argLength: 3, reg: fp2kfp, asm: "VPMADDWD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPOPCNTWMasked512", argLength: 2, reg: fpkfp, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDSWMasked512", argLength: 3, reg: fp2kfp, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPSUBSWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPSUBWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSW512", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSW512", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULHW512", argLength: 2, reg: fp21, asm: "VPMULHW", commutative: true, typ: "Vec512", resultInArg0: false},
@ -274,17 +274,17 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VPADDW128", argLength: 2, reg: fp21, asm: "VPADDW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPCMPEQW128", argLength: 2, reg: fp21, asm: "VPCMPEQW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPCMPGTW128", argLength: 2, reg: fp21, asm: "VPCMPGTW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPABSWMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPABSW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPADDW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXSWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINSWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULHWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULHW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULLWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULLW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMADDWDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMADDWD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPOPCNTWMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDSWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPADDSW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPSUBSWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPSUBWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPABSWMasked128", argLength: 2, reg: fpkfp, asm: "VPABSW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDWMasked128", argLength: 3, reg: fp2kfp, asm: "VPADDW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXSWMasked128", argLength: 3, reg: fp2kfp, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINSWMasked128", argLength: 3, reg: fp2kfp, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULHWMasked128", argLength: 3, reg: fp2kfp, asm: "VPMULHW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULLWMasked128", argLength: 3, reg: fp2kfp, asm: "VPMULLW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMADDWDMasked128", argLength: 3, reg: fp2kfp, asm: "VPMADDWD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPOPCNTWMasked128", argLength: 2, reg: fpkfp, asm: "VPOPCNTW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDSWMasked128", argLength: 3, reg: fp2kfp, asm: "VPADDSW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPSUBSWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPSUBWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMAXSW128", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINSW128", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULHW128", argLength: 2, reg: fp21, asm: "VPMULHW", commutative: true, typ: "Vec128", resultInArg0: false},
@ -303,21 +303,21 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VPADDD512", argLength: 2, reg: fp21, asm: "VPADDD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPANDD512", argLength: 2, reg: fp21, asm: "VPANDD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPANDND512", argLength: 2, reg: fp21, asm: "VPANDND", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPABSDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPABSD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPADDD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPANDDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPANDD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPANDNDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPANDND", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINSD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULLDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULLD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPORDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPDPWSSDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPOPCNTDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPDPWSSDSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPDPBUSDSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPSUBDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPDPBUSDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPXORDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPABSDMasked512", argLength: 2, reg: fpkfp, asm: "VPABSD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDDMasked512", argLength: 3, reg: fp2kfp, asm: "VPADDD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPANDDMasked512", argLength: 3, reg: fp2kfp, asm: "VPANDD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPANDNDMasked512", argLength: 3, reg: fp2kfp, asm: "VPANDND", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSDMasked512", argLength: 3, reg: fp2kfp, asm: "VPMAXSD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSDMasked512", argLength: 3, reg: fp2kfp, asm: "VPMINSD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULLDMasked512", argLength: 3, reg: fp2kfp, asm: "VPMULLD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPORDMasked512", argLength: 3, reg: fp2kfp, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPDPWSSDMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPOPCNTDMasked512", argLength: 2, reg: fpkfp, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPDPWSSDSMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPDPBUSDSMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPSUBDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPDPBUSDMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPXORDMasked512", argLength: 3, reg: fp2kfp, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSD512", argLength: 2, reg: fp21, asm: "VPMAXSD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSD512", argLength: 2, reg: fp21, asm: "VPMINSD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULLD512", argLength: 2, reg: fp21, asm: "VPMULLD", commutative: true, typ: "Vec512", resultInArg0: false},
@ -333,21 +333,21 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VPADDD128", argLength: 2, reg: fp21, asm: "VPADDD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPCMPEQD128", argLength: 2, reg: fp21, asm: "VPCMPEQD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPCMPGTD128", argLength: 2, reg: fp21, asm: "VPCMPGTD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPABSDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPABSD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPADDD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPANDDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPANDD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPANDNDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPANDND", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMAXSDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINSDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINSD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULLDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULLD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPORDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPORD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPDPWSSDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VPDPWSSD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPOPCNTDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPDPWSSDSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPDPBUSDSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPSUBDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPDPBUSDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPXORDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPXORD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPABSDMasked128", argLength: 2, reg: fpkfp, asm: "VPABSD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDDMasked128", argLength: 3, reg: fp2kfp, asm: "VPADDD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPANDDMasked128", argLength: 3, reg: fp2kfp, asm: "VPANDD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPANDNDMasked128", argLength: 3, reg: fp2kfp, asm: "VPANDND", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMAXSDMasked128", argLength: 3, reg: fp2kfp, asm: "VPMAXSD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINSDMasked128", argLength: 3, reg: fp2kfp, asm: "VPMINSD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULLDMasked128", argLength: 3, reg: fp2kfp, asm: "VPMULLD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPORDMasked128", argLength: 3, reg: fp2kfp, asm: "VPORD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPDPWSSDMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPWSSD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPOPCNTDMasked128", argLength: 2, reg: fpkfp, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPDPWSSDSMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPDPBUSDSMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPSUBDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPDPBUSDMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPXORDMasked128", argLength: 3, reg: fp2kfp, asm: "VPXORD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXSD128", argLength: 2, reg: fp21, asm: "VPMAXSD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINSD128", argLength: 2, reg: fp21, asm: "VPMINSD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULDQ128", argLength: 2, reg: fp21, asm: "VPMULDQ", commutative: true, typ: "Vec128", resultInArg0: false},
@ -365,21 +365,21 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VPADDD256", argLength: 2, reg: fp21, asm: "VPADDD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPCMPEQD256", argLength: 2, reg: fp21, asm: "VPCMPEQD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPCMPGTD256", argLength: 2, reg: fp21, asm: "VPCMPGTD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPABSDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPABSD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPADDDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPADDD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPANDDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPANDD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPANDNDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPANDND", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMAXSDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINSDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINSD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULLDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULLD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPORDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPORD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPDPWSSDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VPDPWSSD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPOPCNTDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPDPWSSDSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPDPBUSDSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPSUBDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPDPBUSDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPXORDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPXORD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPABSDMasked256", argLength: 2, reg: fpkfp, asm: "VPABSD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPADDDMasked256", argLength: 3, reg: fp2kfp, asm: "VPADDD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPANDDMasked256", argLength: 3, reg: fp2kfp, asm: "VPANDD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPANDNDMasked256", argLength: 3, reg: fp2kfp, asm: "VPANDND", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMAXSDMasked256", argLength: 3, reg: fp2kfp, asm: "VPMAXSD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINSDMasked256", argLength: 3, reg: fp2kfp, asm: "VPMINSD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULLDMasked256", argLength: 3, reg: fp2kfp, asm: "VPMULLD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPORDMasked256", argLength: 3, reg: fp2kfp, asm: "VPORD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPDPWSSDMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPWSSD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPOPCNTDMasked256", argLength: 2, reg: fpkfp, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPDPWSSDSMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPDPBUSDSMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPSUBDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPDPBUSDMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPXORDMasked256", argLength: 3, reg: fp2kfp, asm: "VPXORD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXSD256", argLength: 2, reg: fp21, asm: "VPMAXSD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINSD256", argLength: 2, reg: fp21, asm: "VPMINSD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULDQ256", argLength: 2, reg: fp21, asm: "VPMULDQ", commutative: true, typ: "Vec256", resultInArg0: false},
@ -396,18 +396,18 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VPABSQ128", argLength: 1, reg: fp11, asm: "VPABSQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDQ128", argLength: 2, reg: fp21, asm: "VPADDQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPCMPEQQ128", argLength: 2, reg: fp21, asm: "VPCMPEQQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPABSQMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPABSQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPADDQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPANDQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPANDQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPANDNQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPANDNQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMAXSQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINSQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINSQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULDQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULDQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULLQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPORQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPORQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPOPCNTQMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPSUBQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPXORQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPXORQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPABSQMasked128", argLength: 2, reg: fpkfp, asm: "VPABSQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDQMasked128", argLength: 3, reg: fp2kfp, asm: "VPADDQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPANDQMasked128", argLength: 3, reg: fp2kfp, asm: "VPANDQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPANDNQMasked128", argLength: 3, reg: fp2kfp, asm: "VPANDNQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMAXSQMasked128", argLength: 3, reg: fp2kfp, asm: "VPMAXSQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINSQMasked128", argLength: 3, reg: fp2kfp, asm: "VPMINSQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULDQMasked128", argLength: 3, reg: fp2kfp, asm: "VPMULDQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULLQMasked128", argLength: 3, reg: fp2kfp, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPORQMasked128", argLength: 3, reg: fp2kfp, asm: "VPORQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPOPCNTQMasked128", argLength: 2, reg: fpkfp, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPSUBQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPXORQMasked128", argLength: 3, reg: fp2kfp, asm: "VPXORQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXSQ128", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINSQ128", argLength: 2, reg: fp21, asm: "VPMINSQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULLQ128", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false},
@ -417,18 +417,18 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VPADDQ256", argLength: 2, reg: fp21, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPCMPEQQ256", argLength: 2, reg: fp21, asm: "VPCMPEQQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPCMPGTQ256", argLength: 2, reg: fp21, asm: "VPCMPGTQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPABSQMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPABSQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPADDQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPANDQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPANDQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPANDNQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPANDNQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMAXSQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINSQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULDQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULDQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULLQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPORQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPORQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPOPCNTQMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSUBQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPXORQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPXORQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPABSQMasked256", argLength: 2, reg: fpkfp, asm: "VPABSQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPADDQMasked256", argLength: 3, reg: fp2kfp, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPANDQMasked256", argLength: 3, reg: fp2kfp, asm: "VPANDQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPANDNQMasked256", argLength: 3, reg: fp2kfp, asm: "VPANDNQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMAXSQMasked256", argLength: 3, reg: fp2kfp, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINSQMasked256", argLength: 3, reg: fp2kfp, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULDQMasked256", argLength: 3, reg: fp2kfp, asm: "VPMULDQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULLQMasked256", argLength: 3, reg: fp2kfp, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPORQMasked256", argLength: 3, reg: fp2kfp, asm: "VPORQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPOPCNTQMasked256", argLength: 2, reg: fpkfp, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSUBQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPXORQMasked256", argLength: 3, reg: fp2kfp, asm: "VPXORQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXSQ256", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINSQ256", argLength: 2, reg: fp21, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULLQ256", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
@ -438,18 +438,18 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VPADDQ512", argLength: 2, reg: fp21, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPANDQ512", argLength: 2, reg: fp21, asm: "VPANDQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPANDNQ512", argLength: 2, reg: fp21, asm: "VPANDNQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPABSQMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPABSQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPANDQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPANDQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPANDNQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPANDNQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINSQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULDQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULDQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULLQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPORQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPOPCNTQMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPSUBQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPXORQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPABSQMasked512", argLength: 2, reg: fpkfp, asm: "VPABSQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDQMasked512", argLength: 3, reg: fp2kfp, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPANDQMasked512", argLength: 3, reg: fp2kfp, asm: "VPANDQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPANDNQMasked512", argLength: 3, reg: fp2kfp, asm: "VPANDNQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSQMasked512", argLength: 3, reg: fp2kfp, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSQMasked512", argLength: 3, reg: fp2kfp, asm: "VPMINSQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULDQMasked512", argLength: 3, reg: fp2kfp, asm: "VPMULDQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULLQMasked512", argLength: 3, reg: fp2kfp, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPORQMasked512", argLength: 3, reg: fp2kfp, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPOPCNTQMasked512", argLength: 2, reg: fpkfp, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPSUBQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPXORQMasked512", argLength: 3, reg: fp2kfp, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSQ512", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSQ512", argLength: 2, reg: fp21, asm: "VPMINSQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULDQ512", argLength: 2, reg: fp21, asm: "VPMULDQ", commutative: true, typ: "Vec512", resultInArg0: false},
@ -464,14 +464,14 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VPANDN128", argLength: 2, reg: fp21, asm: "VPANDN", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPCMPEQB128", argLength: 2, reg: fp21, asm: "VPCMPEQB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPCMPGTB128", argLength: 2, reg: fp21, asm: "VPCMPGTB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPABSBMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPABSB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPADDB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXSBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINSBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINSB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPOPCNTBMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDSBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPADDSB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPSUBSBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPSUBSB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPSUBBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPSUBB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPABSBMasked128", argLength: 2, reg: fpkfp, asm: "VPABSB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDBMasked128", argLength: 3, reg: fp2kfp, asm: "VPADDB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXSBMasked128", argLength: 3, reg: fp2kfp, asm: "VPMAXSB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINSBMasked128", argLength: 3, reg: fp2kfp, asm: "VPMINSB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPOPCNTBMasked128", argLength: 2, reg: fpkfp, asm: "VPOPCNTB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPADDSBMasked128", argLength: 3, reg: fp2kfp, asm: "VPADDSB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPSUBSBMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBSB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPSUBBMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMAXSB128", argLength: 2, reg: fp21, asm: "VPMAXSB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINSB128", argLength: 2, reg: fp21, asm: "VPMINSB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPOR128", argLength: 2, reg: fp21, asm: "VPOR", commutative: true, typ: "Vec128", resultInArg0: false},
@ -487,14 +487,14 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VPANDN256", argLength: 2, reg: fp21, asm: "VPANDN", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPCMPEQB256", argLength: 2, reg: fp21, asm: "VPCMPEQB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPCMPGTB256", argLength: 2, reg: fp21, asm: "VPCMPGTB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPABSBMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPABSB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPADDBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPADDB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXSBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINSBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINSB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPOPCNTBMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPADDSBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPADDSB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPSUBSBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPSUBSB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSUBBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPSUBB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPABSBMasked256", argLength: 2, reg: fpkfp, asm: "VPABSB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPADDBMasked256", argLength: 3, reg: fp2kfp, asm: "VPADDB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXSBMasked256", argLength: 3, reg: fp2kfp, asm: "VPMAXSB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINSBMasked256", argLength: 3, reg: fp2kfp, asm: "VPMINSB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPOPCNTBMasked256", argLength: 2, reg: fpkfp, asm: "VPOPCNTB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPADDSBMasked256", argLength: 3, reg: fp2kfp, asm: "VPADDSB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPSUBSBMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBSB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPSUBBMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMAXSB256", argLength: 2, reg: fp21, asm: "VPMAXSB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINSB256", argLength: 2, reg: fp21, asm: "VPMINSB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPOR256", argLength: 2, reg: fp21, asm: "VPOR", commutative: true, typ: "Vec256", resultInArg0: false},
@ -506,14 +506,14 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VPXOR256", argLength: 2, reg: fp21, asm: "VPXOR", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPABSB512", argLength: 1, reg: fp11, asm: "VPABSB", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDB512", argLength: 2, reg: fp21, asm: "VPADDB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPABSBMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPABSB", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPADDB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINSB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPOPCNTBMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTB", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDSBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPADDSB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPSUBSBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPSUBSB", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPSUBBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPSUBB", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPABSBMasked512", argLength: 2, reg: fpkfp, asm: "VPABSB", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDBMasked512", argLength: 3, reg: fp2kfp, asm: "VPADDB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSBMasked512", argLength: 3, reg: fp2kfp, asm: "VPMAXSB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSBMasked512", argLength: 3, reg: fp2kfp, asm: "VPMINSB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPOPCNTBMasked512", argLength: 2, reg: fpkfp, asm: "VPOPCNTB", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPADDSBMasked512", argLength: 3, reg: fp2kfp, asm: "VPADDSB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPSUBSBMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBSB", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPSUBBMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBB", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPMAXSB512", argLength: 2, reg: fp21, asm: "VPMAXSB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINSB512", argLength: 2, reg: fp21, asm: "VPMINSB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPOPCNTB512", argLength: 1, reg: fp11, asm: "VPOPCNTB", commutative: false, typ: "Vec512", resultInArg0: false},
@ -521,175 +521,175 @@ func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1
{name: "VPSUBSB512", argLength: 2, reg: fp21, asm: "VPSUBSB", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPSUBB512", argLength: 2, reg: fp21, asm: "VPSUBB", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPAVGW256", argLength: 2, reg: fp21, asm: "VPAVGW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPAVGWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPAVGW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXUWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINUWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINUW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULHUWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULHUW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPAVGWMasked256", argLength: 3, reg: fp2kfp, asm: "VPAVGW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXUWMasked256", argLength: 3, reg: fp2kfp, asm: "VPMAXUW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINUWMasked256", argLength: 3, reg: fp2kfp, asm: "VPMINUW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULHUWMasked256", argLength: 3, reg: fp2kfp, asm: "VPMULHUW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXUW256", argLength: 2, reg: fp21, asm: "VPMAXUW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINUW256", argLength: 2, reg: fp21, asm: "VPMINUW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULHUW256", argLength: 2, reg: fp21, asm: "VPMULHUW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPAVGW512", argLength: 2, reg: fp21, asm: "VPAVGW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPAVGWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPAVGW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXUWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINUWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINUW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULHUWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULHUW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPAVGWMasked512", argLength: 3, reg: fp2kfp, asm: "VPAVGW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXUWMasked512", argLength: 3, reg: fp2kfp, asm: "VPMAXUW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINUWMasked512", argLength: 3, reg: fp2kfp, asm: "VPMINUW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULHUWMasked512", argLength: 3, reg: fp2kfp, asm: "VPMULHUW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXUW512", argLength: 2, reg: fp21, asm: "VPMAXUW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINUW512", argLength: 2, reg: fp21, asm: "VPMINUW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULHUW512", argLength: 2, reg: fp21, asm: "VPMULHUW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPAVGW128", argLength: 2, reg: fp21, asm: "VPAVGW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPAVGWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPAVGW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXUWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINUWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINUW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULHUWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULHUW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPAVGWMasked128", argLength: 3, reg: fp2kfp, asm: "VPAVGW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXUWMasked128", argLength: 3, reg: fp2kfp, asm: "VPMAXUW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINUWMasked128", argLength: 3, reg: fp2kfp, asm: "VPMINUW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULHUWMasked128", argLength: 3, reg: fp2kfp, asm: "VPMULHUW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXUW128", argLength: 2, reg: fp21, asm: "VPMAXUW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINUW128", argLength: 2, reg: fp21, asm: "VPMINUW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULHUW128", argLength: 2, reg: fp21, asm: "VPMULHUW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXUDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINUDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINUD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXUDMasked512", argLength: 3, reg: fp2kfp, asm: "VPMAXUD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINUDMasked512", argLength: 3, reg: fp2kfp, asm: "VPMINUD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXUD512", argLength: 2, reg: fp21, asm: "VPMAXUD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINUD512", argLength: 2, reg: fp21, asm: "VPMINUD", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXUDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINUDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINUD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXUDMasked128", argLength: 3, reg: fp2kfp, asm: "VPMAXUD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINUDMasked128", argLength: 3, reg: fp2kfp, asm: "VPMINUD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXUD128", argLength: 2, reg: fp21, asm: "VPMAXUD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINUD128", argLength: 2, reg: fp21, asm: "VPMINUD", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULUDQ128", argLength: 2, reg: fp21, asm: "VPMULUDQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXUDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINUDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINUD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXUDMasked256", argLength: 3, reg: fp2kfp, asm: "VPMAXUD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINUDMasked256", argLength: 3, reg: fp2kfp, asm: "VPMINUD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXUD256", argLength: 2, reg: fp21, asm: "VPMAXUD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINUD256", argLength: 2, reg: fp21, asm: "VPMINUD", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULUDQ256", argLength: 2, reg: fp21, asm: "VPMULUDQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXUQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINUQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINUQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULUDQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULUDQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXUQMasked128", argLength: 3, reg: fp2kfp, asm: "VPMAXUQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINUQMasked128", argLength: 3, reg: fp2kfp, asm: "VPMINUQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMULUDQMasked128", argLength: 3, reg: fp2kfp, asm: "VPMULUDQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXUQ128", argLength: 2, reg: fp21, asm: "VPMAXUQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINUQ128", argLength: 2, reg: fp21, asm: "VPMINUQ", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXUQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINUQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINUQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULUDQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULUDQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXUQMasked256", argLength: 3, reg: fp2kfp, asm: "VPMAXUQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINUQMasked256", argLength: 3, reg: fp2kfp, asm: "VPMINUQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMULUDQMasked256", argLength: 3, reg: fp2kfp, asm: "VPMULUDQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXUQ256", argLength: 2, reg: fp21, asm: "VPMAXUQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINUQ256", argLength: 2, reg: fp21, asm: "VPMINUQ", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXUQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINUQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINUQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULUDQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULUDQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXUQMasked512", argLength: 3, reg: fp2kfp, asm: "VPMAXUQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINUQMasked512", argLength: 3, reg: fp2kfp, asm: "VPMINUQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULUDQMasked512", argLength: 3, reg: fp2kfp, asm: "VPMULUDQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXUQ512", argLength: 2, reg: fp21, asm: "VPMAXUQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINUQ512", argLength: 2, reg: fp21, asm: "VPMINUQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMULUDQ512", argLength: 2, reg: fp21, asm: "VPMULUDQ", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPAVGB128", argLength: 2, reg: fp21, asm: "VPAVGB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPAVGBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPAVGB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXUBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINUBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINUB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMADDUBSWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMADDUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPAVGBMasked128", argLength: 3, reg: fp2kfp, asm: "VPAVGB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMAXUBMasked128", argLength: 3, reg: fp2kfp, asm: "VPMAXUB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINUBMasked128", argLength: 3, reg: fp2kfp, asm: "VPMINUB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMADDUBSWMasked128", argLength: 3, reg: fp2kfp, asm: "VPMADDUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMAXUB128", argLength: 2, reg: fp21, asm: "VPMAXUB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINUB128", argLength: 2, reg: fp21, asm: "VPMINUB", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMADDUBSW128", argLength: 2, reg: fp21, asm: "VPMADDUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPAVGB256", argLength: 2, reg: fp21, asm: "VPAVGB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPAVGBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPAVGB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXUBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINUBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINUB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMADDUBSWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMADDUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPAVGBMasked256", argLength: 3, reg: fp2kfp, asm: "VPAVGB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMAXUBMasked256", argLength: 3, reg: fp2kfp, asm: "VPMAXUB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINUBMasked256", argLength: 3, reg: fp2kfp, asm: "VPMINUB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMADDUBSWMasked256", argLength: 3, reg: fp2kfp, asm: "VPMADDUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMAXUB256", argLength: 2, reg: fp21, asm: "VPMAXUB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINUB256", argLength: 2, reg: fp21, asm: "VPMINUB", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMADDUBSW256", argLength: 2, reg: fp21, asm: "VPMADDUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPAVGB512", argLength: 2, reg: fp21, asm: "VPAVGB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPAVGBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPAVGB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXUBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINUBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINUB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMADDUBSWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMADDUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPAVGBMasked512", argLength: 3, reg: fp2kfp, asm: "VPAVGB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMAXUBMasked512", argLength: 3, reg: fp2kfp, asm: "VPMAXUB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINUBMasked512", argLength: 3, reg: fp2kfp, asm: "VPMINUB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMADDUBSWMasked512", argLength: 3, reg: fp2kfp, asm: "VPMADDUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPMAXUB512", argLength: 2, reg: fp21, asm: "VPMAXUB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMINUB512", argLength: 2, reg: fp21, asm: "VPMINUB", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMADDUBSW512", argLength: 2, reg: fp21, asm: "VPMADDUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VRNDSCALEPS512", argLength: 1, reg: fp11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VREDUCEPS512", argLength: 1, reg: fp11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VCMPPS512", argLength: 2, reg: fp2k1, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VRNDSCALEPSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VREDUCEPSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VCMPPSMasked512", argLength: 3, reg: fp2k1k1, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VCMPPS512", argLength: 2, reg: fp2k, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VRNDSCALEPSMasked512", argLength: 2, reg: fpkfp, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VREDUCEPSMasked512", argLength: 2, reg: fpkfp, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VCMPPSMasked512", argLength: 3, reg: fp2kk, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VROUNDPS128", argLength: 1, reg: fp11, asm: "VROUNDPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRNDSCALEPS128", argLength: 1, reg: fp11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VREDUCEPS128", argLength: 1, reg: fp11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VCMPPS128", argLength: 2, reg: fp21, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VRNDSCALEPSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VREDUCEPSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VCMPPSMasked128", argLength: 3, reg: fp2k1k1, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VRNDSCALEPSMasked128", argLength: 2, reg: fpkfp, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VREDUCEPSMasked128", argLength: 2, reg: fpkfp, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VCMPPSMasked128", argLength: 3, reg: fp2kk, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VROUNDPS256", argLength: 1, reg: fp11, asm: "VROUNDPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRNDSCALEPS256", argLength: 1, reg: fp11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VREDUCEPS256", argLength: 1, reg: fp11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VCMPPS256", argLength: 2, reg: fp21, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VRNDSCALEPSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VREDUCEPSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VCMPPSMasked256", argLength: 3, reg: fp2k1k1, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VRNDSCALEPSMasked256", argLength: 2, reg: fpkfp, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VREDUCEPSMasked256", argLength: 2, reg: fpkfp, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VCMPPSMasked256", argLength: 3, reg: fp2kk, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VROUNDPD128", argLength: 1, reg: fp11, asm: "VROUNDPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VRNDSCALEPD128", argLength: 1, reg: fp11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VREDUCEPD128", argLength: 1, reg: fp11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VDPPD128", argLength: 2, reg: fp21, asm: "VDPPD", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VCMPPD128", argLength: 2, reg: fp21, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VRNDSCALEPDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VREDUCEPDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VCMPPDMasked128", argLength: 3, reg: fp2k1k1, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VRNDSCALEPDMasked128", argLength: 2, reg: fpkfp, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VREDUCEPDMasked128", argLength: 2, reg: fpkfp, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VCMPPDMasked128", argLength: 3, reg: fp2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VROUNDPD256", argLength: 1, reg: fp11, asm: "VROUNDPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VRNDSCALEPD256", argLength: 1, reg: fp11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VREDUCEPD256", argLength: 1, reg: fp11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VCMPPD256", argLength: 2, reg: fp21, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VRNDSCALEPDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VREDUCEPDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VCMPPDMasked256", argLength: 3, reg: fp2k1k1, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VRNDSCALEPDMasked256", argLength: 2, reg: fpkfp, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VREDUCEPDMasked256", argLength: 2, reg: fpkfp, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VCMPPDMasked256", argLength: 3, reg: fp2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VRNDSCALEPD512", argLength: 1, reg: fp11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VREDUCEPD512", argLength: 1, reg: fp11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VCMPPD512", argLength: 2, reg: fp2k1, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VRNDSCALEPDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VREDUCEPDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VCMPPDMasked512", argLength: 3, reg: fp2k1k1, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPW256", argLength: 2, reg: fp2k1, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPWMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPW512", argLength: 2, reg: fp2k1, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPWMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPW128", argLength: 2, reg: fp2k1, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPWMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPINSRW128", argLength: 2, reg: fp1gp1fp1, asm: "VPINSRW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPCMPD512", argLength: 2, reg: fp2k1, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPDMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPD128", argLength: 2, reg: fp2k1, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPDMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPINSRD128", argLength: 2, reg: fp1gp1fp1, asm: "VPINSRD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPCMPD256", argLength: 2, reg: fp2k1, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPDMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPQ128", argLength: 2, reg: fp2k1, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPQMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPINSRQ128", argLength: 2, reg: fp1gp1fp1, asm: "VPINSRQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPCMPQ256", argLength: 2, reg: fp2k1, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPQMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPQ512", argLength: 2, reg: fp2k1, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPQMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPB128", argLength: 2, reg: fp2k1, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPBMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPINSRB128", argLength: 2, reg: fp1gp1fp1, asm: "VPINSRB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPCMPB256", argLength: 2, reg: fp2k1, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPBMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPB512", argLength: 2, reg: fp2k1, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPBMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUW256", argLength: 2, reg: fp2k1, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUWMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUW512", argLength: 2, reg: fp2k1, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUWMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUW128", argLength: 2, reg: fp2k1, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUWMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUD512", argLength: 2, reg: fp2k1, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUDMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUD128", argLength: 2, reg: fp2k1, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUDMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUD256", argLength: 2, reg: fp2k1, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUDMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQ128", argLength: 2, reg: fp2k1, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQ256", argLength: 2, reg: fp2k1, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQ512", argLength: 2, reg: fp2k1, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUB128", argLength: 2, reg: fp2k1, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUBMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUB256", argLength: 2, reg: fp2k1, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUBMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUB512", argLength: 2, reg: fp2k1, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUBMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VCMPPD512", argLength: 2, reg: fp2k, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VRNDSCALEPDMasked512", argLength: 2, reg: fpkfp, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VREDUCEPDMasked512", argLength: 2, reg: fpkfp, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VCMPPDMasked512", argLength: 3, reg: fp2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPW256", argLength: 2, reg: fp2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPWMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPW512", argLength: 2, reg: fp2k, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPWMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPW128", argLength: 2, reg: fp2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPWMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPINSRW128", argLength: 2, reg: fpgpfp, asm: "VPINSRW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPCMPD512", argLength: 2, reg: fp2k, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPDMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPD128", argLength: 2, reg: fp2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPDMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPINSRD128", argLength: 2, reg: fpgpfp, asm: "VPINSRD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPCMPD256", argLength: 2, reg: fp2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPDMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPQ128", argLength: 2, reg: fp2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPQMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPINSRQ128", argLength: 2, reg: fpgpfp, asm: "VPINSRQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPCMPQ256", argLength: 2, reg: fp2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPQMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPQ512", argLength: 2, reg: fp2k, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPQMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPB128", argLength: 2, reg: fp2k, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPBMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPINSRB128", argLength: 2, reg: fpgpfp, asm: "VPINSRB", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPCMPB256", argLength: 2, reg: fp2k, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
{name: "VPCMPBMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPB512", argLength: 2, reg: fp2k, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPBMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUW256", argLength: 2, reg: fp2k, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUWMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUW512", argLength: 2, reg: fp2k, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUWMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUW128", argLength: 2, reg: fp2k, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUWMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUD512", argLength: 2, reg: fp2k, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUDMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUD128", argLength: 2, reg: fp2k, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUDMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUD256", argLength: 2, reg: fp2k, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUDMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQ128", argLength: 2, reg: fp2k, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQ256", argLength: 2, reg: fp2k, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQ512", argLength: 2, reg: fp2k, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUQMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUB128", argLength: 2, reg: fp2k, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUBMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUB256", argLength: 2, reg: fp2k, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUBMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUB512", argLength: 2, reg: fp2k, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
{name: "VPCMPUBMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
}
}