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[dev.simd] cmd/compile: fix unstable output

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This CL fixed an error left by CL 718160.

Change-Id: I442ea59bc1ff0dda2914d1858dd5ebe93e2818dc
Reviewed-on: https://go-review.googlesource.com/c/go/+/720281
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: David Chase <drchase@google.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
This commit is contained in:
Junyang Shao 2025-11-13 17:07:16 +00:00
parent d7a0c45642
commit e4d9484220
7 changed files with 8864 additions and 6501 deletions
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252
src/cmd/compile/internal/amd64/simdssa.go
View file

@ -42,22 +42,38 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPBROADCASTW512, ssa.OpAMD64VPBROADCASTW512,
ssa.OpAMD64VPBROADCASTD512, ssa.OpAMD64VPBROADCASTD512,
ssa.OpAMD64VPBROADCASTQ512, ssa.OpAMD64VPBROADCASTQ512,
ssa.OpAMD64VPMOVWB128, ssa.OpAMD64VPMOVWB128_128,
ssa.OpAMD64VPMOVWB128_256,
ssa.OpAMD64VPMOVWB256, ssa.OpAMD64VPMOVWB256,
ssa.OpAMD64VPMOVDB128, ssa.OpAMD64VPMOVDB128_128,
ssa.OpAMD64VPMOVQB128, ssa.OpAMD64VPMOVDB128_256,
ssa.OpAMD64VPMOVSWB128, ssa.OpAMD64VPMOVDB128_512,
ssa.OpAMD64VPMOVQB128_128,
ssa.OpAMD64VPMOVQB128_256,
ssa.OpAMD64VPMOVQB128_512,
ssa.OpAMD64VPMOVSWB128_128,
ssa.OpAMD64VPMOVSWB128_256,
ssa.OpAMD64VPMOVSWB256, ssa.OpAMD64VPMOVSWB256,
ssa.OpAMD64VPMOVSDB128, ssa.OpAMD64VPMOVSDB128_128,
ssa.OpAMD64VPMOVSQB128, ssa.OpAMD64VPMOVSDB128_256,
ssa.OpAMD64VPMOVSDB128_512,
ssa.OpAMD64VPMOVSQB128_128,
ssa.OpAMD64VPMOVSQB128_256,
ssa.OpAMD64VPMOVSQB128_512,
ssa.OpAMD64VPMOVSXBW256, ssa.OpAMD64VPMOVSXBW256,
ssa.OpAMD64VPMOVSXBW512, ssa.OpAMD64VPMOVSXBW512,
ssa.OpAMD64VPMOVDW128, ssa.OpAMD64VPMOVDW128_128,
ssa.OpAMD64VPMOVDW128_256,
ssa.OpAMD64VPMOVDW256, ssa.OpAMD64VPMOVDW256,
ssa.OpAMD64VPMOVQW128, ssa.OpAMD64VPMOVQW128_128,
ssa.OpAMD64VPMOVSDW128, ssa.OpAMD64VPMOVQW128_256,
ssa.OpAMD64VPMOVQW128_512,
ssa.OpAMD64VPMOVSDW128_128,
ssa.OpAMD64VPMOVSDW128_256,
ssa.OpAMD64VPMOVSDW256, ssa.OpAMD64VPMOVSDW256,
ssa.OpAMD64VPMOVSQW128, ssa.OpAMD64VPMOVSQW128_128,
ssa.OpAMD64VPMOVSQW128_256,
ssa.OpAMD64VPMOVSQW128_512,
ssa.OpAMD64VPMOVSXBW128, ssa.OpAMD64VPMOVSXBW128,
ssa.OpAMD64VCVTTPS2DQ128, ssa.OpAMD64VCVTTPS2DQ128,
ssa.OpAMD64VCVTTPS2DQ256, ssa.OpAMD64VCVTTPS2DQ256,
@ -65,9 +81,11 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMOVSXBD512, ssa.OpAMD64VPMOVSXBD512,
ssa.OpAMD64VPMOVSXWD256, ssa.OpAMD64VPMOVSXWD256,
ssa.OpAMD64VPMOVSXWD512, ssa.OpAMD64VPMOVSXWD512,
ssa.OpAMD64VPMOVQD128, ssa.OpAMD64VPMOVQD128_128,
ssa.OpAMD64VPMOVQD128_256,
ssa.OpAMD64VPMOVQD256, ssa.OpAMD64VPMOVQD256,
ssa.OpAMD64VPMOVSQD128, ssa.OpAMD64VPMOVSQD128_128,
ssa.OpAMD64VPMOVSQD128_256,
ssa.OpAMD64VPMOVSQD256, ssa.OpAMD64VPMOVSQD256,
ssa.OpAMD64VPMOVSXBD128, ssa.OpAMD64VPMOVSXBD128,
ssa.OpAMD64VPMOVSXWD128, ssa.OpAMD64VPMOVSXWD128,
@ -80,15 +98,23 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMOVSXDQ128, ssa.OpAMD64VPMOVSXDQ128,
ssa.OpAMD64VPMOVSXBQ256, ssa.OpAMD64VPMOVSXBQ256,
ssa.OpAMD64VPMOVSXBQ512, ssa.OpAMD64VPMOVSXBQ512,
ssa.OpAMD64VPMOVUSWB128, ssa.OpAMD64VPMOVUSWB128_128,
ssa.OpAMD64VPMOVUSWB128_256,
ssa.OpAMD64VPMOVUSWB256, ssa.OpAMD64VPMOVUSWB256,
ssa.OpAMD64VPMOVUSDB128, ssa.OpAMD64VPMOVUSDB128_128,
ssa.OpAMD64VPMOVUSQB128, ssa.OpAMD64VPMOVUSDB128_256,
ssa.OpAMD64VPMOVUSDB128_512,
ssa.OpAMD64VPMOVUSQB128_128,
ssa.OpAMD64VPMOVUSQB128_256,
ssa.OpAMD64VPMOVUSQB128_512,
ssa.OpAMD64VPMOVZXBW256, ssa.OpAMD64VPMOVZXBW256,
ssa.OpAMD64VPMOVZXBW512, ssa.OpAMD64VPMOVZXBW512,
ssa.OpAMD64VPMOVUSDW128, ssa.OpAMD64VPMOVUSDW128_128,
ssa.OpAMD64VPMOVUSDW128_256,
ssa.OpAMD64VPMOVUSDW256, ssa.OpAMD64VPMOVUSDW256,
ssa.OpAMD64VPMOVUSQW128, ssa.OpAMD64VPMOVUSQW128_128,
ssa.OpAMD64VPMOVUSQW128_256,
ssa.OpAMD64VPMOVUSQW128_512,
ssa.OpAMD64VPMOVZXBW128, ssa.OpAMD64VPMOVZXBW128,
ssa.OpAMD64VCVTPS2UDQ128, ssa.OpAMD64VCVTPS2UDQ128,
ssa.OpAMD64VCVTPS2UDQ256, ssa.OpAMD64VCVTPS2UDQ256,
@ -96,7 +122,8 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMOVZXBD512, ssa.OpAMD64VPMOVZXBD512,
ssa.OpAMD64VPMOVZXWD256, ssa.OpAMD64VPMOVZXWD256,
ssa.OpAMD64VPMOVZXWD512, ssa.OpAMD64VPMOVZXWD512,
ssa.OpAMD64VPMOVUSQD128, ssa.OpAMD64VPMOVUSQD128_128,
ssa.OpAMD64VPMOVUSQD128_256,
ssa.OpAMD64VPMOVUSQD256, ssa.OpAMD64VPMOVUSQD256,
ssa.OpAMD64VPMOVZXBD128, ssa.OpAMD64VPMOVZXBD128,
ssa.OpAMD64VPMOVZXWD128, ssa.OpAMD64VPMOVZXWD128,
@ -791,22 +818,38 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPCOMPRESSQMasked128, ssa.OpAMD64VPCOMPRESSQMasked128,
ssa.OpAMD64VPCOMPRESSQMasked256, ssa.OpAMD64VPCOMPRESSQMasked256,
ssa.OpAMD64VPCOMPRESSQMasked512, ssa.OpAMD64VPCOMPRESSQMasked512,
ssa.OpAMD64VPMOVWBMasked128, ssa.OpAMD64VPMOVWBMasked128_128,
ssa.OpAMD64VPMOVWBMasked128_256,
ssa.OpAMD64VPMOVWBMasked256, ssa.OpAMD64VPMOVWBMasked256,
ssa.OpAMD64VPMOVDBMasked128, ssa.OpAMD64VPMOVDBMasked128_128,
ssa.OpAMD64VPMOVQBMasked128, ssa.OpAMD64VPMOVDBMasked128_256,
ssa.OpAMD64VPMOVSWBMasked128, ssa.OpAMD64VPMOVDBMasked128_512,
ssa.OpAMD64VPMOVQBMasked128_128,
ssa.OpAMD64VPMOVQBMasked128_256,
ssa.OpAMD64VPMOVQBMasked128_512,
ssa.OpAMD64VPMOVSWBMasked128_128,
ssa.OpAMD64VPMOVSWBMasked128_256,
ssa.OpAMD64VPMOVSWBMasked256, ssa.OpAMD64VPMOVSWBMasked256,
ssa.OpAMD64VPMOVSDBMasked128, ssa.OpAMD64VPMOVSDBMasked128_128,
ssa.OpAMD64VPMOVSQBMasked128, ssa.OpAMD64VPMOVSDBMasked128_256,
ssa.OpAMD64VPMOVSDBMasked128_512,
ssa.OpAMD64VPMOVSQBMasked128_128,
ssa.OpAMD64VPMOVSQBMasked128_256,
ssa.OpAMD64VPMOVSQBMasked128_512,
ssa.OpAMD64VPMOVSXBWMasked256, ssa.OpAMD64VPMOVSXBWMasked256,
ssa.OpAMD64VPMOVSXBWMasked512, ssa.OpAMD64VPMOVSXBWMasked512,
ssa.OpAMD64VPMOVDWMasked128, ssa.OpAMD64VPMOVDWMasked128_128,
ssa.OpAMD64VPMOVDWMasked128_256,
ssa.OpAMD64VPMOVDWMasked256, ssa.OpAMD64VPMOVDWMasked256,
ssa.OpAMD64VPMOVQWMasked128, ssa.OpAMD64VPMOVQWMasked128_128,
ssa.OpAMD64VPMOVSDWMasked128, ssa.OpAMD64VPMOVQWMasked128_256,
ssa.OpAMD64VPMOVQWMasked128_512,
ssa.OpAMD64VPMOVSDWMasked128_128,
ssa.OpAMD64VPMOVSDWMasked128_256,
ssa.OpAMD64VPMOVSDWMasked256, ssa.OpAMD64VPMOVSDWMasked256,
ssa.OpAMD64VPMOVSQWMasked128, ssa.OpAMD64VPMOVSQWMasked128_128,
ssa.OpAMD64VPMOVSQWMasked128_256,
ssa.OpAMD64VPMOVSQWMasked128_512,
ssa.OpAMD64VPMOVSXBWMasked128, ssa.OpAMD64VPMOVSXBWMasked128,
ssa.OpAMD64VCVTTPS2DQMasked128, ssa.OpAMD64VCVTTPS2DQMasked128,
ssa.OpAMD64VCVTTPS2DQMasked256, ssa.OpAMD64VCVTTPS2DQMasked256,
@ -814,9 +857,11 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMOVSXBDMasked512, ssa.OpAMD64VPMOVSXBDMasked512,
ssa.OpAMD64VPMOVSXWDMasked256, ssa.OpAMD64VPMOVSXWDMasked256,
ssa.OpAMD64VPMOVSXWDMasked512, ssa.OpAMD64VPMOVSXWDMasked512,
ssa.OpAMD64VPMOVQDMasked128, ssa.OpAMD64VPMOVQDMasked128_128,
ssa.OpAMD64VPMOVQDMasked128_256,
ssa.OpAMD64VPMOVQDMasked256, ssa.OpAMD64VPMOVQDMasked256,
ssa.OpAMD64VPMOVSQDMasked128, ssa.OpAMD64VPMOVSQDMasked128_128,
ssa.OpAMD64VPMOVSQDMasked128_256,
ssa.OpAMD64VPMOVSQDMasked256, ssa.OpAMD64VPMOVSQDMasked256,
ssa.OpAMD64VPMOVSXBDMasked128, ssa.OpAMD64VPMOVSXBDMasked128,
ssa.OpAMD64VPMOVSXWDMasked128, ssa.OpAMD64VPMOVSXWDMasked128,
@ -829,15 +874,23 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMOVSXDQMasked128, ssa.OpAMD64VPMOVSXDQMasked128,
ssa.OpAMD64VPMOVSXBQMasked256, ssa.OpAMD64VPMOVSXBQMasked256,
ssa.OpAMD64VPMOVSXBQMasked512, ssa.OpAMD64VPMOVSXBQMasked512,
ssa.OpAMD64VPMOVUSWBMasked128, ssa.OpAMD64VPMOVUSWBMasked128_128,
ssa.OpAMD64VPMOVUSWBMasked128_256,
ssa.OpAMD64VPMOVUSWBMasked256, ssa.OpAMD64VPMOVUSWBMasked256,
ssa.OpAMD64VPMOVUSDBMasked128, ssa.OpAMD64VPMOVUSDBMasked128_128,
ssa.OpAMD64VPMOVUSQBMasked128, ssa.OpAMD64VPMOVUSDBMasked128_256,
ssa.OpAMD64VPMOVUSDBMasked128_512,
ssa.OpAMD64VPMOVUSQBMasked128_128,
ssa.OpAMD64VPMOVUSQBMasked128_256,
ssa.OpAMD64VPMOVUSQBMasked128_512,
ssa.OpAMD64VPMOVZXBWMasked256, ssa.OpAMD64VPMOVZXBWMasked256,
ssa.OpAMD64VPMOVZXBWMasked512, ssa.OpAMD64VPMOVZXBWMasked512,
ssa.OpAMD64VPMOVUSDWMasked128, ssa.OpAMD64VPMOVUSDWMasked128_128,
ssa.OpAMD64VPMOVUSDWMasked128_256,
ssa.OpAMD64VPMOVUSDWMasked256, ssa.OpAMD64VPMOVUSDWMasked256,
ssa.OpAMD64VPMOVUSQWMasked128, ssa.OpAMD64VPMOVUSQWMasked128_128,
ssa.OpAMD64VPMOVUSQWMasked128_256,
ssa.OpAMD64VPMOVUSQWMasked128_512,
ssa.OpAMD64VPMOVZXBWMasked128, ssa.OpAMD64VPMOVZXBWMasked128,
ssa.OpAMD64VCVTPS2UDQMasked128, ssa.OpAMD64VCVTPS2UDQMasked128,
ssa.OpAMD64VCVTPS2UDQMasked256, ssa.OpAMD64VCVTPS2UDQMasked256,
@ -845,7 +898,8 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMOVZXBDMasked512, ssa.OpAMD64VPMOVZXBDMasked512,
ssa.OpAMD64VPMOVZXWDMasked256, ssa.OpAMD64VPMOVZXWDMasked256,
ssa.OpAMD64VPMOVZXWDMasked512, ssa.OpAMD64VPMOVZXWDMasked512,
ssa.OpAMD64VPMOVUSQDMasked128, ssa.OpAMD64VPMOVUSQDMasked128_128,
ssa.OpAMD64VPMOVUSQDMasked128_256,
ssa.OpAMD64VPMOVUSQDMasked256, ssa.OpAMD64VPMOVUSQDMasked256,
ssa.OpAMD64VPMOVZXBDMasked128, ssa.OpAMD64VPMOVZXBDMasked128,
ssa.OpAMD64VPMOVZXWDMasked128, ssa.OpAMD64VPMOVZXWDMasked128,
@ -2266,22 +2320,38 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VREDUCEPDMasked128Merging, ssa.OpAMD64VREDUCEPDMasked128Merging,
ssa.OpAMD64VREDUCEPDMasked256Merging, ssa.OpAMD64VREDUCEPDMasked256Merging,
ssa.OpAMD64VREDUCEPDMasked512Merging, ssa.OpAMD64VREDUCEPDMasked512Merging,
ssa.OpAMD64VPMOVWBMasked128Merging, ssa.OpAMD64VPMOVWBMasked128_128Merging,
ssa.OpAMD64VPMOVWBMasked128_256Merging,
ssa.OpAMD64VPMOVWBMasked256Merging, ssa.OpAMD64VPMOVWBMasked256Merging,
ssa.OpAMD64VPMOVDBMasked128Merging, ssa.OpAMD64VPMOVDBMasked128_128Merging,
ssa.OpAMD64VPMOVQBMasked128Merging, ssa.OpAMD64VPMOVDBMasked128_256Merging,
ssa.OpAMD64VPMOVSWBMasked128Merging, ssa.OpAMD64VPMOVDBMasked128_512Merging,
ssa.OpAMD64VPMOVQBMasked128_128Merging,
ssa.OpAMD64VPMOVQBMasked128_256Merging,
ssa.OpAMD64VPMOVQBMasked128_512Merging,
ssa.OpAMD64VPMOVSWBMasked128_128Merging,
ssa.OpAMD64VPMOVSWBMasked128_256Merging,
ssa.OpAMD64VPMOVSWBMasked256Merging, ssa.OpAMD64VPMOVSWBMasked256Merging,
ssa.OpAMD64VPMOVSDBMasked128Merging, ssa.OpAMD64VPMOVSDBMasked128_128Merging,
ssa.OpAMD64VPMOVSQBMasked128Merging, ssa.OpAMD64VPMOVSDBMasked128_256Merging,
ssa.OpAMD64VPMOVSDBMasked128_512Merging,
ssa.OpAMD64VPMOVSQBMasked128_128Merging,
ssa.OpAMD64VPMOVSQBMasked128_256Merging,
ssa.OpAMD64VPMOVSQBMasked128_512Merging,
ssa.OpAMD64VPMOVSXBWMasked256Merging, ssa.OpAMD64VPMOVSXBWMasked256Merging,
ssa.OpAMD64VPMOVSXBWMasked512Merging, ssa.OpAMD64VPMOVSXBWMasked512Merging,
ssa.OpAMD64VPMOVDWMasked128Merging, ssa.OpAMD64VPMOVDWMasked128_128Merging,
ssa.OpAMD64VPMOVDWMasked128_256Merging,
ssa.OpAMD64VPMOVDWMasked256Merging, ssa.OpAMD64VPMOVDWMasked256Merging,
ssa.OpAMD64VPMOVQWMasked128Merging, ssa.OpAMD64VPMOVQWMasked128_128Merging,
ssa.OpAMD64VPMOVSDWMasked128Merging, ssa.OpAMD64VPMOVQWMasked128_256Merging,
ssa.OpAMD64VPMOVQWMasked128_512Merging,
ssa.OpAMD64VPMOVSDWMasked128_128Merging,
ssa.OpAMD64VPMOVSDWMasked128_256Merging,
ssa.OpAMD64VPMOVSDWMasked256Merging, ssa.OpAMD64VPMOVSDWMasked256Merging,
ssa.OpAMD64VPMOVSQWMasked128Merging, ssa.OpAMD64VPMOVSQWMasked128_128Merging,
ssa.OpAMD64VPMOVSQWMasked128_256Merging,
ssa.OpAMD64VPMOVSQWMasked128_512Merging,
ssa.OpAMD64VPMOVSXBWMasked128Merging, ssa.OpAMD64VPMOVSXBWMasked128Merging,
ssa.OpAMD64VCVTTPS2DQMasked128Merging, ssa.OpAMD64VCVTTPS2DQMasked128Merging,
ssa.OpAMD64VCVTTPS2DQMasked256Merging, ssa.OpAMD64VCVTTPS2DQMasked256Merging,
@ -2289,9 +2359,11 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMOVSXBDMasked512Merging, ssa.OpAMD64VPMOVSXBDMasked512Merging,
ssa.OpAMD64VPMOVSXWDMasked256Merging, ssa.OpAMD64VPMOVSXWDMasked256Merging,
ssa.OpAMD64VPMOVSXWDMasked512Merging, ssa.OpAMD64VPMOVSXWDMasked512Merging,
ssa.OpAMD64VPMOVQDMasked128Merging, ssa.OpAMD64VPMOVQDMasked128_128Merging,
ssa.OpAMD64VPMOVQDMasked128_256Merging,
ssa.OpAMD64VPMOVQDMasked256Merging, ssa.OpAMD64VPMOVQDMasked256Merging,
ssa.OpAMD64VPMOVSQDMasked128Merging, ssa.OpAMD64VPMOVSQDMasked128_128Merging,
ssa.OpAMD64VPMOVSQDMasked128_256Merging,
ssa.OpAMD64VPMOVSQDMasked256Merging, ssa.OpAMD64VPMOVSQDMasked256Merging,
ssa.OpAMD64VPMOVSXBDMasked128Merging, ssa.OpAMD64VPMOVSXBDMasked128Merging,
ssa.OpAMD64VPMOVSXWDMasked128Merging, ssa.OpAMD64VPMOVSXWDMasked128Merging,
@ -2304,15 +2376,23 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMOVSXDQMasked128Merging, ssa.OpAMD64VPMOVSXDQMasked128Merging,
ssa.OpAMD64VPMOVSXBQMasked256Merging, ssa.OpAMD64VPMOVSXBQMasked256Merging,
ssa.OpAMD64VPMOVSXBQMasked512Merging, ssa.OpAMD64VPMOVSXBQMasked512Merging,
ssa.OpAMD64VPMOVUSWBMasked128Merging, ssa.OpAMD64VPMOVUSWBMasked128_128Merging,
ssa.OpAMD64VPMOVUSWBMasked128_256Merging,
ssa.OpAMD64VPMOVUSWBMasked256Merging, ssa.OpAMD64VPMOVUSWBMasked256Merging,
ssa.OpAMD64VPMOVUSDBMasked128Merging, ssa.OpAMD64VPMOVUSDBMasked128_128Merging,
ssa.OpAMD64VPMOVUSQBMasked128Merging, ssa.OpAMD64VPMOVUSDBMasked128_256Merging,
ssa.OpAMD64VPMOVUSDBMasked128_512Merging,
ssa.OpAMD64VPMOVUSQBMasked128_128Merging,
ssa.OpAMD64VPMOVUSQBMasked128_256Merging,
ssa.OpAMD64VPMOVUSQBMasked128_512Merging,
ssa.OpAMD64VPMOVZXBWMasked256Merging, ssa.OpAMD64VPMOVZXBWMasked256Merging,
ssa.OpAMD64VPMOVZXBWMasked512Merging, ssa.OpAMD64VPMOVZXBWMasked512Merging,
ssa.OpAMD64VPMOVUSDWMasked128Merging, ssa.OpAMD64VPMOVUSDWMasked128_128Merging,
ssa.OpAMD64VPMOVUSDWMasked128_256Merging,
ssa.OpAMD64VPMOVUSDWMasked256Merging, ssa.OpAMD64VPMOVUSDWMasked256Merging,
ssa.OpAMD64VPMOVUSQWMasked128Merging, ssa.OpAMD64VPMOVUSQWMasked128_128Merging,
ssa.OpAMD64VPMOVUSQWMasked128_256Merging,
ssa.OpAMD64VPMOVUSQWMasked128_512Merging,
ssa.OpAMD64VPMOVZXBWMasked128Merging, ssa.OpAMD64VPMOVZXBWMasked128Merging,
ssa.OpAMD64VCVTPS2UDQMasked128Merging, ssa.OpAMD64VCVTPS2UDQMasked128Merging,
ssa.OpAMD64VCVTPS2UDQMasked256Merging, ssa.OpAMD64VCVTPS2UDQMasked256Merging,
@ -2320,7 +2400,8 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMOVZXBDMasked512Merging, ssa.OpAMD64VPMOVZXBDMasked512Merging,
ssa.OpAMD64VPMOVZXWDMasked256Merging, ssa.OpAMD64VPMOVZXWDMasked256Merging,
ssa.OpAMD64VPMOVZXWDMasked512Merging, ssa.OpAMD64VPMOVZXWDMasked512Merging,
ssa.OpAMD64VPMOVUSQDMasked128Merging, ssa.OpAMD64VPMOVUSQDMasked128_128Merging,
ssa.OpAMD64VPMOVUSQDMasked128_256Merging,
ssa.OpAMD64VPMOVUSQDMasked256Merging, ssa.OpAMD64VPMOVUSQDMasked256Merging,
ssa.OpAMD64VPMOVZXBDMasked128Merging, ssa.OpAMD64VPMOVZXBDMasked128Merging,
ssa.OpAMD64VPMOVZXWDMasked128Merging, ssa.OpAMD64VPMOVZXWDMasked128Merging,
@ -2592,22 +2673,38 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPCOMPRESSQMasked128, ssa.OpAMD64VPCOMPRESSQMasked128,
ssa.OpAMD64VPCOMPRESSQMasked256, ssa.OpAMD64VPCOMPRESSQMasked256,
ssa.OpAMD64VPCOMPRESSQMasked512, ssa.OpAMD64VPCOMPRESSQMasked512,
ssa.OpAMD64VPMOVWBMasked128, ssa.OpAMD64VPMOVWBMasked128_128,
ssa.OpAMD64VPMOVWBMasked128_256,
ssa.OpAMD64VPMOVWBMasked256, ssa.OpAMD64VPMOVWBMasked256,
ssa.OpAMD64VPMOVDBMasked128, ssa.OpAMD64VPMOVDBMasked128_128,
ssa.OpAMD64VPMOVQBMasked128, ssa.OpAMD64VPMOVDBMasked128_256,
ssa.OpAMD64VPMOVSWBMasked128, ssa.OpAMD64VPMOVDBMasked128_512,
ssa.OpAMD64VPMOVQBMasked128_128,
ssa.OpAMD64VPMOVQBMasked128_256,
ssa.OpAMD64VPMOVQBMasked128_512,
ssa.OpAMD64VPMOVSWBMasked128_128,
ssa.OpAMD64VPMOVSWBMasked128_256,
ssa.OpAMD64VPMOVSWBMasked256, ssa.OpAMD64VPMOVSWBMasked256,
ssa.OpAMD64VPMOVSDBMasked128, ssa.OpAMD64VPMOVSDBMasked128_128,
ssa.OpAMD64VPMOVSQBMasked128, ssa.OpAMD64VPMOVSDBMasked128_256,
ssa.OpAMD64VPMOVSDBMasked128_512,
ssa.OpAMD64VPMOVSQBMasked128_128,
ssa.OpAMD64VPMOVSQBMasked128_256,
ssa.OpAMD64VPMOVSQBMasked128_512,
ssa.OpAMD64VPMOVSXBWMasked256, ssa.OpAMD64VPMOVSXBWMasked256,
ssa.OpAMD64VPMOVSXBWMasked512, ssa.OpAMD64VPMOVSXBWMasked512,
ssa.OpAMD64VPMOVDWMasked128, ssa.OpAMD64VPMOVDWMasked128_128,
ssa.OpAMD64VPMOVDWMasked128_256,
ssa.OpAMD64VPMOVDWMasked256, ssa.OpAMD64VPMOVDWMasked256,
ssa.OpAMD64VPMOVQWMasked128, ssa.OpAMD64VPMOVQWMasked128_128,
ssa.OpAMD64VPMOVSDWMasked128, ssa.OpAMD64VPMOVQWMasked128_256,
ssa.OpAMD64VPMOVQWMasked128_512,
ssa.OpAMD64VPMOVSDWMasked128_128,
ssa.OpAMD64VPMOVSDWMasked128_256,
ssa.OpAMD64VPMOVSDWMasked256, ssa.OpAMD64VPMOVSDWMasked256,
ssa.OpAMD64VPMOVSQWMasked128, ssa.OpAMD64VPMOVSQWMasked128_128,
ssa.OpAMD64VPMOVSQWMasked128_256,
ssa.OpAMD64VPMOVSQWMasked128_512,
ssa.OpAMD64VPACKSSDWMasked128, ssa.OpAMD64VPACKSSDWMasked128,
ssa.OpAMD64VPACKSSDWMasked128load, ssa.OpAMD64VPACKSSDWMasked128load,
ssa.OpAMD64VPACKSSDWMasked256, ssa.OpAMD64VPACKSSDWMasked256,
@ -2624,9 +2721,11 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMOVSXBDMasked512, ssa.OpAMD64VPMOVSXBDMasked512,
ssa.OpAMD64VPMOVSXWDMasked256, ssa.OpAMD64VPMOVSXWDMasked256,
ssa.OpAMD64VPMOVSXWDMasked512, ssa.OpAMD64VPMOVSXWDMasked512,
ssa.OpAMD64VPMOVQDMasked128, ssa.OpAMD64VPMOVQDMasked128_128,
ssa.OpAMD64VPMOVQDMasked128_256,
ssa.OpAMD64VPMOVQDMasked256, ssa.OpAMD64VPMOVQDMasked256,
ssa.OpAMD64VPMOVSQDMasked128, ssa.OpAMD64VPMOVSQDMasked128_128,
ssa.OpAMD64VPMOVSQDMasked128_256,
ssa.OpAMD64VPMOVSQDMasked256, ssa.OpAMD64VPMOVSQDMasked256,
ssa.OpAMD64VPMOVSXBDMasked128, ssa.OpAMD64VPMOVSXBDMasked128,
ssa.OpAMD64VPMOVSXWDMasked128, ssa.OpAMD64VPMOVSXWDMasked128,
@ -2639,15 +2738,23 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMOVSXDQMasked128, ssa.OpAMD64VPMOVSXDQMasked128,
ssa.OpAMD64VPMOVSXBQMasked256, ssa.OpAMD64VPMOVSXBQMasked256,
ssa.OpAMD64VPMOVSXBQMasked512, ssa.OpAMD64VPMOVSXBQMasked512,
ssa.OpAMD64VPMOVUSWBMasked128, ssa.OpAMD64VPMOVUSWBMasked128_128,
ssa.OpAMD64VPMOVUSWBMasked128_256,
ssa.OpAMD64VPMOVUSWBMasked256, ssa.OpAMD64VPMOVUSWBMasked256,
ssa.OpAMD64VPMOVUSDBMasked128, ssa.OpAMD64VPMOVUSDBMasked128_128,
ssa.OpAMD64VPMOVUSQBMasked128, ssa.OpAMD64VPMOVUSDBMasked128_256,
ssa.OpAMD64VPMOVUSDBMasked128_512,
ssa.OpAMD64VPMOVUSQBMasked128_128,
ssa.OpAMD64VPMOVUSQBMasked128_256,
ssa.OpAMD64VPMOVUSQBMasked128_512,
ssa.OpAMD64VPMOVZXBWMasked256, ssa.OpAMD64VPMOVZXBWMasked256,
ssa.OpAMD64VPMOVZXBWMasked512, ssa.OpAMD64VPMOVZXBWMasked512,
ssa.OpAMD64VPMOVUSDWMasked128, ssa.OpAMD64VPMOVUSDWMasked128_128,
ssa.OpAMD64VPMOVUSDWMasked128_256,
ssa.OpAMD64VPMOVUSDWMasked256, ssa.OpAMD64VPMOVUSDWMasked256,
ssa.OpAMD64VPMOVUSQWMasked128, ssa.OpAMD64VPMOVUSQWMasked128_128,
ssa.OpAMD64VPMOVUSQWMasked128_256,
ssa.OpAMD64VPMOVUSQWMasked128_512,
ssa.OpAMD64VPACKUSDWMasked128, ssa.OpAMD64VPACKUSDWMasked128,
ssa.OpAMD64VPACKUSDWMasked128load, ssa.OpAMD64VPACKUSDWMasked128load,
ssa.OpAMD64VPACKUSDWMasked256, ssa.OpAMD64VPACKUSDWMasked256,
@ -2664,7 +2771,8 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
ssa.OpAMD64VPMOVZXBDMasked512, ssa.OpAMD64VPMOVZXBDMasked512,
ssa.OpAMD64VPMOVZXWDMasked256, ssa.OpAMD64VPMOVZXWDMasked256,
ssa.OpAMD64VPMOVZXWDMasked512, ssa.OpAMD64VPMOVZXWDMasked512,
ssa.OpAMD64VPMOVUSQDMasked128, ssa.OpAMD64VPMOVUSQDMasked128_128,
ssa.OpAMD64VPMOVUSQDMasked128_256,
ssa.OpAMD64VPMOVUSQDMasked256, ssa.OpAMD64VPMOVUSQDMasked256,
ssa.OpAMD64VPMOVZXBDMasked128, ssa.OpAMD64VPMOVZXBDMasked128,
ssa.OpAMD64VPMOVZXWDMasked128, ssa.OpAMD64VPMOVZXWDMasked128,

1014
src/cmd/compile/internal/ssa/_gen/simdAMD64.rules
View file

File diff suppressed because it is too large Load diff

189
src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go
View file

@ -585,37 +585,71 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
{name: "VPMINUWMasked128", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec128", resultInArg0: false}, {name: "VPMINUWMasked128", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec128", resultInArg0: false},
{name: "VPMINUWMasked256", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec256", resultInArg0: false}, {name: "VPMINUWMasked256", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec256", resultInArg0: false},
{name: "VPMINUWMasked512", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec512", resultInArg0: false}, {name: "VPMINUWMasked512", argLength: 3, reg: w2kw, asm: "VPMINUW", commutative: true, typ: "Vec512", resultInArg0: false},
{name: "VPMOVDB128", argLength: 1, reg: w11, asm: "VPMOVDB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVDB128_128", argLength: 1, reg: w11, asm: "VPMOVDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVDBMasked128", argLength: 2, reg: wkw, asm: "VPMOVDB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVDB128_256", argLength: 1, reg: w11, asm: "VPMOVDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVDW128", argLength: 1, reg: w11, asm: "VPMOVDW", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVDB128_512", argLength: 1, reg: w11, asm: "VPMOVDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVDBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVDBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVDBMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVDW128_128", argLength: 1, reg: w11, asm: "VPMOVDW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVDW128_256", argLength: 1, reg: w11, asm: "VPMOVDW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVDW256", argLength: 1, reg: w11, asm: "VPMOVDW", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVDW256", argLength: 1, reg: w11, asm: "VPMOVDW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVDWMasked128", argLength: 2, reg: wkw, asm: "VPMOVDW", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVDWMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVDW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVDWMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVDW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVDWMasked256", argLength: 2, reg: wkw, asm: "VPMOVDW", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVDWMasked256", argLength: 2, reg: wkw, asm: "VPMOVDW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVQB128", argLength: 1, reg: w11, asm: "VPMOVQB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVQB128_128", argLength: 1, reg: w11, asm: "VPMOVQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVQBMasked128", argLength: 2, reg: wkw, asm: "VPMOVQB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVQB128_256", argLength: 1, reg: w11, asm: "VPMOVQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVQD128", argLength: 1, reg: w11, asm: "VPMOVQD", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVQB128_512", argLength: 1, reg: w11, asm: "VPMOVQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVQBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVQBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVQBMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVQD128_128", argLength: 1, reg: w11, asm: "VPMOVQD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVQD128_256", argLength: 1, reg: w11, asm: "VPMOVQD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVQD256", argLength: 1, reg: w11, asm: "VPMOVQD", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVQD256", argLength: 1, reg: w11, asm: "VPMOVQD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVQDMasked128", argLength: 2, reg: wkw, asm: "VPMOVQD", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVQDMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVQD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVQDMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVQD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVQDMasked256", argLength: 2, reg: wkw, asm: "VPMOVQD", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVQDMasked256", argLength: 2, reg: wkw, asm: "VPMOVQD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVQW128", argLength: 1, reg: w11, asm: "VPMOVQW", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVQW128_128", argLength: 1, reg: w11, asm: "VPMOVQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVQWMasked128", argLength: 2, reg: wkw, asm: "VPMOVQW", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVQW128_256", argLength: 1, reg: w11, asm: "VPMOVQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDB128", argLength: 1, reg: w11, asm: "VPMOVSDB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVQW128_512", argLength: 1, reg: w11, asm: "VPMOVQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDBMasked128", argLength: 2, reg: wkw, asm: "VPMOVSDB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVQWMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDW128", argLength: 1, reg: w11, asm: "VPMOVSDW", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVQWMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVQWMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDB128_128", argLength: 1, reg: w11, asm: "VPMOVSDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDB128_256", argLength: 1, reg: w11, asm: "VPMOVSDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDB128_512", argLength: 1, reg: w11, asm: "VPMOVSDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVSDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVSDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDBMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVSDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDW128_128", argLength: 1, reg: w11, asm: "VPMOVSDW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDW128_256", argLength: 1, reg: w11, asm: "VPMOVSDW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDW256", argLength: 1, reg: w11, asm: "VPMOVSDW", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVSDW256", argLength: 1, reg: w11, asm: "VPMOVSDW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVSDWMasked128", argLength: 2, reg: wkw, asm: "VPMOVSDW", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVSDWMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVSDW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDWMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVSDW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSDWMasked256", argLength: 2, reg: wkw, asm: "VPMOVSDW", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVSDWMasked256", argLength: 2, reg: wkw, asm: "VPMOVSDW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVSQB128", argLength: 1, reg: w11, asm: "VPMOVSQB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVSQB128_128", argLength: 1, reg: w11, asm: "VPMOVSQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQBMasked128", argLength: 2, reg: wkw, asm: "VPMOVSQB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVSQB128_256", argLength: 1, reg: w11, asm: "VPMOVSQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQD128", argLength: 1, reg: w11, asm: "VPMOVSQD", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVSQB128_512", argLength: 1, reg: w11, asm: "VPMOVSQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVSQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVSQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQBMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVSQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQD128_128", argLength: 1, reg: w11, asm: "VPMOVSQD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQD128_256", argLength: 1, reg: w11, asm: "VPMOVSQD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQD256", argLength: 1, reg: w11, asm: "VPMOVSQD", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVSQD256", argLength: 1, reg: w11, asm: "VPMOVSQD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVSQDMasked128", argLength: 2, reg: wkw, asm: "VPMOVSQD", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVSQDMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVSQD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQDMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVSQD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQDMasked256", argLength: 2, reg: wkw, asm: "VPMOVSQD", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVSQDMasked256", argLength: 2, reg: wkw, asm: "VPMOVSQD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVSQW128", argLength: 1, reg: w11, asm: "VPMOVSQW", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVSQW128_128", argLength: 1, reg: w11, asm: "VPMOVSQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQWMasked128", argLength: 2, reg: wkw, asm: "VPMOVSQW", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVSQW128_256", argLength: 1, reg: w11, asm: "VPMOVSQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSWB128", argLength: 1, reg: w11, asm: "VPMOVSWB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVSQW128_512", argLength: 1, reg: w11, asm: "VPMOVSQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQWMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVSQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQWMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVSQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSQWMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVSQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSWB128_128", argLength: 1, reg: w11, asm: "VPMOVSWB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSWB128_256", argLength: 1, reg: w11, asm: "VPMOVSWB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSWB256", argLength: 1, reg: w11, asm: "VPMOVSWB", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVSWB256", argLength: 1, reg: w11, asm: "VPMOVSWB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVSWBMasked128", argLength: 2, reg: wkw, asm: "VPMOVSWB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVSWBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVSWB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSWBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVSWB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSWBMasked256", argLength: 2, reg: wkw, asm: "VPMOVSWB", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVSWBMasked256", argLength: 2, reg: wkw, asm: "VPMOVSWB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVSXBD128", argLength: 1, reg: v11, asm: "VPMOVSXBD", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVSXBD128", argLength: 1, reg: v11, asm: "VPMOVSXBD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSXBD256", argLength: 1, reg: v11, asm: "VPMOVSXBD", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVSXBD256", argLength: 1, reg: v11, asm: "VPMOVSXBD", commutative: false, typ: "Vec256", resultInArg0: false},
@ -653,27 +687,47 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
{name: "VPMOVSXWQMasked128", argLength: 2, reg: wkw, asm: "VPMOVSXWQ", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVSXWQMasked128", argLength: 2, reg: wkw, asm: "VPMOVSXWQ", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVSXWQMasked256", argLength: 2, reg: wkw, asm: "VPMOVSXWQ", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVSXWQMasked256", argLength: 2, reg: wkw, asm: "VPMOVSXWQ", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVSXWQMasked512", argLength: 2, reg: wkw, asm: "VPMOVSXWQ", commutative: false, typ: "Vec512", resultInArg0: false}, {name: "VPMOVSXWQMasked512", argLength: 2, reg: wkw, asm: "VPMOVSXWQ", commutative: false, typ: "Vec512", resultInArg0: false},
{name: "VPMOVUSDB128", argLength: 1, reg: w11, asm: "VPMOVUSDB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVUSDB128_128", argLength: 1, reg: w11, asm: "VPMOVUSDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSDBMasked128", argLength: 2, reg: wkw, asm: "VPMOVUSDB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVUSDB128_256", argLength: 1, reg: w11, asm: "VPMOVUSDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSDW128", argLength: 1, reg: w11, asm: "VPMOVUSDW", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVUSDB128_512", argLength: 1, reg: w11, asm: "VPMOVUSDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSDBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVUSDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSDBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVUSDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSDBMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVUSDB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSDW128_128", argLength: 1, reg: w11, asm: "VPMOVUSDW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSDW128_256", argLength: 1, reg: w11, asm: "VPMOVUSDW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSDW256", argLength: 1, reg: w11, asm: "VPMOVUSDW", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVUSDW256", argLength: 1, reg: w11, asm: "VPMOVUSDW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVUSDWMasked128", argLength: 2, reg: wkw, asm: "VPMOVUSDW", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVUSDWMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVUSDW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSDWMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVUSDW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSDWMasked256", argLength: 2, reg: wkw, asm: "VPMOVUSDW", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVUSDWMasked256", argLength: 2, reg: wkw, asm: "VPMOVUSDW", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVUSQB128", argLength: 1, reg: w11, asm: "VPMOVUSQB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVUSQB128_128", argLength: 1, reg: w11, asm: "VPMOVUSQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQBMasked128", argLength: 2, reg: wkw, asm: "VPMOVUSQB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVUSQB128_256", argLength: 1, reg: w11, asm: "VPMOVUSQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQD128", argLength: 1, reg: w11, asm: "VPMOVUSQD", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVUSQB128_512", argLength: 1, reg: w11, asm: "VPMOVUSQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVUSQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVUSQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQBMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVUSQB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQD128_128", argLength: 1, reg: w11, asm: "VPMOVUSQD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQD128_256", argLength: 1, reg: w11, asm: "VPMOVUSQD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQD256", argLength: 1, reg: w11, asm: "VPMOVUSQD", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVUSQD256", argLength: 1, reg: w11, asm: "VPMOVUSQD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVUSQDMasked128", argLength: 2, reg: wkw, asm: "VPMOVUSQD", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVUSQDMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVUSQD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQDMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVUSQD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQDMasked256", argLength: 2, reg: wkw, asm: "VPMOVUSQD", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVUSQDMasked256", argLength: 2, reg: wkw, asm: "VPMOVUSQD", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVUSQW128", argLength: 1, reg: w11, asm: "VPMOVUSQW", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVUSQW128_128", argLength: 1, reg: w11, asm: "VPMOVUSQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQWMasked128", argLength: 2, reg: wkw, asm: "VPMOVUSQW", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVUSQW128_256", argLength: 1, reg: w11, asm: "VPMOVUSQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSWB128", argLength: 1, reg: w11, asm: "VPMOVUSWB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVUSQW128_512", argLength: 1, reg: w11, asm: "VPMOVUSQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQWMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVUSQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQWMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVUSQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSQWMasked128_512", argLength: 2, reg: wkw, asm: "VPMOVUSQW", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSWB128_128", argLength: 1, reg: w11, asm: "VPMOVUSWB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSWB128_256", argLength: 1, reg: w11, asm: "VPMOVUSWB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSWB256", argLength: 1, reg: w11, asm: "VPMOVUSWB", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVUSWB256", argLength: 1, reg: w11, asm: "VPMOVUSWB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVUSWBMasked128", argLength: 2, reg: wkw, asm: "VPMOVUSWB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVUSWBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVUSWB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSWBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVUSWB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVUSWBMasked256", argLength: 2, reg: wkw, asm: "VPMOVUSWB", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVUSWBMasked256", argLength: 2, reg: wkw, asm: "VPMOVUSWB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVWB128", argLength: 1, reg: w11, asm: "VPMOVWB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVWB128_128", argLength: 1, reg: w11, asm: "VPMOVWB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVWB128_256", argLength: 1, reg: w11, asm: "VPMOVWB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVWB256", argLength: 1, reg: w11, asm: "VPMOVWB", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVWB256", argLength: 1, reg: w11, asm: "VPMOVWB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVWBMasked128", argLength: 2, reg: wkw, asm: "VPMOVWB", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVWBMasked128_128", argLength: 2, reg: wkw, asm: "VPMOVWB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVWBMasked128_256", argLength: 2, reg: wkw, asm: "VPMOVWB", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVWBMasked256", argLength: 2, reg: wkw, asm: "VPMOVWB", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVWBMasked256", argLength: 2, reg: wkw, asm: "VPMOVWB", commutative: false, typ: "Vec256", resultInArg0: false},
{name: "VPMOVZXBD128", argLength: 1, reg: v11, asm: "VPMOVZXBD", commutative: false, typ: "Vec128", resultInArg0: false}, {name: "VPMOVZXBD128", argLength: 1, reg: v11, asm: "VPMOVZXBD", commutative: false, typ: "Vec128", resultInArg0: false},
{name: "VPMOVZXBD256", argLength: 1, reg: v11, asm: "VPMOVZXBD", commutative: false, typ: "Vec256", resultInArg0: false}, {name: "VPMOVZXBD256", argLength: 1, reg: v11, asm: "VPMOVZXBD", commutative: false, typ: "Vec256", resultInArg0: false},
@ -2064,21 +2118,38 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
{name: "VPMINUWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMINUW", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMINUWMasked128Merging", argLength: 4, reg: w3kw, asm: "VPMINUW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMINUWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMINUW", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VPMINUWMasked256Merging", argLength: 4, reg: w3kw, asm: "VPMINUW", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPMINUWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMINUW", commutative: false, typ: "Vec512", resultInArg0: true}, {name: "VPMINUWMasked512Merging", argLength: 4, reg: w3kw, asm: "VPMINUW", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPMOVDBMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVDB", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVDBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVDB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVDWMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVDW", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVDBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVDB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVDBMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVDB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVDWMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVDW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVDWMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVDW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVDWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVDW", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VPMOVDWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVDW", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPMOVQBMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVQB", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVQBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVQB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVQDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVQD", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVQBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVQB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVQBMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVQB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVQDMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVQD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVQDMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVQD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVQDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVQD", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VPMOVQDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVQD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPMOVQWMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVQW", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVQWMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVQW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSDBMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDB", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVQWMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVQW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSDWMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDW", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVQWMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVQW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSDBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSDBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSDBMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSDWMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSDWMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSDWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDW", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VPMOVSDWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSDW", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPMOVSQBMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQB", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVSQBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSQDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQD", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVSQBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSQBMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSQDMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSQDMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSQDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQD", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VPMOVSQDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPMOVSQWMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQW", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVSQWMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSWBMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSWB", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVSQWMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSQWMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSQW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSWBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSWB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSWBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSWB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSWBMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSWB", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VPMOVSWBMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSWB", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPMOVSXBDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXBD", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVSXBDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXBD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSXBDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXBD", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VPMOVSXBDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXBD", commutative: false, typ: "Vec256", resultInArg0: true},
@ -2098,16 +2169,26 @@ func simdAMD64Ops(v11, v21, v2k, vkv, v2kv, v2kk, v31, v3kv, vgpv, vgp, vfpv, vf
{name: "VPMOVSXWQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXWQ", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVSXWQMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXWQ", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVSXWQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXWQ", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VPMOVSXWQMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXWQ", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPMOVSXWQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXWQ", commutative: false, typ: "Vec512", resultInArg0: true}, {name: "VPMOVSXWQMasked512Merging", argLength: 3, reg: w2kw, asm: "VPMOVSXWQ", commutative: false, typ: "Vec512", resultInArg0: true},
{name: "VPMOVUSDBMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDB", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVUSDBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSDWMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDW", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVUSDBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSDBMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSDWMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSDWMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSDWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDW", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VPMOVUSDWMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSDW", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPMOVUSQBMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQB", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVUSQBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSQDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQD", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVUSQBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSQBMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSQDMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSQDMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSQDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQD", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VPMOVUSQDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQD", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPMOVUSQWMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQW", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVUSQWMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSWBMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSWB", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVUSQWMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSQWMasked128_512Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSQW", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSWBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSWB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSWBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSWB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVUSWBMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSWB", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VPMOVUSWBMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVUSWB", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPMOVWBMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVWB", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVWBMasked128_128Merging", argLength: 3, reg: w2kw, asm: "VPMOVWB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVWBMasked128_256Merging", argLength: 3, reg: w2kw, asm: "VPMOVWB", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVWBMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVWB", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VPMOVWBMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVWB", commutative: false, typ: "Vec256", resultInArg0: true},
{name: "VPMOVZXBDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXBD", commutative: false, typ: "Vec128", resultInArg0: true}, {name: "VPMOVZXBDMasked128Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXBD", commutative: false, typ: "Vec128", resultInArg0: true},
{name: "VPMOVZXBDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXBD", commutative: false, typ: "Vec256", resultInArg0: true}, {name: "VPMOVZXBDMasked256Merging", argLength: 3, reg: w2kw, asm: "VPMOVZXBD", commutative: false, typ: "Vec256", resultInArg0: true},

1458
src/cmd/compile/internal/ssa/opGen.go
View file

File diff suppressed because it is too large Load diff

12407
src/cmd/compile/internal/ssa/rewriteAMD64.go
View file

File diff suppressed because it is too large Load diff

21
src/simd/_gen/simdgen/gen_simdrules.go
View file

@ -318,13 +318,25 @@ func writeSIMDRules(ops []Operation) *bytes.Buffer {
case 128, 256: case 128, 256:
// VPBLENDVB cases. // VPBLENDVB cases.
noMaskName := machineOpName(NoMask, gOp) noMaskName := machineOpName(NoMask, gOp)
maskedMergeOpts[noMaskName] = fmt.Sprintf("(VPBLENDVB%d dst (%s %s) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (%sMerging dst %s (VPMOVVec%dx%dToM <types.TypeMask> mask))\n", ruleExisting, ok := maskedMergeOpts[noMaskName]
rule := fmt.Sprintf("(VPBLENDVB%d dst (%s %s) mask) && v.Block.CPUfeatures.hasFeature(CPUavx512) => (%sMerging dst %s (VPMOVVec%dx%dToM <types.TypeMask> mask))\n",
*maskElem.Bits, noMaskName, data.Args, data.Asm, data.Args, *maskElem.ElemBits, *maskElem.Lanes) *maskElem.Bits, noMaskName, data.Args, data.Asm, data.Args, *maskElem.ElemBits, *maskElem.Lanes)
if ok && ruleExisting != rule {
panic("multiple masked merge rules for one op")
} else {
maskedMergeOpts[noMaskName] = rule
}
case 512: case 512:
// VPBLENDM[BWDQ] cases. // VPBLENDM[BWDQ] cases.
noMaskName := machineOpName(NoMask, gOp) noMaskName := machineOpName(NoMask, gOp)
maskedMergeOpts[noMaskName] = fmt.Sprintf("(VPBLENDM%sMasked%d dst (%s %s) mask) => (%sMerging dst %s mask)\n", ruleExisting, ok := maskedMergeOpts[noMaskName]
rule := fmt.Sprintf("(VPBLENDM%sMasked%d dst (%s %s) mask) => (%sMerging dst %s mask)\n",
s2n[*maskElem.ElemBits], *maskElem.Bits, noMaskName, data.Args, data.Asm, data.Args) s2n[*maskElem.ElemBits], *maskElem.Bits, noMaskName, data.Args, data.Asm, data.Args)
if ok && ruleExisting != rule {
panic("multiple masked merge rules for one op")
} else {
maskedMergeOpts[noMaskName] = rule
}
} }
} }
@ -362,10 +374,15 @@ func writeSIMDRules(ops []Operation) *bytes.Buffer {
} }
} }
maskedMergeOptsRules := []string{}
for asm, rule := range maskedMergeOpts { for asm, rule := range maskedMergeOpts {
if !asmCheck[asm] { if !asmCheck[asm] {
continue continue
} }
maskedMergeOptsRules = append(maskedMergeOptsRules, rule)
}
slices.Sort(maskedMergeOptsRules)
for _, rule := range maskedMergeOptsRules {
buffer.WriteString(rule) buffer.WriteString(rule)
} }

24
src/simd/_gen/simdgen/godefs.go
View file

@ -133,6 +133,25 @@ func (o *Operation) VectorWidth() int {
panic(fmt.Errorf("Figure out what the vector width is for %v and implement it", *o)) panic(fmt.Errorf("Figure out what the vector width is for %v and implement it", *o))
} }
// Right now simdgen computes the machine op name for most instructions
// as $Name$OutputSize, by this denotation, these instructions are "overloaded".
// for example:
// (Uint16x8) ConvertToInt8
// (Uint16x16) ConvertToInt8
// are both VPMOVWB128.
// To make them distinguishable we need to append the input size to them as well.
// TODO: document them well in the generated code.
var demotingConvertOps = map[string]bool{
"VPMOVQD128": true, "VPMOVSQD128": true, "VPMOVUSQD128": true, "VPMOVQW128": true, "VPMOVSQW128": true,
"VPMOVUSQW128": true, "VPMOVDW128": true, "VPMOVSDW128": true, "VPMOVUSDW128": true, "VPMOVQB128": true,
"VPMOVSQB128": true, "VPMOVUSQB128": true, "VPMOVDB128": true, "VPMOVSDB128": true, "VPMOVUSDB128": true,
"VPMOVWB128": true, "VPMOVSWB128": true, "VPMOVUSWB128": true,
"VPMOVQDMasked128": true, "VPMOVSQDMasked128": true, "VPMOVUSQDMasked128": true, "VPMOVQWMasked128": true, "VPMOVSQWMasked128": true,
"VPMOVUSQWMasked128": true, "VPMOVDWMasked128": true, "VPMOVSDWMasked128": true, "VPMOVUSDWMasked128": true, "VPMOVQBMasked128": true,
"VPMOVSQBMasked128": true, "VPMOVUSQBMasked128": true, "VPMOVDBMasked128": true, "VPMOVSDBMasked128": true, "VPMOVUSDBMasked128": true,
"VPMOVWBMasked128": true, "VPMOVSWBMasked128": true, "VPMOVUSWBMasked128": true,
}
func machineOpName(maskType maskShape, gOp Operation) string { func machineOpName(maskType maskShape, gOp Operation) string {
asm := gOp.Asm asm := gOp.Asm
if maskType == OneMask { if maskType == OneMask {
@ -142,6 +161,11 @@ func machineOpName(maskType maskShape, gOp Operation) string {
if gOp.SSAVariant != nil { if gOp.SSAVariant != nil {
asm += *gOp.SSAVariant asm += *gOp.SSAVariant
} }
if demotingConvertOps[asm] {
// Need to append the size of the source as well.
// TODO: should be "%sto%d".
asm = fmt.Sprintf("%s_%d", asm, *gOp.In[0].Bits)
}
return asm return asm
} }