mirror of
https://github.com/golang/go.git
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[dev.simd] cmd/compile, simd: add shift operations
This CL is generated by CL 683475. Change-Id: I9e3ac6aff6f711cb26ff85e4c8729d9e2cc38e7d Reviewed-on: https://go-review.googlesource.com/c/go/+/683715 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Junyang Shao
parent
35b8cf7fed
commit
e61ebfce56
9 changed files with 16257 additions and 3 deletions
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@ -247,6 +247,18 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPHSUBW256,
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ssa.OpAMD64VPHSUBW256,
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ssa.OpAMD64VPHSUBD128,
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ssa.OpAMD64VPHSUBD128,
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ssa.OpAMD64VPHSUBD256,
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ssa.OpAMD64VPHSUBD256,
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ssa.OpAMD64VPROLVD128,
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ssa.OpAMD64VPROLVD256,
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ssa.OpAMD64VPROLVD512,
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ssa.OpAMD64VPROLVQ128,
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ssa.OpAMD64VPROLVQ256,
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ssa.OpAMD64VPROLVQ512,
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ssa.OpAMD64VPRORVD128,
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ssa.OpAMD64VPRORVD256,
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ssa.OpAMD64VPRORVD512,
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ssa.OpAMD64VPRORVQ128,
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ssa.OpAMD64VPRORVQ256,
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ssa.OpAMD64VPRORVQ512,
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ssa.OpAMD64VPADDSB128,
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ssa.OpAMD64VPADDSB128,
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ssa.OpAMD64VPADDSB256,
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ssa.OpAMD64VPADDSB256,
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ssa.OpAMD64VPADDSB512,
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ssa.OpAMD64VPADDSB512,
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@ -266,6 +278,33 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPMADDUBSW128,
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ssa.OpAMD64VPMADDUBSW128,
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ssa.OpAMD64VPMADDUBSW256,
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ssa.OpAMD64VPMADDUBSW256,
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ssa.OpAMD64VPMADDUBSW512,
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ssa.OpAMD64VPMADDUBSW512,
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ssa.OpAMD64VPSLLVW128,
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ssa.OpAMD64VPSLLVW256,
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ssa.OpAMD64VPSLLVW512,
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ssa.OpAMD64VPSLLVD128,
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ssa.OpAMD64VPSLLVD256,
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ssa.OpAMD64VPSLLVD512,
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ssa.OpAMD64VPSLLVQ128,
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ssa.OpAMD64VPSLLVQ256,
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ssa.OpAMD64VPSLLVQ512,
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ssa.OpAMD64VPSRLVW128,
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ssa.OpAMD64VPSRLVW256,
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ssa.OpAMD64VPSRLVW512,
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ssa.OpAMD64VPSRLVD128,
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ssa.OpAMD64VPSRLVD256,
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ssa.OpAMD64VPSRLVD512,
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ssa.OpAMD64VPSRLVQ128,
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ssa.OpAMD64VPSRLVQ256,
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ssa.OpAMD64VPSRLVQ512,
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ssa.OpAMD64VPSRAVW128,
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ssa.OpAMD64VPSRAVW256,
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ssa.OpAMD64VPSRAVW512,
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ssa.OpAMD64VPSRAVD128,
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ssa.OpAMD64VPSRAVD256,
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ssa.OpAMD64VPSRAVD512,
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ssa.OpAMD64VPSRAVQ128,
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ssa.OpAMD64VPSRAVQ256,
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ssa.OpAMD64VPSRAVQ512,
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ssa.OpAMD64VPSIGNB128,
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ssa.OpAMD64VPSIGNB128,
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ssa.OpAMD64VPSIGNB256,
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ssa.OpAMD64VPSIGNB256,
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ssa.OpAMD64VPSIGNW128,
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ssa.OpAMD64VPSIGNW128,
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@ -464,6 +503,18 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPMADDWDMasked128,
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ssa.OpAMD64VPMADDWDMasked128,
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ssa.OpAMD64VPMADDWDMasked256,
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ssa.OpAMD64VPMADDWDMasked256,
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ssa.OpAMD64VPMADDWDMasked512,
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ssa.OpAMD64VPMADDWDMasked512,
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ssa.OpAMD64VPROLVDMasked128,
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ssa.OpAMD64VPROLVDMasked256,
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ssa.OpAMD64VPROLVDMasked512,
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ssa.OpAMD64VPROLVQMasked128,
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ssa.OpAMD64VPROLVQMasked256,
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ssa.OpAMD64VPROLVQMasked512,
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ssa.OpAMD64VPRORVDMasked128,
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ssa.OpAMD64VPRORVDMasked256,
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ssa.OpAMD64VPRORVDMasked512,
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ssa.OpAMD64VPRORVQMasked128,
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ssa.OpAMD64VPRORVQMasked256,
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ssa.OpAMD64VPRORVQMasked512,
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ssa.OpAMD64VPADDSBMasked128,
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ssa.OpAMD64VPADDSBMasked128,
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ssa.OpAMD64VPADDSBMasked256,
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ssa.OpAMD64VPADDSBMasked256,
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ssa.OpAMD64VPADDSBMasked512,
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ssa.OpAMD64VPADDSBMasked512,
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@ -479,6 +530,33 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPMADDUBSWMasked128,
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ssa.OpAMD64VPMADDUBSWMasked128,
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ssa.OpAMD64VPMADDUBSWMasked256,
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ssa.OpAMD64VPMADDUBSWMasked256,
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ssa.OpAMD64VPMADDUBSWMasked512,
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ssa.OpAMD64VPMADDUBSWMasked512,
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ssa.OpAMD64VPSLLVWMasked128,
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ssa.OpAMD64VPSLLVWMasked256,
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ssa.OpAMD64VPSLLVWMasked512,
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ssa.OpAMD64VPSLLVDMasked128,
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ssa.OpAMD64VPSLLVDMasked256,
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ssa.OpAMD64VPSLLVDMasked512,
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ssa.OpAMD64VPSLLVQMasked128,
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ssa.OpAMD64VPSLLVQMasked256,
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ssa.OpAMD64VPSLLVQMasked512,
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ssa.OpAMD64VPSRLVWMasked128,
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ssa.OpAMD64VPSRLVWMasked256,
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ssa.OpAMD64VPSRLVWMasked512,
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ssa.OpAMD64VPSRLVDMasked128,
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ssa.OpAMD64VPSRLVDMasked256,
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ssa.OpAMD64VPSRLVDMasked512,
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ssa.OpAMD64VPSRLVQMasked128,
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ssa.OpAMD64VPSRLVQMasked256,
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ssa.OpAMD64VPSRLVQMasked512,
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ssa.OpAMD64VPSRAVWMasked128,
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ssa.OpAMD64VPSRAVWMasked256,
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ssa.OpAMD64VPSRAVWMasked512,
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ssa.OpAMD64VPSRAVDMasked128,
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ssa.OpAMD64VPSRAVDMasked256,
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ssa.OpAMD64VPSRAVDMasked512,
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ssa.OpAMD64VPSRAVQMasked128,
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ssa.OpAMD64VPSRAVQMasked256,
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ssa.OpAMD64VPSRAVQMasked512,
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ssa.OpAMD64VSUBPSMasked128,
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ssa.OpAMD64VSUBPSMasked128,
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ssa.OpAMD64VSUBPSMasked256,
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ssa.OpAMD64VSUBPSMasked256,
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ssa.OpAMD64VSUBPSMasked512,
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ssa.OpAMD64VSUBPSMasked512,
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@ -570,7 +648,19 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VREDUCEPS512,
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ssa.OpAMD64VREDUCEPS512,
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ssa.OpAMD64VREDUCEPD128,
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ssa.OpAMD64VREDUCEPD128,
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ssa.OpAMD64VREDUCEPD256,
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ssa.OpAMD64VREDUCEPD256,
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ssa.OpAMD64VREDUCEPD512:
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ssa.OpAMD64VREDUCEPD512,
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ssa.OpAMD64VPROLD128,
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ssa.OpAMD64VPROLD256,
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ssa.OpAMD64VPROLD512,
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ssa.OpAMD64VPROLQ128,
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ssa.OpAMD64VPROLQ256,
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ssa.OpAMD64VPROLQ512,
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ssa.OpAMD64VPRORD128,
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ssa.OpAMD64VPRORD256,
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ssa.OpAMD64VPRORD512,
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ssa.OpAMD64VPRORQ128,
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ssa.OpAMD64VPRORQ256,
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ssa.OpAMD64VPRORQ512:
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p = simdFp11Imm8(s, v)
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p = simdFp11Imm8(s, v)
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case ssa.OpAMD64VRNDSCALEPSMasked128,
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case ssa.OpAMD64VRNDSCALEPSMasked128,
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@ -584,14 +674,44 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VREDUCEPSMasked512,
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ssa.OpAMD64VREDUCEPSMasked512,
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ssa.OpAMD64VREDUCEPDMasked128,
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ssa.OpAMD64VREDUCEPDMasked128,
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ssa.OpAMD64VREDUCEPDMasked256,
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ssa.OpAMD64VREDUCEPDMasked256,
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ssa.OpAMD64VREDUCEPDMasked512:
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ssa.OpAMD64VREDUCEPDMasked512,
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ssa.OpAMD64VPROLDMasked128,
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ssa.OpAMD64VPROLDMasked256,
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ssa.OpAMD64VPROLDMasked512,
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ssa.OpAMD64VPROLQMasked128,
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ssa.OpAMD64VPROLQMasked256,
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ssa.OpAMD64VPROLQMasked512,
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ssa.OpAMD64VPRORDMasked128,
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ssa.OpAMD64VPRORDMasked256,
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ssa.OpAMD64VPRORDMasked512,
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ssa.OpAMD64VPRORQMasked128,
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ssa.OpAMD64VPRORQMasked256,
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ssa.OpAMD64VPRORQMasked512:
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p = simdFpkfpImm8(s, v)
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p = simdFpkfpImm8(s, v)
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case ssa.OpAMD64VDPPD128,
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case ssa.OpAMD64VDPPD128,
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ssa.OpAMD64VCMPPS128,
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ssa.OpAMD64VCMPPS128,
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ssa.OpAMD64VCMPPS256,
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ssa.OpAMD64VCMPPS256,
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ssa.OpAMD64VCMPPD128,
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ssa.OpAMD64VCMPPD128,
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ssa.OpAMD64VCMPPD256:
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ssa.OpAMD64VCMPPD256,
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ssa.OpAMD64VPSHLDW128,
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ssa.OpAMD64VPSHLDW256,
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ssa.OpAMD64VPSHLDW512,
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ssa.OpAMD64VPSHLDD128,
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ssa.OpAMD64VPSHLDD256,
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ssa.OpAMD64VPSHLDD512,
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ssa.OpAMD64VPSHLDQ128,
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ssa.OpAMD64VPSHLDQ256,
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ssa.OpAMD64VPSHLDQ512,
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ssa.OpAMD64VPSHRDW128,
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ssa.OpAMD64VPSHRDW256,
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ssa.OpAMD64VPSHRDW512,
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ssa.OpAMD64VPSHRDD128,
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ssa.OpAMD64VPSHRDD256,
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ssa.OpAMD64VPSHRDD512,
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ssa.OpAMD64VPSHRDQ128,
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ssa.OpAMD64VPSHRDQ256,
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ssa.OpAMD64VPSHRDQ512:
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p = simdFp21Imm8(s, v)
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p = simdFp21Imm8(s, v)
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case ssa.OpAMD64VCMPPS512,
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case ssa.OpAMD64VCMPPS512,
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@ -681,6 +801,24 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPDPBUSDS128,
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ssa.OpAMD64VPDPBUSDS128,
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ssa.OpAMD64VPDPBUSDS256,
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ssa.OpAMD64VPDPBUSDS256,
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ssa.OpAMD64VPDPBUSDS512,
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ssa.OpAMD64VPDPBUSDS512,
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ssa.OpAMD64VPSHLDVW128,
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ssa.OpAMD64VPSHLDVW256,
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ssa.OpAMD64VPSHLDVW512,
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ssa.OpAMD64VPSHLDVD128,
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ssa.OpAMD64VPSHLDVD256,
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ssa.OpAMD64VPSHLDVD512,
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ssa.OpAMD64VPSHLDVQ128,
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ssa.OpAMD64VPSHLDVQ256,
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ssa.OpAMD64VPSHLDVQ512,
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ssa.OpAMD64VPSHRDVW128,
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ssa.OpAMD64VPSHRDVW256,
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ssa.OpAMD64VPSHRDVW512,
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ssa.OpAMD64VPSHRDVD128,
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ssa.OpAMD64VPSHRDVD256,
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ssa.OpAMD64VPSHRDVD512,
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ssa.OpAMD64VPSHRDVQ128,
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ssa.OpAMD64VPSHRDVQ256,
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ssa.OpAMD64VPSHRDVQ512,
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ssa.OpAMD64VPDPBUSD128,
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ssa.OpAMD64VPDPBUSD128,
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ssa.OpAMD64VPDPBUSD256,
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ssa.OpAMD64VPDPBUSD256,
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ssa.OpAMD64VPDPBUSD512:
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ssa.OpAMD64VPDPBUSD512:
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@ -713,11 +851,63 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPDPBUSDSMasked128,
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ssa.OpAMD64VPDPBUSDSMasked128,
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ssa.OpAMD64VPDPBUSDSMasked256,
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ssa.OpAMD64VPDPBUSDSMasked256,
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ssa.OpAMD64VPDPBUSDSMasked512,
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ssa.OpAMD64VPDPBUSDSMasked512,
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ssa.OpAMD64VPSHLDVWMasked128,
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ssa.OpAMD64VPSHLDVWMasked256,
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ssa.OpAMD64VPSHLDVWMasked512,
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ssa.OpAMD64VPSHLDVDMasked128,
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ssa.OpAMD64VPSHLDVDMasked256,
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ssa.OpAMD64VPSHLDVDMasked512,
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ssa.OpAMD64VPSHLDVQMasked128,
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ssa.OpAMD64VPSHLDVQMasked256,
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ssa.OpAMD64VPSHLDVQMasked512,
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ssa.OpAMD64VPSHRDVWMasked128,
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ssa.OpAMD64VPSHRDVWMasked256,
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ssa.OpAMD64VPSHRDVWMasked512,
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ssa.OpAMD64VPSHRDVDMasked128,
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ssa.OpAMD64VPSHRDVDMasked256,
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ssa.OpAMD64VPSHRDVDMasked512,
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ssa.OpAMD64VPSHRDVQMasked128,
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ssa.OpAMD64VPSHRDVQMasked256,
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ssa.OpAMD64VPSHRDVQMasked512,
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ssa.OpAMD64VPDPBUSDMasked128,
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ssa.OpAMD64VPDPBUSDMasked128,
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ssa.OpAMD64VPDPBUSDMasked256,
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ssa.OpAMD64VPDPBUSDMasked256,
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ssa.OpAMD64VPDPBUSDMasked512:
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ssa.OpAMD64VPDPBUSDMasked512:
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p = simdFp3kfpResultInArg0(s, v)
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p = simdFp3kfpResultInArg0(s, v)
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case ssa.OpAMD64VPSLLW128,
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ssa.OpAMD64VPSLLW256,
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ssa.OpAMD64VPSLLD128,
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ssa.OpAMD64VPSLLD256,
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ssa.OpAMD64VPSLLQ128,
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ssa.OpAMD64VPSLLQ256,
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ssa.OpAMD64VPSLLQ512,
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ssa.OpAMD64VPSRLW128,
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ssa.OpAMD64VPSRLW256,
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ssa.OpAMD64VPSRLD128,
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ssa.OpAMD64VPSRLD256,
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ssa.OpAMD64VPSRLQ128,
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ssa.OpAMD64VPSRLQ256,
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ssa.OpAMD64VPSRLQ512,
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ssa.OpAMD64VPSRAW128,
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ssa.OpAMD64VPSRAW256,
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ssa.OpAMD64VPSRAD128,
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ssa.OpAMD64VPSRAD256,
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ssa.OpAMD64VPSRAQ128,
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ssa.OpAMD64VPSRAQ256,
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ssa.OpAMD64VPSRAQ512:
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p = simdFpXfp(s, v)
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case ssa.OpAMD64VPSLLQMasked128,
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ssa.OpAMD64VPSLLQMasked256,
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ssa.OpAMD64VPSLLQMasked512,
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ssa.OpAMD64VPSRLQMasked128,
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ssa.OpAMD64VPSRLQMasked256,
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ssa.OpAMD64VPSRLQMasked512,
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ssa.OpAMD64VPSRAQMasked128,
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ssa.OpAMD64VPSRAQMasked256,
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ssa.OpAMD64VPSRAQMasked512:
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p = simdFpXkfp(s, v)
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case ssa.OpAMD64VPINSRB128,
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case ssa.OpAMD64VPINSRB128,
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ssa.OpAMD64VPINSRW128,
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ssa.OpAMD64VPINSRW128,
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ssa.OpAMD64VPINSRD128,
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ssa.OpAMD64VPINSRD128,
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@ -730,6 +920,26 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
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ssa.OpAMD64VPEXTRQ128:
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ssa.OpAMD64VPEXTRQ128:
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p = simdFpgpImm8(s, v)
|
p = simdFpgpImm8(s, v)
|
||||||
|
|
||||||
|
case ssa.OpAMD64VPSHLDWMasked128,
|
||||||
|
ssa.OpAMD64VPSHLDWMasked256,
|
||||||
|
ssa.OpAMD64VPSHLDWMasked512,
|
||||||
|
ssa.OpAMD64VPSHLDDMasked128,
|
||||||
|
ssa.OpAMD64VPSHLDDMasked256,
|
||||||
|
ssa.OpAMD64VPSHLDDMasked512,
|
||||||
|
ssa.OpAMD64VPSHLDQMasked128,
|
||||||
|
ssa.OpAMD64VPSHLDQMasked256,
|
||||||
|
ssa.OpAMD64VPSHLDQMasked512,
|
||||||
|
ssa.OpAMD64VPSHRDWMasked128,
|
||||||
|
ssa.OpAMD64VPSHRDWMasked256,
|
||||||
|
ssa.OpAMD64VPSHRDWMasked512,
|
||||||
|
ssa.OpAMD64VPSHRDDMasked128,
|
||||||
|
ssa.OpAMD64VPSHRDDMasked256,
|
||||||
|
ssa.OpAMD64VPSHRDDMasked512,
|
||||||
|
ssa.OpAMD64VPSHRDQMasked128,
|
||||||
|
ssa.OpAMD64VPSHRDQMasked256,
|
||||||
|
ssa.OpAMD64VPSHRDQMasked512:
|
||||||
|
p = simdFp2kfpImm8(s, v)
|
||||||
|
|
||||||
default:
|
default:
|
||||||
// Unknown reg shape
|
// Unknown reg shape
|
||||||
return false
|
return false
|
||||||
|
|
@ -968,6 +1178,30 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
||||||
ssa.OpAMD64VPOPCNTQMasked128,
|
ssa.OpAMD64VPOPCNTQMasked128,
|
||||||
ssa.OpAMD64VPOPCNTQMasked256,
|
ssa.OpAMD64VPOPCNTQMasked256,
|
||||||
ssa.OpAMD64VPOPCNTQMasked512,
|
ssa.OpAMD64VPOPCNTQMasked512,
|
||||||
|
ssa.OpAMD64VPROLDMasked128,
|
||||||
|
ssa.OpAMD64VPROLDMasked256,
|
||||||
|
ssa.OpAMD64VPROLDMasked512,
|
||||||
|
ssa.OpAMD64VPROLQMasked128,
|
||||||
|
ssa.OpAMD64VPROLQMasked256,
|
||||||
|
ssa.OpAMD64VPROLQMasked512,
|
||||||
|
ssa.OpAMD64VPRORDMasked128,
|
||||||
|
ssa.OpAMD64VPRORDMasked256,
|
||||||
|
ssa.OpAMD64VPRORDMasked512,
|
||||||
|
ssa.OpAMD64VPRORQMasked128,
|
||||||
|
ssa.OpAMD64VPRORQMasked256,
|
||||||
|
ssa.OpAMD64VPRORQMasked512,
|
||||||
|
ssa.OpAMD64VPROLVDMasked128,
|
||||||
|
ssa.OpAMD64VPROLVDMasked256,
|
||||||
|
ssa.OpAMD64VPROLVDMasked512,
|
||||||
|
ssa.OpAMD64VPROLVQMasked128,
|
||||||
|
ssa.OpAMD64VPROLVQMasked256,
|
||||||
|
ssa.OpAMD64VPROLVQMasked512,
|
||||||
|
ssa.OpAMD64VPRORVDMasked128,
|
||||||
|
ssa.OpAMD64VPRORVDMasked256,
|
||||||
|
ssa.OpAMD64VPRORVDMasked512,
|
||||||
|
ssa.OpAMD64VPRORVQMasked128,
|
||||||
|
ssa.OpAMD64VPRORVQMasked256,
|
||||||
|
ssa.OpAMD64VPRORVQMasked512,
|
||||||
ssa.OpAMD64VPADDSBMasked128,
|
ssa.OpAMD64VPADDSBMasked128,
|
||||||
ssa.OpAMD64VPADDSBMasked256,
|
ssa.OpAMD64VPADDSBMasked256,
|
||||||
ssa.OpAMD64VPADDSBMasked512,
|
ssa.OpAMD64VPADDSBMasked512,
|
||||||
|
|
@ -989,6 +1223,78 @@ func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool {
|
||||||
ssa.OpAMD64VPDPBUSDSMasked128,
|
ssa.OpAMD64VPDPBUSDSMasked128,
|
||||||
ssa.OpAMD64VPDPBUSDSMasked256,
|
ssa.OpAMD64VPDPBUSDSMasked256,
|
||||||
ssa.OpAMD64VPDPBUSDSMasked512,
|
ssa.OpAMD64VPDPBUSDSMasked512,
|
||||||
|
ssa.OpAMD64VPSLLQMasked128,
|
||||||
|
ssa.OpAMD64VPSLLQMasked256,
|
||||||
|
ssa.OpAMD64VPSLLQMasked512,
|
||||||
|
ssa.OpAMD64VPSHLDWMasked128,
|
||||||
|
ssa.OpAMD64VPSHLDWMasked256,
|
||||||
|
ssa.OpAMD64VPSHLDWMasked512,
|
||||||
|
ssa.OpAMD64VPSHLDDMasked128,
|
||||||
|
ssa.OpAMD64VPSHLDDMasked256,
|
||||||
|
ssa.OpAMD64VPSHLDDMasked512,
|
||||||
|
ssa.OpAMD64VPSHLDQMasked128,
|
||||||
|
ssa.OpAMD64VPSHLDQMasked256,
|
||||||
|
ssa.OpAMD64VPSHLDQMasked512,
|
||||||
|
ssa.OpAMD64VPSRLQMasked128,
|
||||||
|
ssa.OpAMD64VPSRLQMasked256,
|
||||||
|
ssa.OpAMD64VPSRLQMasked512,
|
||||||
|
ssa.OpAMD64VPSHRDWMasked128,
|
||||||
|
ssa.OpAMD64VPSHRDWMasked256,
|
||||||
|
ssa.OpAMD64VPSHRDWMasked512,
|
||||||
|
ssa.OpAMD64VPSHRDDMasked128,
|
||||||
|
ssa.OpAMD64VPSHRDDMasked256,
|
||||||
|
ssa.OpAMD64VPSHRDDMasked512,
|
||||||
|
ssa.OpAMD64VPSHRDQMasked128,
|
||||||
|
ssa.OpAMD64VPSHRDQMasked256,
|
||||||
|
ssa.OpAMD64VPSHRDQMasked512,
|
||||||
|
ssa.OpAMD64VPSRAQMasked128,
|
||||||
|
ssa.OpAMD64VPSRAQMasked256,
|
||||||
|
ssa.OpAMD64VPSRAQMasked512,
|
||||||
|
ssa.OpAMD64VPSLLVWMasked128,
|
||||||
|
ssa.OpAMD64VPSLLVWMasked256,
|
||||||
|
ssa.OpAMD64VPSLLVWMasked512,
|
||||||
|
ssa.OpAMD64VPSLLVDMasked128,
|
||||||
|
ssa.OpAMD64VPSLLVDMasked256,
|
||||||
|
ssa.OpAMD64VPSLLVDMasked512,
|
||||||
|
ssa.OpAMD64VPSLLVQMasked128,
|
||||||
|
ssa.OpAMD64VPSLLVQMasked256,
|
||||||
|
ssa.OpAMD64VPSLLVQMasked512,
|
||||||
|
ssa.OpAMD64VPSHLDVWMasked128,
|
||||||
|
ssa.OpAMD64VPSHLDVWMasked256,
|
||||||
|
ssa.OpAMD64VPSHLDVWMasked512,
|
||||||
|
ssa.OpAMD64VPSHLDVDMasked128,
|
||||||
|
ssa.OpAMD64VPSHLDVDMasked256,
|
||||||
|
ssa.OpAMD64VPSHLDVDMasked512,
|
||||||
|
ssa.OpAMD64VPSHLDVQMasked128,
|
||||||
|
ssa.OpAMD64VPSHLDVQMasked256,
|
||||||
|
ssa.OpAMD64VPSHLDVQMasked512,
|
||||||
|
ssa.OpAMD64VPSRLVWMasked128,
|
||||||
|
ssa.OpAMD64VPSRLVWMasked256,
|
||||||
|
ssa.OpAMD64VPSRLVWMasked512,
|
||||||
|
ssa.OpAMD64VPSRLVDMasked128,
|
||||||
|
ssa.OpAMD64VPSRLVDMasked256,
|
||||||
|
ssa.OpAMD64VPSRLVDMasked512,
|
||||||
|
ssa.OpAMD64VPSRLVQMasked128,
|
||||||
|
ssa.OpAMD64VPSRLVQMasked256,
|
||||||
|
ssa.OpAMD64VPSRLVQMasked512,
|
||||||
|
ssa.OpAMD64VPSHRDVWMasked128,
|
||||||
|
ssa.OpAMD64VPSHRDVWMasked256,
|
||||||
|
ssa.OpAMD64VPSHRDVWMasked512,
|
||||||
|
ssa.OpAMD64VPSHRDVDMasked128,
|
||||||
|
ssa.OpAMD64VPSHRDVDMasked256,
|
||||||
|
ssa.OpAMD64VPSHRDVDMasked512,
|
||||||
|
ssa.OpAMD64VPSHRDVQMasked128,
|
||||||
|
ssa.OpAMD64VPSHRDVQMasked256,
|
||||||
|
ssa.OpAMD64VPSHRDVQMasked512,
|
||||||
|
ssa.OpAMD64VPSRAVWMasked128,
|
||||||
|
ssa.OpAMD64VPSRAVWMasked256,
|
||||||
|
ssa.OpAMD64VPSRAVWMasked512,
|
||||||
|
ssa.OpAMD64VPSRAVDMasked128,
|
||||||
|
ssa.OpAMD64VPSRAVDMasked256,
|
||||||
|
ssa.OpAMD64VPSRAVDMasked512,
|
||||||
|
ssa.OpAMD64VPSRAVQMasked128,
|
||||||
|
ssa.OpAMD64VPSRAVQMasked256,
|
||||||
|
ssa.OpAMD64VPSRAVQMasked512,
|
||||||
ssa.OpAMD64VSQRTPSMasked128,
|
ssa.OpAMD64VSQRTPSMasked128,
|
||||||
ssa.OpAMD64VSQRTPSMasked256,
|
ssa.OpAMD64VSQRTPSMasked256,
|
||||||
ssa.OpAMD64VSQRTPSMasked512,
|
ssa.OpAMD64VSQRTPSMasked512,
|
||||||
|
|
|
||||||
|
|
@ -904,6 +904,54 @@
|
||||||
(MaskedPopCountUint64x2 x mask) => (VPOPCNTQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
(MaskedPopCountUint64x2 x mask) => (VPOPCNTQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
(MaskedPopCountUint64x4 x mask) => (VPOPCNTQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
(MaskedPopCountUint64x4 x mask) => (VPOPCNTQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
(MaskedPopCountUint64x8 x mask) => (VPOPCNTQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
(MaskedPopCountUint64x8 x mask) => (VPOPCNTQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllLeftInt32x4 [a] x mask) => (VPROLDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllLeftInt32x8 [a] x mask) => (VPROLDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllLeftInt32x16 [a] x mask) => (VPROLDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllLeftInt64x2 [a] x mask) => (VPROLQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllLeftInt64x4 [a] x mask) => (VPROLQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllLeftInt64x8 [a] x mask) => (VPROLQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllLeftUint32x4 [a] x mask) => (VPROLDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllLeftUint32x8 [a] x mask) => (VPROLDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllLeftUint32x16 [a] x mask) => (VPROLDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllLeftUint64x2 [a] x mask) => (VPROLQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllLeftUint64x4 [a] x mask) => (VPROLQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllLeftUint64x8 [a] x mask) => (VPROLQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllRightInt32x4 [a] x mask) => (VPRORDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllRightInt32x8 [a] x mask) => (VPRORDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllRightInt32x16 [a] x mask) => (VPRORDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllRightInt64x2 [a] x mask) => (VPRORQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllRightInt64x4 [a] x mask) => (VPRORQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllRightInt64x8 [a] x mask) => (VPRORQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllRightUint32x4 [a] x mask) => (VPRORDMasked128 [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllRightUint32x8 [a] x mask) => (VPRORDMasked256 [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllRightUint32x16 [a] x mask) => (VPRORDMasked512 [a] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllRightUint64x2 [a] x mask) => (VPRORQMasked128 [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllRightUint64x4 [a] x mask) => (VPRORQMasked256 [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateAllRightUint64x8 [a] x mask) => (VPRORQMasked512 [a] x (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateLeftInt32x4 x y mask) => (VPROLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateLeftInt32x8 x y mask) => (VPROLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateLeftInt32x16 x y mask) => (VPROLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateLeftInt64x2 x y mask) => (VPROLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateLeftInt64x4 x y mask) => (VPROLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateLeftInt64x8 x y mask) => (VPROLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateLeftUint32x4 x y mask) => (VPROLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateLeftUint32x8 x y mask) => (VPROLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateLeftUint32x16 x y mask) => (VPROLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateLeftUint64x2 x y mask) => (VPROLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateLeftUint64x4 x y mask) => (VPROLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateLeftUint64x8 x y mask) => (VPROLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateRightInt32x4 x y mask) => (VPRORVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateRightInt32x8 x y mask) => (VPRORVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateRightInt32x16 x y mask) => (VPRORVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateRightInt64x2 x y mask) => (VPRORVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateRightInt64x4 x y mask) => (VPRORVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateRightInt64x8 x y mask) => (VPRORVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateRightUint32x4 x y mask) => (VPRORVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateRightUint32x8 x y mask) => (VPRORVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateRightUint32x16 x y mask) => (VPRORVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateRightUint64x2 x y mask) => (VPRORVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateRightUint64x4 x y mask) => (VPRORVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedRotateRightUint64x8 x y mask) => (VPRORVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
(MaskedRoundSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+8] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
(MaskedRoundSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+8] x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
(MaskedRoundSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+8] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
(MaskedRoundSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+8] x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
(MaskedRoundSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+8] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
(MaskedRoundSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+8] x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
|
@ -952,6 +1000,147 @@
|
||||||
(MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4 x y z mask) => (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
(MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4 x y z mask) => (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
(MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8 x y z mask) => (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
(MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8 x y z mask) => (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
(MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16 x y z mask) => (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
(MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16 x y z mask) => (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftInt64x2 x y mask) => (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftInt64x4 x y mask) => (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftInt64x8 x y mask) => (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftUint64x2 x y mask) => (VPSLLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftUint64x4 x y mask) => (VPSLLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftUint64x8 x y mask) => (VPSLLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromInt16x8 [a] x y mask) => (VPSHLDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromInt16x16 [a] x y mask) => (VPSHLDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromInt16x32 [a] x y mask) => (VPSHLDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromInt32x4 [a] x y mask) => (VPSHLDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromInt32x8 [a] x y mask) => (VPSHLDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromInt32x16 [a] x y mask) => (VPSHLDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromInt64x2 [a] x y mask) => (VPSHLDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromInt64x4 [a] x y mask) => (VPSHLDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromInt64x8 [a] x y mask) => (VPSHLDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromUint16x8 [a] x y mask) => (VPSHLDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromUint16x16 [a] x y mask) => (VPSHLDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromUint16x32 [a] x y mask) => (VPSHLDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromUint32x4 [a] x y mask) => (VPSHLDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromUint32x8 [a] x y mask) => (VPSHLDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromUint32x16 [a] x y mask) => (VPSHLDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromUint64x2 [a] x y mask) => (VPSHLDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromUint64x4 [a] x y mask) => (VPSHLDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllLeftAndFillUpperFromUint64x8 [a] x y mask) => (VPSHLDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightInt64x2 x y mask) => (VPSRLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightInt64x4 x y mask) => (VPSRLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightInt64x8 x y mask) => (VPSRLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightUint64x2 x y mask) => (VPSRLQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightUint64x4 x y mask) => (VPSRLQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightUint64x8 x y mask) => (VPSRLQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromInt16x8 [a] x y mask) => (VPSHRDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromInt16x16 [a] x y mask) => (VPSHRDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromInt16x32 [a] x y mask) => (VPSHRDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromInt32x4 [a] x y mask) => (VPSHRDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromInt32x8 [a] x y mask) => (VPSHRDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromInt32x16 [a] x y mask) => (VPSHRDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromInt64x2 [a] x y mask) => (VPSHRDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromInt64x4 [a] x y mask) => (VPSHRDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromInt64x8 [a] x y mask) => (VPSHRDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromUint16x8 [a] x y mask) => (VPSHRDWMasked128 [a] x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromUint16x16 [a] x y mask) => (VPSHRDWMasked256 [a] x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromUint16x32 [a] x y mask) => (VPSHRDWMasked512 [a] x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromUint32x4 [a] x y mask) => (VPSHRDDMasked128 [a] x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromUint32x8 [a] x y mask) => (VPSHRDDMasked256 [a] x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromUint32x16 [a] x y mask) => (VPSHRDDMasked512 [a] x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromUint64x2 [a] x y mask) => (VPSHRDQMasked128 [a] x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromUint64x4 [a] x y mask) => (VPSHRDQMasked256 [a] x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightAndFillUpperFromUint64x8 [a] x y mask) => (VPSHRDQMasked512 [a] x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightSignExtendedInt64x2 x y mask) => (VPSRAQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightSignExtendedInt64x4 x y mask) => (VPSRAQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftAllRightSignExtendedInt64x8 x y mask) => (VPSRAQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftInt16x8 x y mask) => (VPSLLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftInt16x16 x y mask) => (VPSLLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftInt16x32 x y mask) => (VPSLLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftInt32x4 x y mask) => (VPSLLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftInt32x8 x y mask) => (VPSLLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftInt32x16 x y mask) => (VPSLLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftInt64x2 x y mask) => (VPSLLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftInt64x4 x y mask) => (VPSLLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftInt64x8 x y mask) => (VPSLLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftUint16x8 x y mask) => (VPSLLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftUint16x16 x y mask) => (VPSLLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftUint16x32 x y mask) => (VPSLLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftUint32x4 x y mask) => (VPSLLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftUint32x8 x y mask) => (VPSLLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftUint32x16 x y mask) => (VPSLLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftUint64x2 x y mask) => (VPSLLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftUint64x4 x y mask) => (VPSLLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftUint64x8 x y mask) => (VPSLLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromInt16x8 x y z mask) => (VPSHLDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromInt16x16 x y z mask) => (VPSHLDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromInt16x32 x y z mask) => (VPSHLDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromInt32x4 x y z mask) => (VPSHLDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromInt32x8 x y z mask) => (VPSHLDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromInt32x16 x y z mask) => (VPSHLDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromInt64x2 x y z mask) => (VPSHLDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromInt64x4 x y z mask) => (VPSHLDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromInt64x8 x y z mask) => (VPSHLDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromUint16x8 x y z mask) => (VPSHLDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromUint16x16 x y z mask) => (VPSHLDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromUint16x32 x y z mask) => (VPSHLDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromUint32x4 x y z mask) => (VPSHLDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromUint32x8 x y z mask) => (VPSHLDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromUint32x16 x y z mask) => (VPSHLDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromUint64x2 x y z mask) => (VPSHLDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromUint64x4 x y z mask) => (VPSHLDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftLeftAndFillUpperFromUint64x8 x y z mask) => (VPSHLDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightInt16x8 x y mask) => (VPSRLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightInt16x16 x y mask) => (VPSRLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightInt16x32 x y mask) => (VPSRLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightInt32x4 x y mask) => (VPSRLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightInt32x8 x y mask) => (VPSRLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightInt32x16 x y mask) => (VPSRLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightInt64x2 x y mask) => (VPSRLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightInt64x4 x y mask) => (VPSRLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightInt64x8 x y mask) => (VPSRLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightUint16x8 x y mask) => (VPSRLVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightUint16x16 x y mask) => (VPSRLVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightUint16x32 x y mask) => (VPSRLVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightUint32x4 x y mask) => (VPSRLVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightUint32x8 x y mask) => (VPSRLVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightUint32x16 x y mask) => (VPSRLVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightUint64x2 x y mask) => (VPSRLVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightUint64x4 x y mask) => (VPSRLVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightUint64x8 x y mask) => (VPSRLVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromInt16x8 x y z mask) => (VPSHRDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromInt16x16 x y z mask) => (VPSHRDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromInt16x32 x y z mask) => (VPSHRDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromInt32x4 x y z mask) => (VPSHRDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromInt32x8 x y z mask) => (VPSHRDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromInt32x16 x y z mask) => (VPSHRDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromInt64x2 x y z mask) => (VPSHRDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromInt64x4 x y z mask) => (VPSHRDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromInt64x8 x y z mask) => (VPSHRDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromUint16x8 x y z mask) => (VPSHRDVWMasked128 x y z (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromUint16x16 x y z mask) => (VPSHRDVWMasked256 x y z (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromUint16x32 x y z mask) => (VPSHRDVWMasked512 x y z (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromUint32x4 x y z mask) => (VPSHRDVDMasked128 x y z (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromUint32x8 x y z mask) => (VPSHRDVDMasked256 x y z (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromUint32x16 x y z mask) => (VPSHRDVDMasked512 x y z (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromUint64x2 x y z mask) => (VPSHRDVQMasked128 x y z (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromUint64x4 x y z mask) => (VPSHRDVQMasked256 x y z (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightAndFillUpperFromUint64x8 x y z mask) => (VPSHRDVQMasked512 x y z (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedInt16x8 x y mask) => (VPSRAVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedInt16x16 x y mask) => (VPSRAVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedInt16x32 x y mask) => (VPSRAVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedInt32x4 x y mask) => (VPSRAVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedInt32x8 x y mask) => (VPSRAVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedInt32x16 x y mask) => (VPSRAVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedInt64x2 x y mask) => (VPSRAVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedInt64x4 x y mask) => (VPSRAVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedInt64x8 x y mask) => (VPSRAVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedUint16x8 x y mask) => (VPSRAVWMasked128 x y (VPMOVVec16x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedUint16x16 x y mask) => (VPSRAVWMasked256 x y (VPMOVVec16x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedUint16x32 x y mask) => (VPSRAVWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedUint32x4 x y mask) => (VPSRAVDMasked128 x y (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedUint32x8 x y mask) => (VPSRAVDMasked256 x y (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedUint32x16 x y mask) => (VPSRAVDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedUint64x2 x y mask) => (VPSRAVQMasked128 x y (VPMOVVec64x2ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedUint64x4 x y mask) => (VPSRAVQMasked256 x y (VPMOVVec64x4ToM <types.TypeMask> mask))
|
||||||
|
(MaskedShiftRightSignExtendedUint64x8 x y mask) => (VPSRAVQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
|
||||||
(MaskedSqrtFloat32x4 x mask) => (VSQRTPSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
(MaskedSqrtFloat32x4 x mask) => (VSQRTPSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
|
||||||
(MaskedSqrtFloat32x8 x mask) => (VSQRTPSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
(MaskedSqrtFloat32x8 x mask) => (VSQRTPSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
|
||||||
(MaskedSqrtFloat32x16 x mask) => (VSQRTPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
(MaskedSqrtFloat32x16 x mask) => (VSQRTPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
|
||||||
|
|
@ -1231,6 +1420,54 @@
|
||||||
(PopCountUint64x2 ...) => (VPOPCNTQ128 ...)
|
(PopCountUint64x2 ...) => (VPOPCNTQ128 ...)
|
||||||
(PopCountUint64x4 ...) => (VPOPCNTQ256 ...)
|
(PopCountUint64x4 ...) => (VPOPCNTQ256 ...)
|
||||||
(PopCountUint64x8 ...) => (VPOPCNTQ512 ...)
|
(PopCountUint64x8 ...) => (VPOPCNTQ512 ...)
|
||||||
|
(RotateAllLeftInt32x4 [a] x) => (VPROLD128 [a] x)
|
||||||
|
(RotateAllLeftInt32x8 [a] x) => (VPROLD256 [a] x)
|
||||||
|
(RotateAllLeftInt32x16 [a] x) => (VPROLD512 [a] x)
|
||||||
|
(RotateAllLeftInt64x2 [a] x) => (VPROLQ128 [a] x)
|
||||||
|
(RotateAllLeftInt64x4 [a] x) => (VPROLQ256 [a] x)
|
||||||
|
(RotateAllLeftInt64x8 [a] x) => (VPROLQ512 [a] x)
|
||||||
|
(RotateAllLeftUint32x4 [a] x) => (VPROLD128 [a] x)
|
||||||
|
(RotateAllLeftUint32x8 [a] x) => (VPROLD256 [a] x)
|
||||||
|
(RotateAllLeftUint32x16 [a] x) => (VPROLD512 [a] x)
|
||||||
|
(RotateAllLeftUint64x2 [a] x) => (VPROLQ128 [a] x)
|
||||||
|
(RotateAllLeftUint64x4 [a] x) => (VPROLQ256 [a] x)
|
||||||
|
(RotateAllLeftUint64x8 [a] x) => (VPROLQ512 [a] x)
|
||||||
|
(RotateAllRightInt32x4 [a] x) => (VPRORD128 [a] x)
|
||||||
|
(RotateAllRightInt32x8 [a] x) => (VPRORD256 [a] x)
|
||||||
|
(RotateAllRightInt32x16 [a] x) => (VPRORD512 [a] x)
|
||||||
|
(RotateAllRightInt64x2 [a] x) => (VPRORQ128 [a] x)
|
||||||
|
(RotateAllRightInt64x4 [a] x) => (VPRORQ256 [a] x)
|
||||||
|
(RotateAllRightInt64x8 [a] x) => (VPRORQ512 [a] x)
|
||||||
|
(RotateAllRightUint32x4 [a] x) => (VPRORD128 [a] x)
|
||||||
|
(RotateAllRightUint32x8 [a] x) => (VPRORD256 [a] x)
|
||||||
|
(RotateAllRightUint32x16 [a] x) => (VPRORD512 [a] x)
|
||||||
|
(RotateAllRightUint64x2 [a] x) => (VPRORQ128 [a] x)
|
||||||
|
(RotateAllRightUint64x4 [a] x) => (VPRORQ256 [a] x)
|
||||||
|
(RotateAllRightUint64x8 [a] x) => (VPRORQ512 [a] x)
|
||||||
|
(RotateLeftInt32x4 ...) => (VPROLVD128 ...)
|
||||||
|
(RotateLeftInt32x8 ...) => (VPROLVD256 ...)
|
||||||
|
(RotateLeftInt32x16 ...) => (VPROLVD512 ...)
|
||||||
|
(RotateLeftInt64x2 ...) => (VPROLVQ128 ...)
|
||||||
|
(RotateLeftInt64x4 ...) => (VPROLVQ256 ...)
|
||||||
|
(RotateLeftInt64x8 ...) => (VPROLVQ512 ...)
|
||||||
|
(RotateLeftUint32x4 ...) => (VPROLVD128 ...)
|
||||||
|
(RotateLeftUint32x8 ...) => (VPROLVD256 ...)
|
||||||
|
(RotateLeftUint32x16 ...) => (VPROLVD512 ...)
|
||||||
|
(RotateLeftUint64x2 ...) => (VPROLVQ128 ...)
|
||||||
|
(RotateLeftUint64x4 ...) => (VPROLVQ256 ...)
|
||||||
|
(RotateLeftUint64x8 ...) => (VPROLVQ512 ...)
|
||||||
|
(RotateRightInt32x4 ...) => (VPRORVD128 ...)
|
||||||
|
(RotateRightInt32x8 ...) => (VPRORVD256 ...)
|
||||||
|
(RotateRightInt32x16 ...) => (VPRORVD512 ...)
|
||||||
|
(RotateRightInt64x2 ...) => (VPRORVQ128 ...)
|
||||||
|
(RotateRightInt64x4 ...) => (VPRORVQ256 ...)
|
||||||
|
(RotateRightInt64x8 ...) => (VPRORVQ512 ...)
|
||||||
|
(RotateRightUint32x4 ...) => (VPRORVD128 ...)
|
||||||
|
(RotateRightUint32x8 ...) => (VPRORVD256 ...)
|
||||||
|
(RotateRightUint32x16 ...) => (VPRORVD512 ...)
|
||||||
|
(RotateRightUint64x2 ...) => (VPRORVQ128 ...)
|
||||||
|
(RotateRightUint64x4 ...) => (VPRORVQ256 ...)
|
||||||
|
(RotateRightUint64x8 ...) => (VPRORVQ512 ...)
|
||||||
(RoundFloat32x4 x) => (VROUNDPS128 [0] x)
|
(RoundFloat32x4 x) => (VROUNDPS128 [0] x)
|
||||||
(RoundFloat32x8 x) => (VROUNDPS256 [0] x)
|
(RoundFloat32x8 x) => (VROUNDPS256 [0] x)
|
||||||
(RoundFloat64x2 x) => (VROUNDPD128 [0] x)
|
(RoundFloat64x2 x) => (VROUNDPD128 [0] x)
|
||||||
|
|
@ -1295,6 +1532,167 @@
|
||||||
(SetElemUint16x8 [a] x y) => (VPINSRW128 [a] x y)
|
(SetElemUint16x8 [a] x y) => (VPINSRW128 [a] x y)
|
||||||
(SetElemUint32x4 [a] x y) => (VPINSRD128 [a] x y)
|
(SetElemUint32x4 [a] x y) => (VPINSRD128 [a] x y)
|
||||||
(SetElemUint64x2 [a] x y) => (VPINSRQ128 [a] x y)
|
(SetElemUint64x2 [a] x y) => (VPINSRQ128 [a] x y)
|
||||||
|
(ShiftAllLeftInt16x8 ...) => (VPSLLW128 ...)
|
||||||
|
(ShiftAllLeftInt16x16 ...) => (VPSLLW256 ...)
|
||||||
|
(ShiftAllLeftInt32x4 ...) => (VPSLLD128 ...)
|
||||||
|
(ShiftAllLeftInt32x8 ...) => (VPSLLD256 ...)
|
||||||
|
(ShiftAllLeftInt64x2 ...) => (VPSLLQ128 ...)
|
||||||
|
(ShiftAllLeftInt64x4 ...) => (VPSLLQ256 ...)
|
||||||
|
(ShiftAllLeftInt64x8 ...) => (VPSLLQ512 ...)
|
||||||
|
(ShiftAllLeftUint16x8 ...) => (VPSLLW128 ...)
|
||||||
|
(ShiftAllLeftUint16x16 ...) => (VPSLLW256 ...)
|
||||||
|
(ShiftAllLeftUint32x4 ...) => (VPSLLD128 ...)
|
||||||
|
(ShiftAllLeftUint32x8 ...) => (VPSLLD256 ...)
|
||||||
|
(ShiftAllLeftUint64x2 ...) => (VPSLLQ128 ...)
|
||||||
|
(ShiftAllLeftUint64x4 ...) => (VPSLLQ256 ...)
|
||||||
|
(ShiftAllLeftUint64x8 ...) => (VPSLLQ512 ...)
|
||||||
|
(ShiftAllLeftAndFillUpperFromInt16x8 [a] x y) => (VPSHLDW128 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromInt16x16 [a] x y) => (VPSHLDW256 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromInt16x32 [a] x y) => (VPSHLDW512 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromInt32x4 [a] x y) => (VPSHLDD128 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromInt32x8 [a] x y) => (VPSHLDD256 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromInt32x16 [a] x y) => (VPSHLDD512 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromInt64x2 [a] x y) => (VPSHLDQ128 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromInt64x4 [a] x y) => (VPSHLDQ256 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromInt64x8 [a] x y) => (VPSHLDQ512 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromUint16x8 [a] x y) => (VPSHLDW128 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromUint16x16 [a] x y) => (VPSHLDW256 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromUint16x32 [a] x y) => (VPSHLDW512 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromUint32x4 [a] x y) => (VPSHLDD128 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromUint32x8 [a] x y) => (VPSHLDD256 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromUint32x16 [a] x y) => (VPSHLDD512 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromUint64x2 [a] x y) => (VPSHLDQ128 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromUint64x4 [a] x y) => (VPSHLDQ256 [a] x y)
|
||||||
|
(ShiftAllLeftAndFillUpperFromUint64x8 [a] x y) => (VPSHLDQ512 [a] x y)
|
||||||
|
(ShiftAllRightInt16x8 ...) => (VPSRLW128 ...)
|
||||||
|
(ShiftAllRightInt16x16 ...) => (VPSRLW256 ...)
|
||||||
|
(ShiftAllRightInt32x4 ...) => (VPSRLD128 ...)
|
||||||
|
(ShiftAllRightInt32x8 ...) => (VPSRLD256 ...)
|
||||||
|
(ShiftAllRightInt64x2 ...) => (VPSRLQ128 ...)
|
||||||
|
(ShiftAllRightInt64x4 ...) => (VPSRLQ256 ...)
|
||||||
|
(ShiftAllRightInt64x8 ...) => (VPSRLQ512 ...)
|
||||||
|
(ShiftAllRightUint16x8 ...) => (VPSRLW128 ...)
|
||||||
|
(ShiftAllRightUint16x16 ...) => (VPSRLW256 ...)
|
||||||
|
(ShiftAllRightUint32x4 ...) => (VPSRLD128 ...)
|
||||||
|
(ShiftAllRightUint32x8 ...) => (VPSRLD256 ...)
|
||||||
|
(ShiftAllRightUint64x2 ...) => (VPSRLQ128 ...)
|
||||||
|
(ShiftAllRightUint64x4 ...) => (VPSRLQ256 ...)
|
||||||
|
(ShiftAllRightUint64x8 ...) => (VPSRLQ512 ...)
|
||||||
|
(ShiftAllRightAndFillUpperFromInt16x8 [a] x y) => (VPSHRDW128 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromInt16x16 [a] x y) => (VPSHRDW256 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromInt16x32 [a] x y) => (VPSHRDW512 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromInt32x4 [a] x y) => (VPSHRDD128 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromInt32x8 [a] x y) => (VPSHRDD256 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromInt32x16 [a] x y) => (VPSHRDD512 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromInt64x2 [a] x y) => (VPSHRDQ128 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromInt64x4 [a] x y) => (VPSHRDQ256 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromInt64x8 [a] x y) => (VPSHRDQ512 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromUint16x8 [a] x y) => (VPSHRDW128 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromUint16x16 [a] x y) => (VPSHRDW256 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromUint16x32 [a] x y) => (VPSHRDW512 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromUint32x4 [a] x y) => (VPSHRDD128 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromUint32x8 [a] x y) => (VPSHRDD256 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromUint32x16 [a] x y) => (VPSHRDD512 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromUint64x2 [a] x y) => (VPSHRDQ128 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromUint64x4 [a] x y) => (VPSHRDQ256 [a] x y)
|
||||||
|
(ShiftAllRightAndFillUpperFromUint64x8 [a] x y) => (VPSHRDQ512 [a] x y)
|
||||||
|
(ShiftAllRightSignExtendedInt16x8 ...) => (VPSRAW128 ...)
|
||||||
|
(ShiftAllRightSignExtendedInt16x16 ...) => (VPSRAW256 ...)
|
||||||
|
(ShiftAllRightSignExtendedInt32x4 ...) => (VPSRAD128 ...)
|
||||||
|
(ShiftAllRightSignExtendedInt32x8 ...) => (VPSRAD256 ...)
|
||||||
|
(ShiftAllRightSignExtendedInt64x2 ...) => (VPSRAQ128 ...)
|
||||||
|
(ShiftAllRightSignExtendedInt64x4 ...) => (VPSRAQ256 ...)
|
||||||
|
(ShiftAllRightSignExtendedInt64x8 ...) => (VPSRAQ512 ...)
|
||||||
|
(ShiftLeftInt16x8 ...) => (VPSLLVW128 ...)
|
||||||
|
(ShiftLeftInt16x16 ...) => (VPSLLVW256 ...)
|
||||||
|
(ShiftLeftInt16x32 ...) => (VPSLLVW512 ...)
|
||||||
|
(ShiftLeftInt32x4 ...) => (VPSLLVD128 ...)
|
||||||
|
(ShiftLeftInt32x8 ...) => (VPSLLVD256 ...)
|
||||||
|
(ShiftLeftInt32x16 ...) => (VPSLLVD512 ...)
|
||||||
|
(ShiftLeftInt64x2 ...) => (VPSLLVQ128 ...)
|
||||||
|
(ShiftLeftInt64x4 ...) => (VPSLLVQ256 ...)
|
||||||
|
(ShiftLeftInt64x8 ...) => (VPSLLVQ512 ...)
|
||||||
|
(ShiftLeftUint16x8 ...) => (VPSLLVW128 ...)
|
||||||
|
(ShiftLeftUint16x16 ...) => (VPSLLVW256 ...)
|
||||||
|
(ShiftLeftUint16x32 ...) => (VPSLLVW512 ...)
|
||||||
|
(ShiftLeftUint32x4 ...) => (VPSLLVD128 ...)
|
||||||
|
(ShiftLeftUint32x8 ...) => (VPSLLVD256 ...)
|
||||||
|
(ShiftLeftUint32x16 ...) => (VPSLLVD512 ...)
|
||||||
|
(ShiftLeftUint64x2 ...) => (VPSLLVQ128 ...)
|
||||||
|
(ShiftLeftUint64x4 ...) => (VPSLLVQ256 ...)
|
||||||
|
(ShiftLeftUint64x8 ...) => (VPSLLVQ512 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromInt16x8 ...) => (VPSHLDVW128 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromInt16x16 ...) => (VPSHLDVW256 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromInt16x32 ...) => (VPSHLDVW512 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromInt32x4 ...) => (VPSHLDVD128 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromInt32x8 ...) => (VPSHLDVD256 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromInt32x16 ...) => (VPSHLDVD512 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromInt64x2 ...) => (VPSHLDVQ128 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromInt64x4 ...) => (VPSHLDVQ256 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromInt64x8 ...) => (VPSHLDVQ512 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromUint16x8 ...) => (VPSHLDVW128 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromUint16x16 ...) => (VPSHLDVW256 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromUint16x32 ...) => (VPSHLDVW512 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromUint32x4 ...) => (VPSHLDVD128 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromUint32x8 ...) => (VPSHLDVD256 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromUint32x16 ...) => (VPSHLDVD512 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromUint64x2 ...) => (VPSHLDVQ128 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromUint64x4 ...) => (VPSHLDVQ256 ...)
|
||||||
|
(ShiftLeftAndFillUpperFromUint64x8 ...) => (VPSHLDVQ512 ...)
|
||||||
|
(ShiftRightInt16x8 ...) => (VPSRLVW128 ...)
|
||||||
|
(ShiftRightInt16x16 ...) => (VPSRLVW256 ...)
|
||||||
|
(ShiftRightInt16x32 ...) => (VPSRLVW512 ...)
|
||||||
|
(ShiftRightInt32x4 ...) => (VPSRLVD128 ...)
|
||||||
|
(ShiftRightInt32x8 ...) => (VPSRLVD256 ...)
|
||||||
|
(ShiftRightInt32x16 ...) => (VPSRLVD512 ...)
|
||||||
|
(ShiftRightInt64x2 ...) => (VPSRLVQ128 ...)
|
||||||
|
(ShiftRightInt64x4 ...) => (VPSRLVQ256 ...)
|
||||||
|
(ShiftRightInt64x8 ...) => (VPSRLVQ512 ...)
|
||||||
|
(ShiftRightUint16x8 ...) => (VPSRLVW128 ...)
|
||||||
|
(ShiftRightUint16x16 ...) => (VPSRLVW256 ...)
|
||||||
|
(ShiftRightUint16x32 ...) => (VPSRLVW512 ...)
|
||||||
|
(ShiftRightUint32x4 ...) => (VPSRLVD128 ...)
|
||||||
|
(ShiftRightUint32x8 ...) => (VPSRLVD256 ...)
|
||||||
|
(ShiftRightUint32x16 ...) => (VPSRLVD512 ...)
|
||||||
|
(ShiftRightUint64x2 ...) => (VPSRLVQ128 ...)
|
||||||
|
(ShiftRightUint64x4 ...) => (VPSRLVQ256 ...)
|
||||||
|
(ShiftRightUint64x8 ...) => (VPSRLVQ512 ...)
|
||||||
|
(ShiftRightAndFillUpperFromInt16x8 ...) => (VPSHRDVW128 ...)
|
||||||
|
(ShiftRightAndFillUpperFromInt16x16 ...) => (VPSHRDVW256 ...)
|
||||||
|
(ShiftRightAndFillUpperFromInt16x32 ...) => (VPSHRDVW512 ...)
|
||||||
|
(ShiftRightAndFillUpperFromInt32x4 ...) => (VPSHRDVD128 ...)
|
||||||
|
(ShiftRightAndFillUpperFromInt32x8 ...) => (VPSHRDVD256 ...)
|
||||||
|
(ShiftRightAndFillUpperFromInt32x16 ...) => (VPSHRDVD512 ...)
|
||||||
|
(ShiftRightAndFillUpperFromInt64x2 ...) => (VPSHRDVQ128 ...)
|
||||||
|
(ShiftRightAndFillUpperFromInt64x4 ...) => (VPSHRDVQ256 ...)
|
||||||
|
(ShiftRightAndFillUpperFromInt64x8 ...) => (VPSHRDVQ512 ...)
|
||||||
|
(ShiftRightAndFillUpperFromUint16x8 ...) => (VPSHRDVW128 ...)
|
||||||
|
(ShiftRightAndFillUpperFromUint16x16 ...) => (VPSHRDVW256 ...)
|
||||||
|
(ShiftRightAndFillUpperFromUint16x32 ...) => (VPSHRDVW512 ...)
|
||||||
|
(ShiftRightAndFillUpperFromUint32x4 ...) => (VPSHRDVD128 ...)
|
||||||
|
(ShiftRightAndFillUpperFromUint32x8 ...) => (VPSHRDVD256 ...)
|
||||||
|
(ShiftRightAndFillUpperFromUint32x16 ...) => (VPSHRDVD512 ...)
|
||||||
|
(ShiftRightAndFillUpperFromUint64x2 ...) => (VPSHRDVQ128 ...)
|
||||||
|
(ShiftRightAndFillUpperFromUint64x4 ...) => (VPSHRDVQ256 ...)
|
||||||
|
(ShiftRightAndFillUpperFromUint64x8 ...) => (VPSHRDVQ512 ...)
|
||||||
|
(ShiftRightSignExtendedInt16x8 ...) => (VPSRAVW128 ...)
|
||||||
|
(ShiftRightSignExtendedInt16x16 ...) => (VPSRAVW256 ...)
|
||||||
|
(ShiftRightSignExtendedInt16x32 ...) => (VPSRAVW512 ...)
|
||||||
|
(ShiftRightSignExtendedInt32x4 ...) => (VPSRAVD128 ...)
|
||||||
|
(ShiftRightSignExtendedInt32x8 ...) => (VPSRAVD256 ...)
|
||||||
|
(ShiftRightSignExtendedInt32x16 ...) => (VPSRAVD512 ...)
|
||||||
|
(ShiftRightSignExtendedInt64x2 ...) => (VPSRAVQ128 ...)
|
||||||
|
(ShiftRightSignExtendedInt64x4 ...) => (VPSRAVQ256 ...)
|
||||||
|
(ShiftRightSignExtendedInt64x8 ...) => (VPSRAVQ512 ...)
|
||||||
|
(ShiftRightSignExtendedUint16x8 ...) => (VPSRAVW128 ...)
|
||||||
|
(ShiftRightSignExtendedUint16x16 ...) => (VPSRAVW256 ...)
|
||||||
|
(ShiftRightSignExtendedUint16x32 ...) => (VPSRAVW512 ...)
|
||||||
|
(ShiftRightSignExtendedUint32x4 ...) => (VPSRAVD128 ...)
|
||||||
|
(ShiftRightSignExtendedUint32x8 ...) => (VPSRAVD256 ...)
|
||||||
|
(ShiftRightSignExtendedUint32x16 ...) => (VPSRAVD512 ...)
|
||||||
|
(ShiftRightSignExtendedUint64x2 ...) => (VPSRAVQ128 ...)
|
||||||
|
(ShiftRightSignExtendedUint64x4 ...) => (VPSRAVQ256 ...)
|
||||||
|
(ShiftRightSignExtendedUint64x8 ...) => (VPSRAVQ512 ...)
|
||||||
(SignInt8x16 ...) => (VPSIGNB128 ...)
|
(SignInt8x16 ...) => (VPSIGNB128 ...)
|
||||||
(SignInt8x32 ...) => (VPSIGNB256 ...)
|
(SignInt8x32 ...) => (VPSIGNB256 ...)
|
||||||
(SignInt16x8 ...) => (VPSIGNW128 ...)
|
(SignInt16x8 ...) => (VPSIGNW128 ...)
|
||||||
|
|
|
||||||
|
|
@ -233,6 +233,11 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPOPCNTWMasked256", argLength: 2, reg: fpkfp, asm: "VPOPCNTW", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPOPCNTWMasked256", argLength: 2, reg: fpkfp, asm: "VPOPCNTW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPADDSWMasked256", argLength: 3, reg: fp2kfp, asm: "VPADDSW", commutative: true, typ: "Vec256", resultInArg0: false},
|
{name: "VPADDSWMasked256", argLength: 3, reg: fp2kfp, asm: "VPADDSW", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPSUBSWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPSUBSWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSLLVWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSLLVW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVWMasked256", argLength: 4, reg: fp3kfp, asm: "VPSHLDVW", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSRLVWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRLVW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVWMasked256", argLength: 4, reg: fp3kfp, asm: "VPSHRDVW", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSRAVWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRAVW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPSUBWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPSUBWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPMAXSW256", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false},
|
{name: "VPMAXSW256", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPMINSW256", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false},
|
{name: "VPMINSW256", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||||
|
|
@ -246,6 +251,14 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPHADDSW256", argLength: 2, reg: fp21, asm: "VPHADDSW", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPHADDSW256", argLength: 2, reg: fp21, asm: "VPHADDSW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPHSUBSW256", argLength: 2, reg: fp21, asm: "VPHSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPHSUBSW256", argLength: 2, reg: fp21, asm: "VPHSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPSUBSW256", argLength: 2, reg: fp21, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPSUBSW256", argLength: 2, reg: fp21, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSLLW256", argLength: 2, reg: fp21, asm: "VPSLLW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSRLW256", argLength: 2, reg: fp21, asm: "VPSRLW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSRAW256", argLength: 2, reg: fp21, asm: "VPSRAW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSLLVW256", argLength: 2, reg: fp21, asm: "VPSLLVW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVW256", argLength: 3, reg: fp31, asm: "VPSHLDVW", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSRLVW256", argLength: 2, reg: fp21, asm: "VPSRLVW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVW256", argLength: 3, reg: fp31, asm: "VPSHRDVW", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSRAVW256", argLength: 2, reg: fp21, asm: "VPSRAVW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPSIGNW256", argLength: 2, reg: fp21, asm: "VPSIGNW", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPSIGNW256", argLength: 2, reg: fp21, asm: "VPSIGNW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPSUBW256", argLength: 2, reg: fp21, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPSUBW256", argLength: 2, reg: fp21, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPABSW512", argLength: 1, reg: fp11, asm: "VPABSW", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPABSW512", argLength: 1, reg: fp11, asm: "VPABSW", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
|
@ -260,6 +273,11 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPOPCNTWMasked512", argLength: 2, reg: fpkfp, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPOPCNTWMasked512", argLength: 2, reg: fpkfp, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPADDSWMasked512", argLength: 3, reg: fp2kfp, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPADDSWMasked512", argLength: 3, reg: fp2kfp, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPSUBSWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPSUBSWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSLLVWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSLLVW", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVWMasked512", argLength: 4, reg: fp3kfp, asm: "VPSHLDVW", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSRLVWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRLVW", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVWMasked512", argLength: 4, reg: fp3kfp, asm: "VPSHRDVW", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSRAVWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRAVW", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPSUBWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPSUBWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPMAXSW512", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPMAXSW512", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPMINSW512", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPMINSW512", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
|
|
@ -269,6 +287,11 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPOPCNTW512", argLength: 1, reg: fp11, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPOPCNTW512", argLength: 1, reg: fp11, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPADDSW512", argLength: 2, reg: fp21, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPADDSW512", argLength: 2, reg: fp21, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPSUBSW512", argLength: 2, reg: fp21, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPSUBSW512", argLength: 2, reg: fp21, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSLLVW512", argLength: 2, reg: fp21, asm: "VPSLLVW", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVW512", argLength: 3, reg: fp31, asm: "VPSHLDVW", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSRLVW512", argLength: 2, reg: fp21, asm: "VPSRLVW", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVW512", argLength: 3, reg: fp31, asm: "VPSHRDVW", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSRAVW512", argLength: 2, reg: fp21, asm: "VPSRAVW", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPSUBW512", argLength: 2, reg: fp21, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPSUBW512", argLength: 2, reg: fp21, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPABSW128", argLength: 1, reg: fp11, asm: "VPABSW", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPABSW128", argLength: 1, reg: fp11, asm: "VPABSW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPADDW128", argLength: 2, reg: fp21, asm: "VPADDW", commutative: true, typ: "Vec128", resultInArg0: false},
|
{name: "VPADDW128", argLength: 2, reg: fp21, asm: "VPADDW", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||||
|
|
@ -284,6 +307,11 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPOPCNTWMasked128", argLength: 2, reg: fpkfp, asm: "VPOPCNTW", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPOPCNTWMasked128", argLength: 2, reg: fpkfp, asm: "VPOPCNTW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPADDSWMasked128", argLength: 3, reg: fp2kfp, asm: "VPADDSW", commutative: true, typ: "Vec128", resultInArg0: false},
|
{name: "VPADDSWMasked128", argLength: 3, reg: fp2kfp, asm: "VPADDSW", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPSUBSWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPSUBSWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSLLVWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSLLVW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVWMasked128", argLength: 4, reg: fp3kfp, asm: "VPSHLDVW", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSRLVWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRLVW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVWMasked128", argLength: 4, reg: fp3kfp, asm: "VPSHRDVW", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSRAVWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRAVW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPSUBWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPSUBWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPMAXSW128", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false},
|
{name: "VPMAXSW128", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPMINSW128", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false},
|
{name: "VPMINSW128", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||||
|
|
@ -297,6 +325,14 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPHADDSW128", argLength: 2, reg: fp21, asm: "VPHADDSW", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPHADDSW128", argLength: 2, reg: fp21, asm: "VPHADDSW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPHSUBSW128", argLength: 2, reg: fp21, asm: "VPHSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPHSUBSW128", argLength: 2, reg: fp21, asm: "VPHSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPSUBSW128", argLength: 2, reg: fp21, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPSUBSW128", argLength: 2, reg: fp21, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSLLW128", argLength: 2, reg: fp21, asm: "VPSLLW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSRLW128", argLength: 2, reg: fp21, asm: "VPSRLW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSRAW128", argLength: 2, reg: fp21, asm: "VPSRAW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSLLVW128", argLength: 2, reg: fp21, asm: "VPSLLVW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVW128", argLength: 3, reg: fp31, asm: "VPSHLDVW", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSRLVW128", argLength: 2, reg: fp21, asm: "VPSRLVW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVW128", argLength: 3, reg: fp31, asm: "VPSHRDVW", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSRAVW128", argLength: 2, reg: fp21, asm: "VPSRAVW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPSIGNW128", argLength: 2, reg: fp21, asm: "VPSIGNW", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPSIGNW128", argLength: 2, reg: fp21, asm: "VPSIGNW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPSUBW128", argLength: 2, reg: fp21, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPSUBW128", argLength: 2, reg: fp21, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPABSD512", argLength: 1, reg: fp11, asm: "VPABSD", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPABSD512", argLength: 1, reg: fp11, asm: "VPABSD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
|
@ -313,8 +349,15 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPORDMasked512", argLength: 3, reg: fp2kfp, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPORDMasked512", argLength: 3, reg: fp2kfp, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPDPWSSDMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
|
{name: "VPDPWSSDMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
{name: "VPOPCNTDMasked512", argLength: 2, reg: fpkfp, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPOPCNTDMasked512", argLength: 2, reg: fpkfp, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPROLVDMasked512", argLength: 3, reg: fp2kfp, asm: "VPROLVD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPRORVDMasked512", argLength: 3, reg: fp2kfp, asm: "VPRORVD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPDPWSSDSMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
|
{name: "VPDPWSSDSMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
{name: "VPDPBUSDSMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true},
|
{name: "VPDPBUSDSMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSLLVDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSLLVD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVDMasked512", argLength: 4, reg: fp3kfp, asm: "VPSHLDVD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSRLVDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRLVD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVDMasked512", argLength: 4, reg: fp3kfp, asm: "VPSHRDVD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSRAVDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRAVD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPSUBDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPSUBDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPDPBUSDMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
|
{name: "VPDPBUSDMasked512", argLength: 4, reg: fp3kfp, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
{name: "VPXORDMasked512", argLength: 3, reg: fp2kfp, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPXORDMasked512", argLength: 3, reg: fp2kfp, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
|
|
@ -324,8 +367,15 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPORD512", argLength: 2, reg: fp21, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPORD512", argLength: 2, reg: fp21, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPDPWSSD512", argLength: 3, reg: fp31, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
|
{name: "VPDPWSSD512", argLength: 3, reg: fp31, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
{name: "VPOPCNTD512", argLength: 1, reg: fp11, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPOPCNTD512", argLength: 1, reg: fp11, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPROLVD512", argLength: 2, reg: fp21, asm: "VPROLVD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPRORVD512", argLength: 2, reg: fp21, asm: "VPRORVD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPDPWSSDS512", argLength: 3, reg: fp31, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
|
{name: "VPDPWSSDS512", argLength: 3, reg: fp31, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
{name: "VPDPBUSDS512", argLength: 3, reg: fp31, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true},
|
{name: "VPDPBUSDS512", argLength: 3, reg: fp31, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSLLVD512", argLength: 2, reg: fp21, asm: "VPSLLVD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVD512", argLength: 3, reg: fp31, asm: "VPSHLDVD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSRLVD512", argLength: 2, reg: fp21, asm: "VPSRLVD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVD512", argLength: 3, reg: fp31, asm: "VPSHRDVD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSRAVD512", argLength: 2, reg: fp21, asm: "VPSRAVD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPSUBD512", argLength: 2, reg: fp21, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPSUBD512", argLength: 2, reg: fp21, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPDPBUSD512", argLength: 3, reg: fp31, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
|
{name: "VPDPBUSD512", argLength: 3, reg: fp31, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
{name: "VPXORD512", argLength: 2, reg: fp21, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPXORD512", argLength: 2, reg: fp21, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
|
|
@ -343,8 +393,15 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPORDMasked128", argLength: 3, reg: fp2kfp, asm: "VPORD", commutative: true, typ: "Vec128", resultInArg0: false},
|
{name: "VPORDMasked128", argLength: 3, reg: fp2kfp, asm: "VPORD", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPDPWSSDMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPWSSD", commutative: false, typ: "Vec128", resultInArg0: true},
|
{name: "VPDPWSSDMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPWSSD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
{name: "VPOPCNTDMasked128", argLength: 2, reg: fpkfp, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPOPCNTDMasked128", argLength: 2, reg: fpkfp, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPROLVDMasked128", argLength: 3, reg: fp2kfp, asm: "VPROLVD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPRORVDMasked128", argLength: 3, reg: fp2kfp, asm: "VPRORVD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPDPWSSDSMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true},
|
{name: "VPDPWSSDSMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
{name: "VPDPBUSDSMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
|
{name: "VPDPBUSDSMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSLLVDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSLLVD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVDMasked128", argLength: 4, reg: fp3kfp, asm: "VPSHLDVD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSRLVDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRLVD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVDMasked128", argLength: 4, reg: fp3kfp, asm: "VPSHRDVD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSRAVDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRAVD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPSUBDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPSUBDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPDPBUSDMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
|
{name: "VPDPBUSDMasked128", argLength: 4, reg: fp3kfp, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
{name: "VPXORDMasked128", argLength: 3, reg: fp2kfp, asm: "VPXORD", commutative: true, typ: "Vec128", resultInArg0: false},
|
{name: "VPXORDMasked128", argLength: 3, reg: fp2kfp, asm: "VPXORD", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||||
|
|
@ -356,8 +413,18 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPHADDD128", argLength: 2, reg: fp21, asm: "VPHADDD", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPHADDD128", argLength: 2, reg: fp21, asm: "VPHADDD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPHSUBD128", argLength: 2, reg: fp21, asm: "VPHSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPHSUBD128", argLength: 2, reg: fp21, asm: "VPHSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPOPCNTD128", argLength: 1, reg: fp11, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPOPCNTD128", argLength: 1, reg: fp11, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPROLVD128", argLength: 2, reg: fp21, asm: "VPROLVD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPRORVD128", argLength: 2, reg: fp21, asm: "VPRORVD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPDPWSSDS128", argLength: 3, reg: fp31, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true},
|
{name: "VPDPWSSDS128", argLength: 3, reg: fp31, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
{name: "VPDPBUSDS128", argLength: 3, reg: fp31, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
|
{name: "VPDPBUSDS128", argLength: 3, reg: fp31, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSLLD128", argLength: 2, reg: fp21, asm: "VPSLLD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSRLD128", argLength: 2, reg: fp21, asm: "VPSRLD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSRAD128", argLength: 2, reg: fp21, asm: "VPSRAD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSLLVD128", argLength: 2, reg: fp21, asm: "VPSLLVD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVD128", argLength: 3, reg: fp31, asm: "VPSHLDVD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSRLVD128", argLength: 2, reg: fp21, asm: "VPSRLVD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVD128", argLength: 3, reg: fp31, asm: "VPSHRDVD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSRAVD128", argLength: 2, reg: fp21, asm: "VPSRAVD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPSIGND128", argLength: 2, reg: fp21, asm: "VPSIGND", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPSIGND128", argLength: 2, reg: fp21, asm: "VPSIGND", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPSUBD128", argLength: 2, reg: fp21, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPSUBD128", argLength: 2, reg: fp21, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPDPBUSD128", argLength: 3, reg: fp31, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
|
{name: "VPDPBUSD128", argLength: 3, reg: fp31, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
|
@ -375,8 +442,15 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPORDMasked256", argLength: 3, reg: fp2kfp, asm: "VPORD", commutative: true, typ: "Vec256", resultInArg0: false},
|
{name: "VPORDMasked256", argLength: 3, reg: fp2kfp, asm: "VPORD", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPDPWSSDMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPWSSD", commutative: false, typ: "Vec256", resultInArg0: true},
|
{name: "VPDPWSSDMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPWSSD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
{name: "VPOPCNTDMasked256", argLength: 2, reg: fpkfp, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPOPCNTDMasked256", argLength: 2, reg: fpkfp, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPROLVDMasked256", argLength: 3, reg: fp2kfp, asm: "VPROLVD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPRORVDMasked256", argLength: 3, reg: fp2kfp, asm: "VPRORVD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPDPWSSDSMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
|
{name: "VPDPWSSDSMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
{name: "VPDPBUSDSMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
|
{name: "VPDPBUSDSMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSLLVDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSLLVD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVDMasked256", argLength: 4, reg: fp3kfp, asm: "VPSHLDVD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSRLVDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRLVD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVDMasked256", argLength: 4, reg: fp3kfp, asm: "VPSHRDVD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSRAVDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRAVD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPSUBDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPSUBDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPDPBUSDMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
|
{name: "VPDPBUSDMasked256", argLength: 4, reg: fp3kfp, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
{name: "VPXORDMasked256", argLength: 3, reg: fp2kfp, asm: "VPXORD", commutative: true, typ: "Vec256", resultInArg0: false},
|
{name: "VPXORDMasked256", argLength: 3, reg: fp2kfp, asm: "VPXORD", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||||
|
|
@ -388,8 +462,18 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPHADDD256", argLength: 2, reg: fp21, asm: "VPHADDD", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPHADDD256", argLength: 2, reg: fp21, asm: "VPHADDD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPHSUBD256", argLength: 2, reg: fp21, asm: "VPHSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPHSUBD256", argLength: 2, reg: fp21, asm: "VPHSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPOPCNTD256", argLength: 1, reg: fp11, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPOPCNTD256", argLength: 1, reg: fp11, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPROLVD256", argLength: 2, reg: fp21, asm: "VPROLVD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPRORVD256", argLength: 2, reg: fp21, asm: "VPRORVD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPDPWSSDS256", argLength: 3, reg: fp31, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
|
{name: "VPDPWSSDS256", argLength: 3, reg: fp31, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
{name: "VPDPBUSDS256", argLength: 3, reg: fp31, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
|
{name: "VPDPBUSDS256", argLength: 3, reg: fp31, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSLLD256", argLength: 2, reg: fp21, asm: "VPSLLD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSRLD256", argLength: 2, reg: fp21, asm: "VPSRLD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSRAD256", argLength: 2, reg: fp21, asm: "VPSRAD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSLLVD256", argLength: 2, reg: fp21, asm: "VPSLLVD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVD256", argLength: 3, reg: fp31, asm: "VPSHLDVD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSRLVD256", argLength: 2, reg: fp21, asm: "VPSRLVD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVD256", argLength: 3, reg: fp31, asm: "VPSHRDVD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSRAVD256", argLength: 2, reg: fp21, asm: "VPSRAVD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPSIGND256", argLength: 2, reg: fp21, asm: "VPSIGND", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPSIGND256", argLength: 2, reg: fp21, asm: "VPSIGND", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPSUBD256", argLength: 2, reg: fp21, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPSUBD256", argLength: 2, reg: fp21, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPDPBUSD256", argLength: 3, reg: fp31, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
|
{name: "VPDPBUSD256", argLength: 3, reg: fp31, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
|
@ -406,12 +490,32 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPMULLQMasked128", argLength: 3, reg: fp2kfp, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false},
|
{name: "VPMULLQMasked128", argLength: 3, reg: fp2kfp, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPORQMasked128", argLength: 3, reg: fp2kfp, asm: "VPORQ", commutative: true, typ: "Vec128", resultInArg0: false},
|
{name: "VPORQMasked128", argLength: 3, reg: fp2kfp, asm: "VPORQ", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPOPCNTQMasked128", argLength: 2, reg: fpkfp, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPOPCNTQMasked128", argLength: 2, reg: fpkfp, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPROLVQMasked128", argLength: 3, reg: fp2kfp, asm: "VPROLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPRORVQMasked128", argLength: 3, reg: fp2kfp, asm: "VPRORVQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSLLQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSLLQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSRLQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRLQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSRAQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRAQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSLLVQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSLLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVQMasked128", argLength: 4, reg: fp3kfp, asm: "VPSHLDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSRLVQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVQMasked128", argLength: 4, reg: fp3kfp, asm: "VPSHRDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSRAVQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSRAVQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPSUBQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPSUBQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPXORQMasked128", argLength: 3, reg: fp2kfp, asm: "VPXORQ", commutative: true, typ: "Vec128", resultInArg0: false},
|
{name: "VPXORQMasked128", argLength: 3, reg: fp2kfp, asm: "VPXORQ", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPMAXSQ128", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec128", resultInArg0: false},
|
{name: "VPMAXSQ128", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPMINSQ128", argLength: 2, reg: fp21, asm: "VPMINSQ", commutative: true, typ: "Vec128", resultInArg0: false},
|
{name: "VPMINSQ128", argLength: 2, reg: fp21, asm: "VPMINSQ", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPMULLQ128", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false},
|
{name: "VPMULLQ128", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPOPCNTQ128", argLength: 1, reg: fp11, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPOPCNTQ128", argLength: 1, reg: fp11, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPROLVQ128", argLength: 2, reg: fp21, asm: "VPROLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPRORVQ128", argLength: 2, reg: fp21, asm: "VPRORVQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSLLQ128", argLength: 2, reg: fp21, asm: "VPSLLQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSRLQ128", argLength: 2, reg: fp21, asm: "VPSRLQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSRAQ128", argLength: 2, reg: fp21, asm: "VPSRAQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSLLVQ128", argLength: 2, reg: fp21, asm: "VPSLLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVQ128", argLength: 3, reg: fp31, asm: "VPSHLDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSRLVQ128", argLength: 2, reg: fp21, asm: "VPSRLVQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVQ128", argLength: 3, reg: fp31, asm: "VPSHRDVQ", commutative: false, typ: "Vec128", resultInArg0: true},
|
||||||
|
{name: "VPSRAVQ128", argLength: 2, reg: fp21, asm: "VPSRAVQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPSUBQ128", argLength: 2, reg: fp21, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPSUBQ128", argLength: 2, reg: fp21, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPABSQ256", argLength: 1, reg: fp11, asm: "VPABSQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPABSQ256", argLength: 1, reg: fp11, asm: "VPABSQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPADDQ256", argLength: 2, reg: fp21, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
{name: "VPADDQ256", argLength: 2, reg: fp21, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||||
|
|
@ -427,12 +531,32 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPMULLQMasked256", argLength: 3, reg: fp2kfp, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
{name: "VPMULLQMasked256", argLength: 3, reg: fp2kfp, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPORQMasked256", argLength: 3, reg: fp2kfp, asm: "VPORQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
{name: "VPORQMasked256", argLength: 3, reg: fp2kfp, asm: "VPORQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPOPCNTQMasked256", argLength: 2, reg: fpkfp, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPOPCNTQMasked256", argLength: 2, reg: fpkfp, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPROLVQMasked256", argLength: 3, reg: fp2kfp, asm: "VPROLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPRORVQMasked256", argLength: 3, reg: fp2kfp, asm: "VPRORVQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSLLQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSLLQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSRLQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRLQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSRAQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRAQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSLLVQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSLLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVQMasked256", argLength: 4, reg: fp3kfp, asm: "VPSHLDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSRLVQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVQMasked256", argLength: 4, reg: fp3kfp, asm: "VPSHRDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSRAVQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSRAVQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPSUBQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPSUBQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPXORQMasked256", argLength: 3, reg: fp2kfp, asm: "VPXORQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
{name: "VPXORQMasked256", argLength: 3, reg: fp2kfp, asm: "VPXORQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPMAXSQ256", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
{name: "VPMAXSQ256", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPMINSQ256", argLength: 2, reg: fp21, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
{name: "VPMINSQ256", argLength: 2, reg: fp21, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPMULLQ256", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
{name: "VPMULLQ256", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPOPCNTQ256", argLength: 1, reg: fp11, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPOPCNTQ256", argLength: 1, reg: fp11, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPROLVQ256", argLength: 2, reg: fp21, asm: "VPROLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPRORVQ256", argLength: 2, reg: fp21, asm: "VPRORVQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSLLQ256", argLength: 2, reg: fp21, asm: "VPSLLQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSRLQ256", argLength: 2, reg: fp21, asm: "VPSRLQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSRAQ256", argLength: 2, reg: fp21, asm: "VPSRAQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSLLVQ256", argLength: 2, reg: fp21, asm: "VPSLLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVQ256", argLength: 3, reg: fp31, asm: "VPSHLDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSRLVQ256", argLength: 2, reg: fp21, asm: "VPSRLVQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVQ256", argLength: 3, reg: fp31, asm: "VPSHRDVQ", commutative: false, typ: "Vec256", resultInArg0: true},
|
||||||
|
{name: "VPSRAVQ256", argLength: 2, reg: fp21, asm: "VPSRAVQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPSUBQ256", argLength: 2, reg: fp21, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
{name: "VPSUBQ256", argLength: 2, reg: fp21, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPABSQ512", argLength: 1, reg: fp11, asm: "VPABSQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPABSQ512", argLength: 1, reg: fp11, asm: "VPABSQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPADDQ512", argLength: 2, reg: fp21, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPADDQ512", argLength: 2, reg: fp21, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
|
|
@ -448,6 +572,16 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPMULLQMasked512", argLength: 3, reg: fp2kfp, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPMULLQMasked512", argLength: 3, reg: fp2kfp, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPORQMasked512", argLength: 3, reg: fp2kfp, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPORQMasked512", argLength: 3, reg: fp2kfp, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPOPCNTQMasked512", argLength: 2, reg: fpkfp, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPOPCNTQMasked512", argLength: 2, reg: fpkfp, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPROLVQMasked512", argLength: 3, reg: fp2kfp, asm: "VPROLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPRORVQMasked512", argLength: 3, reg: fp2kfp, asm: "VPRORVQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSLLQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSLLQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSRLQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRLQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSRAQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRAQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSLLVQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSLLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVQMasked512", argLength: 4, reg: fp3kfp, asm: "VPSHLDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSRLVQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVQMasked512", argLength: 4, reg: fp3kfp, asm: "VPSHRDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSRAVQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSRAVQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPSUBQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPSUBQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPXORQMasked512", argLength: 3, reg: fp2kfp, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPXORQMasked512", argLength: 3, reg: fp2kfp, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPMAXSQ512", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPMAXSQ512", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
|
|
@ -456,6 +590,16 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VPMULLQ512", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPMULLQ512", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPORQ512", argLength: 2, reg: fp21, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPORQ512", argLength: 2, reg: fp21, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPOPCNTQ512", argLength: 1, reg: fp11, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPOPCNTQ512", argLength: 1, reg: fp11, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPROLVQ512", argLength: 2, reg: fp21, asm: "VPROLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPRORVQ512", argLength: 2, reg: fp21, asm: "VPRORVQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSLLQ512", argLength: 2, reg: fp21, asm: "VPSLLQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSRLQ512", argLength: 2, reg: fp21, asm: "VPSRLQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSRAQ512", argLength: 2, reg: fp21, asm: "VPSRAQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSLLVQ512", argLength: 2, reg: fp21, asm: "VPSLLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHLDVQ512", argLength: 3, reg: fp31, asm: "VPSHLDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSRLVQ512", argLength: 2, reg: fp21, asm: "VPSRLVQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHRDVQ512", argLength: 3, reg: fp31, asm: "VPSHRDVQ", commutative: false, typ: "Vec512", resultInArg0: true},
|
||||||
|
{name: "VPSRAVQ512", argLength: 2, reg: fp21, asm: "VPSRAVQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPSUBQ512", argLength: 2, reg: fp21, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
{name: "VPSUBQ512", argLength: 2, reg: fp21, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPXORQ512", argLength: 2, reg: fp21, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
{name: "VPXORQ512", argLength: 2, reg: fp21, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPABSB128", argLength: 1, reg: fp11, asm: "VPABSB", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPABSB128", argLength: 1, reg: fp11, asm: "VPABSB", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
|
@ -641,28 +785,88 @@ func simdAMD64Ops(fp11, fp21, fp2k, fpkfp, fp2kfp, fp2kk, fp31, fp3kfp, fpgpfp,
|
||||||
{name: "VCMPPDMasked512", argLength: 3, reg: fp2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VCMPPDMasked512", argLength: 3, reg: fp2kk, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
{name: "VPCMPW256", argLength: 2, reg: fp2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPW256", argLength: 2, reg: fp2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||||
{name: "VPCMPWMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPWMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
|
{name: "VPSHLDWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHRDWMasked256", argLength: 3, reg: fp2kfp, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHLDW256", argLength: 2, reg: fp21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHRDW256", argLength: 2, reg: fp21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPCMPW512", argLength: 2, reg: fp2k, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPW512", argLength: 2, reg: fp2k, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
{name: "VPCMPWMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPWMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
|
{name: "VPSHLDWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHRDWMasked512", argLength: 3, reg: fp2kfp, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHLDW512", argLength: 2, reg: fp21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHRDW512", argLength: 2, reg: fp21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPEXTRW128", argLength: 1, reg: fpgp, asm: "VPEXTRW", aux: "Int8", commutative: false, typ: "int16", resultInArg0: false},
|
{name: "VPEXTRW128", argLength: 1, reg: fpgp, asm: "VPEXTRW", aux: "Int8", commutative: false, typ: "int16", resultInArg0: false},
|
||||||
{name: "VPCMPW128", argLength: 2, reg: fp2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPW128", argLength: 2, reg: fp2k, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||||
{name: "VPCMPWMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPWMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
|
{name: "VPSHLDWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHRDWMasked128", argLength: 3, reg: fp2kfp, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPINSRW128", argLength: 2, reg: fpgpfp, asm: "VPINSRW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPINSRW128", argLength: 2, reg: fpgpfp, asm: "VPINSRW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHLDW128", argLength: 2, reg: fp21, asm: "VPSHLDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHRDW128", argLength: 2, reg: fp21, asm: "VPSHRDW", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPCMPD512", argLength: 2, reg: fp2k, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPD512", argLength: 2, reg: fp2k, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
{name: "VPCMPDMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPDMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
|
{name: "VPROLDMasked512", argLength: 2, reg: fpkfp, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPRORDMasked512", argLength: 2, reg: fpkfp, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHLDDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHRDDMasked512", argLength: 3, reg: fp2kfp, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPROLD512", argLength: 1, reg: fp11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPRORD512", argLength: 1, reg: fp11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHLDD512", argLength: 2, reg: fp21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHRDD512", argLength: 2, reg: fp21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPEXTRD128", argLength: 1, reg: fpgp, asm: "VPEXTRD", aux: "Int8", commutative: false, typ: "int32", resultInArg0: false},
|
{name: "VPEXTRD128", argLength: 1, reg: fpgp, asm: "VPEXTRD", aux: "Int8", commutative: false, typ: "int32", resultInArg0: false},
|
||||||
{name: "VPCMPD128", argLength: 2, reg: fp2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPD128", argLength: 2, reg: fp2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||||
{name: "VPCMPDMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPDMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
|
{name: "VPROLDMasked128", argLength: 2, reg: fpkfp, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPRORDMasked128", argLength: 2, reg: fpkfp, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHLDDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHRDDMasked128", argLength: 3, reg: fp2kfp, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPROLD128", argLength: 1, reg: fp11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPRORD128", argLength: 1, reg: fp11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPINSRD128", argLength: 2, reg: fpgpfp, asm: "VPINSRD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPINSRD128", argLength: 2, reg: fpgpfp, asm: "VPINSRD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHLDD128", argLength: 2, reg: fp21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHRDD128", argLength: 2, reg: fp21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPCMPD256", argLength: 2, reg: fp2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPD256", argLength: 2, reg: fp2k, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||||
{name: "VPCMPDMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPDMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
|
{name: "VPROLDMasked256", argLength: 2, reg: fpkfp, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPRORDMasked256", argLength: 2, reg: fpkfp, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHLDDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHRDDMasked256", argLength: 3, reg: fp2kfp, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPROLD256", argLength: 1, reg: fp11, asm: "VPROLD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPRORD256", argLength: 1, reg: fp11, asm: "VPRORD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHLDD256", argLength: 2, reg: fp21, asm: "VPSHLDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHRDD256", argLength: 2, reg: fp21, asm: "VPSHRDD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPEXTRQ128", argLength: 1, reg: fpgp, asm: "VPEXTRQ", aux: "Int8", commutative: false, typ: "int64", resultInArg0: false},
|
{name: "VPEXTRQ128", argLength: 1, reg: fpgp, asm: "VPEXTRQ", aux: "Int8", commutative: false, typ: "int64", resultInArg0: false},
|
||||||
{name: "VPCMPQ128", argLength: 2, reg: fp2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPQ128", argLength: 2, reg: fp2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||||
{name: "VPCMPQMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPQMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
|
{name: "VPROLQMasked128", argLength: 2, reg: fpkfp, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPRORQMasked128", argLength: 2, reg: fpkfp, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHLDQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHRDQMasked128", argLength: 3, reg: fp2kfp, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPROLQ128", argLength: 1, reg: fp11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPRORQ128", argLength: 1, reg: fp11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPINSRQ128", argLength: 2, reg: fpgpfp, asm: "VPINSRQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
{name: "VPINSRQ128", argLength: 2, reg: fpgpfp, asm: "VPINSRQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHLDQ128", argLength: 2, reg: fp21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
|
{name: "VPSHRDQ128", argLength: 2, reg: fp21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false},
|
||||||
{name: "VPCMPQ256", argLength: 2, reg: fp2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPQ256", argLength: 2, reg: fp2k, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||||
{name: "VPCMPQMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPQMasked256", argLength: 3, reg: fp2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
|
{name: "VPROLQMasked256", argLength: 2, reg: fpkfp, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPRORQMasked256", argLength: 2, reg: fpkfp, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHLDQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHRDQMasked256", argLength: 3, reg: fp2kfp, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPROLQ256", argLength: 1, reg: fp11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPRORQ256", argLength: 1, reg: fp11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHLDQ256", argLength: 2, reg: fp21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
|
{name: "VPSHRDQ256", argLength: 2, reg: fp21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false},
|
||||||
{name: "VPCMPQ512", argLength: 2, reg: fp2k, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPQ512", argLength: 2, reg: fp2k, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
{name: "VPCMPQMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPQMasked512", argLength: 3, reg: fp2kk, asm: "VPCMPQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
|
{name: "VPROLQMasked512", argLength: 2, reg: fpkfp, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPRORQMasked512", argLength: 2, reg: fpkfp, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHLDQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHRDQMasked512", argLength: 3, reg: fp2kfp, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPROLQ512", argLength: 1, reg: fp11, asm: "VPROLQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPRORQ512", argLength: 1, reg: fp11, asm: "VPRORQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHLDQ512", argLength: 2, reg: fp21, asm: "VPSHLDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
|
{name: "VPSHRDQ512", argLength: 2, reg: fp21, asm: "VPSHRDQ", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false},
|
||||||
{name: "VPEXTRB128", argLength: 1, reg: fpgp, asm: "VPEXTRB", aux: "Int8", commutative: false, typ: "int8", resultInArg0: false},
|
{name: "VPEXTRB128", argLength: 1, reg: fpgp, asm: "VPEXTRB", aux: "Int8", commutative: false, typ: "int8", resultInArg0: false},
|
||||||
{name: "VPCMPB128", argLength: 2, reg: fp2k, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPB128", argLength: 2, reg: fp2k, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false},
|
||||||
{name: "VPCMPBMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
{name: "VPCMPBMasked128", argLength: 3, reg: fp2kk, asm: "VPCMPB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false},
|
||||||
|
|
|
||||||
|
|
@ -345,6 +345,11 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedPopCountInt16x16", argLength: 2, commutative: false},
|
{name: "MaskedPopCountInt16x16", argLength: 2, commutative: false},
|
||||||
{name: "MaskedSaturatedAddInt16x16", argLength: 3, commutative: true},
|
{name: "MaskedSaturatedAddInt16x16", argLength: 3, commutative: true},
|
||||||
{name: "MaskedSaturatedSubInt16x16", argLength: 3, commutative: false},
|
{name: "MaskedSaturatedSubInt16x16", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftInt16x16", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromInt16x16", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightInt16x16", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromInt16x16", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedInt16x16", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubInt16x16", argLength: 3, commutative: false},
|
{name: "MaskedSubInt16x16", argLength: 3, commutative: false},
|
||||||
{name: "MaxInt16x16", argLength: 2, commutative: true},
|
{name: "MaxInt16x16", argLength: 2, commutative: true},
|
||||||
{name: "MinInt16x16", argLength: 2, commutative: true},
|
{name: "MinInt16x16", argLength: 2, commutative: true},
|
||||||
|
|
@ -360,6 +365,14 @@ func simdGenericOps() []opData {
|
||||||
{name: "SaturatedPairwiseAddInt16x16", argLength: 2, commutative: false},
|
{name: "SaturatedPairwiseAddInt16x16", argLength: 2, commutative: false},
|
||||||
{name: "SaturatedPairwiseSubInt16x16", argLength: 2, commutative: false},
|
{name: "SaturatedPairwiseSubInt16x16", argLength: 2, commutative: false},
|
||||||
{name: "SaturatedSubInt16x16", argLength: 2, commutative: false},
|
{name: "SaturatedSubInt16x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllLeftInt16x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightInt16x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightSignExtendedInt16x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftInt16x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromInt16x16", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightInt16x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromInt16x16", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedInt16x16", argLength: 2, commutative: false},
|
||||||
{name: "SignInt16x16", argLength: 2, commutative: false},
|
{name: "SignInt16x16", argLength: 2, commutative: false},
|
||||||
{name: "SubInt16x16", argLength: 2, commutative: false},
|
{name: "SubInt16x16", argLength: 2, commutative: false},
|
||||||
{name: "XorInt16x16", argLength: 2, commutative: true},
|
{name: "XorInt16x16", argLength: 2, commutative: true},
|
||||||
|
|
@ -386,6 +399,11 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedPopCountInt16x32", argLength: 2, commutative: false},
|
{name: "MaskedPopCountInt16x32", argLength: 2, commutative: false},
|
||||||
{name: "MaskedSaturatedAddInt16x32", argLength: 3, commutative: true},
|
{name: "MaskedSaturatedAddInt16x32", argLength: 3, commutative: true},
|
||||||
{name: "MaskedSaturatedSubInt16x32", argLength: 3, commutative: false},
|
{name: "MaskedSaturatedSubInt16x32", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftInt16x32", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromInt16x32", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightInt16x32", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromInt16x32", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedInt16x32", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubInt16x32", argLength: 3, commutative: false},
|
{name: "MaskedSubInt16x32", argLength: 3, commutative: false},
|
||||||
{name: "MaxInt16x32", argLength: 2, commutative: true},
|
{name: "MaxInt16x32", argLength: 2, commutative: true},
|
||||||
{name: "MinInt16x32", argLength: 2, commutative: true},
|
{name: "MinInt16x32", argLength: 2, commutative: true},
|
||||||
|
|
@ -396,6 +414,11 @@ func simdGenericOps() []opData {
|
||||||
{name: "PopCountInt16x32", argLength: 1, commutative: false},
|
{name: "PopCountInt16x32", argLength: 1, commutative: false},
|
||||||
{name: "SaturatedAddInt16x32", argLength: 2, commutative: true},
|
{name: "SaturatedAddInt16x32", argLength: 2, commutative: true},
|
||||||
{name: "SaturatedSubInt16x32", argLength: 2, commutative: false},
|
{name: "SaturatedSubInt16x32", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftInt16x32", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromInt16x32", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightInt16x32", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromInt16x32", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedInt16x32", argLength: 2, commutative: false},
|
||||||
{name: "SubInt16x32", argLength: 2, commutative: false},
|
{name: "SubInt16x32", argLength: 2, commutative: false},
|
||||||
{name: "AbsoluteInt16x8", argLength: 1, commutative: false},
|
{name: "AbsoluteInt16x8", argLength: 1, commutative: false},
|
||||||
{name: "AddInt16x8", argLength: 2, commutative: true},
|
{name: "AddInt16x8", argLength: 2, commutative: true},
|
||||||
|
|
@ -422,6 +445,11 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedPopCountInt16x8", argLength: 2, commutative: false},
|
{name: "MaskedPopCountInt16x8", argLength: 2, commutative: false},
|
||||||
{name: "MaskedSaturatedAddInt16x8", argLength: 3, commutative: true},
|
{name: "MaskedSaturatedAddInt16x8", argLength: 3, commutative: true},
|
||||||
{name: "MaskedSaturatedSubInt16x8", argLength: 3, commutative: false},
|
{name: "MaskedSaturatedSubInt16x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftInt16x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromInt16x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightInt16x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromInt16x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedInt16x8", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubInt16x8", argLength: 3, commutative: false},
|
{name: "MaskedSubInt16x8", argLength: 3, commutative: false},
|
||||||
{name: "MaxInt16x8", argLength: 2, commutative: true},
|
{name: "MaxInt16x8", argLength: 2, commutative: true},
|
||||||
{name: "MinInt16x8", argLength: 2, commutative: true},
|
{name: "MinInt16x8", argLength: 2, commutative: true},
|
||||||
|
|
@ -437,6 +465,14 @@ func simdGenericOps() []opData {
|
||||||
{name: "SaturatedPairwiseAddInt16x8", argLength: 2, commutative: false},
|
{name: "SaturatedPairwiseAddInt16x8", argLength: 2, commutative: false},
|
||||||
{name: "SaturatedPairwiseSubInt16x8", argLength: 2, commutative: false},
|
{name: "SaturatedPairwiseSubInt16x8", argLength: 2, commutative: false},
|
||||||
{name: "SaturatedSubInt16x8", argLength: 2, commutative: false},
|
{name: "SaturatedSubInt16x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllLeftInt16x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightInt16x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightSignExtendedInt16x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftInt16x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromInt16x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightInt16x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromInt16x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedInt16x8", argLength: 2, commutative: false},
|
||||||
{name: "SignInt16x8", argLength: 2, commutative: false},
|
{name: "SignInt16x8", argLength: 2, commutative: false},
|
||||||
{name: "SubInt16x8", argLength: 2, commutative: false},
|
{name: "SubInt16x8", argLength: 2, commutative: false},
|
||||||
{name: "XorInt16x8", argLength: 2, commutative: true},
|
{name: "XorInt16x8", argLength: 2, commutative: true},
|
||||||
|
|
@ -465,8 +501,15 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedOrInt32x16", argLength: 3, commutative: true},
|
{name: "MaskedOrInt32x16", argLength: 3, commutative: true},
|
||||||
{name: "MaskedPairDotProdAccumulateInt32x16", argLength: 4, commutative: false},
|
{name: "MaskedPairDotProdAccumulateInt32x16", argLength: 4, commutative: false},
|
||||||
{name: "MaskedPopCountInt32x16", argLength: 2, commutative: false},
|
{name: "MaskedPopCountInt32x16", argLength: 2, commutative: false},
|
||||||
|
{name: "MaskedRotateLeftInt32x16", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedRotateRightInt32x16", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSaturatedPairDotProdAccumulateInt32x16", argLength: 4, commutative: false},
|
{name: "MaskedSaturatedPairDotProdAccumulateInt32x16", argLength: 4, commutative: false},
|
||||||
{name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 4, commutative: false},
|
{name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftInt32x16", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromInt32x16", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightInt32x16", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromInt32x16", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedInt32x16", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubInt32x16", argLength: 3, commutative: false},
|
{name: "MaskedSubInt32x16", argLength: 3, commutative: false},
|
||||||
{name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 4, commutative: false},
|
{name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 4, commutative: false},
|
||||||
{name: "MaskedXorInt32x16", argLength: 3, commutative: true},
|
{name: "MaskedXorInt32x16", argLength: 3, commutative: true},
|
||||||
|
|
@ -477,8 +520,15 @@ func simdGenericOps() []opData {
|
||||||
{name: "OrInt32x16", argLength: 2, commutative: true},
|
{name: "OrInt32x16", argLength: 2, commutative: true},
|
||||||
{name: "PairDotProdAccumulateInt32x16", argLength: 3, commutative: false},
|
{name: "PairDotProdAccumulateInt32x16", argLength: 3, commutative: false},
|
||||||
{name: "PopCountInt32x16", argLength: 1, commutative: false},
|
{name: "PopCountInt32x16", argLength: 1, commutative: false},
|
||||||
|
{name: "RotateLeftInt32x16", argLength: 2, commutative: false},
|
||||||
|
{name: "RotateRightInt32x16", argLength: 2, commutative: false},
|
||||||
{name: "SaturatedPairDotProdAccumulateInt32x16", argLength: 3, commutative: false},
|
{name: "SaturatedPairDotProdAccumulateInt32x16", argLength: 3, commutative: false},
|
||||||
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false},
|
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftLeftInt32x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromInt32x16", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightInt32x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromInt32x16", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedInt32x16", argLength: 2, commutative: false},
|
||||||
{name: "SubInt32x16", argLength: 2, commutative: false},
|
{name: "SubInt32x16", argLength: 2, commutative: false},
|
||||||
{name: "UnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false},
|
{name: "UnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false},
|
||||||
{name: "XorInt32x16", argLength: 2, commutative: true},
|
{name: "XorInt32x16", argLength: 2, commutative: true},
|
||||||
|
|
@ -507,8 +557,15 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedOrInt32x4", argLength: 3, commutative: true},
|
{name: "MaskedOrInt32x4", argLength: 3, commutative: true},
|
||||||
{name: "MaskedPairDotProdAccumulateInt32x4", argLength: 4, commutative: false},
|
{name: "MaskedPairDotProdAccumulateInt32x4", argLength: 4, commutative: false},
|
||||||
{name: "MaskedPopCountInt32x4", argLength: 2, commutative: false},
|
{name: "MaskedPopCountInt32x4", argLength: 2, commutative: false},
|
||||||
|
{name: "MaskedRotateLeftInt32x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedRotateRightInt32x4", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSaturatedPairDotProdAccumulateInt32x4", argLength: 4, commutative: false},
|
{name: "MaskedSaturatedPairDotProdAccumulateInt32x4", argLength: 4, commutative: false},
|
||||||
{name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 4, commutative: false},
|
{name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftInt32x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromInt32x4", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightInt32x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromInt32x4", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedInt32x4", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubInt32x4", argLength: 3, commutative: false},
|
{name: "MaskedSubInt32x4", argLength: 3, commutative: false},
|
||||||
{name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 4, commutative: false},
|
{name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 4, commutative: false},
|
||||||
{name: "MaskedXorInt32x4", argLength: 3, commutative: true},
|
{name: "MaskedXorInt32x4", argLength: 3, commutative: true},
|
||||||
|
|
@ -522,8 +579,18 @@ func simdGenericOps() []opData {
|
||||||
{name: "PairwiseAddInt32x4", argLength: 2, commutative: false},
|
{name: "PairwiseAddInt32x4", argLength: 2, commutative: false},
|
||||||
{name: "PairwiseSubInt32x4", argLength: 2, commutative: false},
|
{name: "PairwiseSubInt32x4", argLength: 2, commutative: false},
|
||||||
{name: "PopCountInt32x4", argLength: 1, commutative: false},
|
{name: "PopCountInt32x4", argLength: 1, commutative: false},
|
||||||
|
{name: "RotateLeftInt32x4", argLength: 2, commutative: false},
|
||||||
|
{name: "RotateRightInt32x4", argLength: 2, commutative: false},
|
||||||
{name: "SaturatedPairDotProdAccumulateInt32x4", argLength: 3, commutative: false},
|
{name: "SaturatedPairDotProdAccumulateInt32x4", argLength: 3, commutative: false},
|
||||||
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false},
|
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftAllLeftInt32x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightInt32x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightSignExtendedInt32x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftInt32x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromInt32x4", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightInt32x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromInt32x4", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedInt32x4", argLength: 2, commutative: false},
|
||||||
{name: "SignInt32x4", argLength: 2, commutative: false},
|
{name: "SignInt32x4", argLength: 2, commutative: false},
|
||||||
{name: "SubInt32x4", argLength: 2, commutative: false},
|
{name: "SubInt32x4", argLength: 2, commutative: false},
|
||||||
{name: "UnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false},
|
{name: "UnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false},
|
||||||
|
|
@ -553,8 +620,15 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedOrInt32x8", argLength: 3, commutative: true},
|
{name: "MaskedOrInt32x8", argLength: 3, commutative: true},
|
||||||
{name: "MaskedPairDotProdAccumulateInt32x8", argLength: 4, commutative: false},
|
{name: "MaskedPairDotProdAccumulateInt32x8", argLength: 4, commutative: false},
|
||||||
{name: "MaskedPopCountInt32x8", argLength: 2, commutative: false},
|
{name: "MaskedPopCountInt32x8", argLength: 2, commutative: false},
|
||||||
|
{name: "MaskedRotateLeftInt32x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedRotateRightInt32x8", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSaturatedPairDotProdAccumulateInt32x8", argLength: 4, commutative: false},
|
{name: "MaskedSaturatedPairDotProdAccumulateInt32x8", argLength: 4, commutative: false},
|
||||||
{name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 4, commutative: false},
|
{name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftInt32x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromInt32x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightInt32x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromInt32x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedInt32x8", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubInt32x8", argLength: 3, commutative: false},
|
{name: "MaskedSubInt32x8", argLength: 3, commutative: false},
|
||||||
{name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 4, commutative: false},
|
{name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 4, commutative: false},
|
||||||
{name: "MaskedXorInt32x8", argLength: 3, commutative: true},
|
{name: "MaskedXorInt32x8", argLength: 3, commutative: true},
|
||||||
|
|
@ -568,8 +642,18 @@ func simdGenericOps() []opData {
|
||||||
{name: "PairwiseAddInt32x8", argLength: 2, commutative: false},
|
{name: "PairwiseAddInt32x8", argLength: 2, commutative: false},
|
||||||
{name: "PairwiseSubInt32x8", argLength: 2, commutative: false},
|
{name: "PairwiseSubInt32x8", argLength: 2, commutative: false},
|
||||||
{name: "PopCountInt32x8", argLength: 1, commutative: false},
|
{name: "PopCountInt32x8", argLength: 1, commutative: false},
|
||||||
|
{name: "RotateLeftInt32x8", argLength: 2, commutative: false},
|
||||||
|
{name: "RotateRightInt32x8", argLength: 2, commutative: false},
|
||||||
{name: "SaturatedPairDotProdAccumulateInt32x8", argLength: 3, commutative: false},
|
{name: "SaturatedPairDotProdAccumulateInt32x8", argLength: 3, commutative: false},
|
||||||
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 3, commutative: false},
|
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftAllLeftInt32x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightInt32x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightSignExtendedInt32x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftInt32x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromInt32x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightInt32x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromInt32x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedInt32x8", argLength: 2, commutative: false},
|
||||||
{name: "SignInt32x8", argLength: 2, commutative: false},
|
{name: "SignInt32x8", argLength: 2, commutative: false},
|
||||||
{name: "SubInt32x8", argLength: 2, commutative: false},
|
{name: "SubInt32x8", argLength: 2, commutative: false},
|
||||||
{name: "UnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 3, commutative: false},
|
{name: "UnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 3, commutative: false},
|
||||||
|
|
@ -599,6 +683,16 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedNotEqualInt64x2", argLength: 3, commutative: true},
|
{name: "MaskedNotEqualInt64x2", argLength: 3, commutative: true},
|
||||||
{name: "MaskedOrInt64x2", argLength: 3, commutative: true},
|
{name: "MaskedOrInt64x2", argLength: 3, commutative: true},
|
||||||
{name: "MaskedPopCountInt64x2", argLength: 2, commutative: false},
|
{name: "MaskedPopCountInt64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "MaskedRotateLeftInt64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedRotateRightInt64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllLeftInt64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllRightInt64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllRightSignExtendedInt64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftInt64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromInt64x2", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightInt64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromInt64x2", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedInt64x2", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubInt64x2", argLength: 3, commutative: false},
|
{name: "MaskedSubInt64x2", argLength: 3, commutative: false},
|
||||||
{name: "MaskedXorInt64x2", argLength: 3, commutative: true},
|
{name: "MaskedXorInt64x2", argLength: 3, commutative: true},
|
||||||
{name: "MaxInt64x2", argLength: 2, commutative: true},
|
{name: "MaxInt64x2", argLength: 2, commutative: true},
|
||||||
|
|
@ -608,6 +702,16 @@ func simdGenericOps() []opData {
|
||||||
{name: "NotEqualInt64x2", argLength: 2, commutative: true},
|
{name: "NotEqualInt64x2", argLength: 2, commutative: true},
|
||||||
{name: "OrInt64x2", argLength: 2, commutative: true},
|
{name: "OrInt64x2", argLength: 2, commutative: true},
|
||||||
{name: "PopCountInt64x2", argLength: 1, commutative: false},
|
{name: "PopCountInt64x2", argLength: 1, commutative: false},
|
||||||
|
{name: "RotateLeftInt64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "RotateRightInt64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllLeftInt64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightInt64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightSignExtendedInt64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftInt64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromInt64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightInt64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromInt64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedInt64x2", argLength: 2, commutative: false},
|
||||||
{name: "SubInt64x2", argLength: 2, commutative: false},
|
{name: "SubInt64x2", argLength: 2, commutative: false},
|
||||||
{name: "XorInt64x2", argLength: 2, commutative: true},
|
{name: "XorInt64x2", argLength: 2, commutative: true},
|
||||||
{name: "AbsoluteInt64x4", argLength: 1, commutative: false},
|
{name: "AbsoluteInt64x4", argLength: 1, commutative: false},
|
||||||
|
|
@ -635,6 +739,16 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedNotEqualInt64x4", argLength: 3, commutative: true},
|
{name: "MaskedNotEqualInt64x4", argLength: 3, commutative: true},
|
||||||
{name: "MaskedOrInt64x4", argLength: 3, commutative: true},
|
{name: "MaskedOrInt64x4", argLength: 3, commutative: true},
|
||||||
{name: "MaskedPopCountInt64x4", argLength: 2, commutative: false},
|
{name: "MaskedPopCountInt64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "MaskedRotateLeftInt64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedRotateRightInt64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllLeftInt64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllRightInt64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllRightSignExtendedInt64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftInt64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromInt64x4", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightInt64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromInt64x4", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedInt64x4", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubInt64x4", argLength: 3, commutative: false},
|
{name: "MaskedSubInt64x4", argLength: 3, commutative: false},
|
||||||
{name: "MaskedXorInt64x4", argLength: 3, commutative: true},
|
{name: "MaskedXorInt64x4", argLength: 3, commutative: true},
|
||||||
{name: "MaxInt64x4", argLength: 2, commutative: true},
|
{name: "MaxInt64x4", argLength: 2, commutative: true},
|
||||||
|
|
@ -644,6 +758,16 @@ func simdGenericOps() []opData {
|
||||||
{name: "NotEqualInt64x4", argLength: 2, commutative: true},
|
{name: "NotEqualInt64x4", argLength: 2, commutative: true},
|
||||||
{name: "OrInt64x4", argLength: 2, commutative: true},
|
{name: "OrInt64x4", argLength: 2, commutative: true},
|
||||||
{name: "PopCountInt64x4", argLength: 1, commutative: false},
|
{name: "PopCountInt64x4", argLength: 1, commutative: false},
|
||||||
|
{name: "RotateLeftInt64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "RotateRightInt64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllLeftInt64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightInt64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightSignExtendedInt64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftInt64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromInt64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightInt64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromInt64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedInt64x4", argLength: 2, commutative: false},
|
||||||
{name: "SubInt64x4", argLength: 2, commutative: false},
|
{name: "SubInt64x4", argLength: 2, commutative: false},
|
||||||
{name: "XorInt64x4", argLength: 2, commutative: true},
|
{name: "XorInt64x4", argLength: 2, commutative: true},
|
||||||
{name: "AbsoluteInt64x8", argLength: 1, commutative: false},
|
{name: "AbsoluteInt64x8", argLength: 1, commutative: false},
|
||||||
|
|
@ -671,6 +795,16 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedNotEqualInt64x8", argLength: 3, commutative: true},
|
{name: "MaskedNotEqualInt64x8", argLength: 3, commutative: true},
|
||||||
{name: "MaskedOrInt64x8", argLength: 3, commutative: true},
|
{name: "MaskedOrInt64x8", argLength: 3, commutative: true},
|
||||||
{name: "MaskedPopCountInt64x8", argLength: 2, commutative: false},
|
{name: "MaskedPopCountInt64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "MaskedRotateLeftInt64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedRotateRightInt64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllLeftInt64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllRightInt64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllRightSignExtendedInt64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftInt64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromInt64x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightInt64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromInt64x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedInt64x8", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubInt64x8", argLength: 3, commutative: false},
|
{name: "MaskedSubInt64x8", argLength: 3, commutative: false},
|
||||||
{name: "MaskedXorInt64x8", argLength: 3, commutative: true},
|
{name: "MaskedXorInt64x8", argLength: 3, commutative: true},
|
||||||
{name: "MaxInt64x8", argLength: 2, commutative: true},
|
{name: "MaxInt64x8", argLength: 2, commutative: true},
|
||||||
|
|
@ -680,6 +814,16 @@ func simdGenericOps() []opData {
|
||||||
{name: "NotEqualInt64x8", argLength: 2, commutative: true},
|
{name: "NotEqualInt64x8", argLength: 2, commutative: true},
|
||||||
{name: "OrInt64x8", argLength: 2, commutative: true},
|
{name: "OrInt64x8", argLength: 2, commutative: true},
|
||||||
{name: "PopCountInt64x8", argLength: 1, commutative: false},
|
{name: "PopCountInt64x8", argLength: 1, commutative: false},
|
||||||
|
{name: "RotateLeftInt64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "RotateRightInt64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllLeftInt64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightInt64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightSignExtendedInt64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftInt64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromInt64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightInt64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromInt64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedInt64x8", argLength: 2, commutative: false},
|
||||||
{name: "SubInt64x8", argLength: 2, commutative: false},
|
{name: "SubInt64x8", argLength: 2, commutative: false},
|
||||||
{name: "XorInt64x8", argLength: 2, commutative: true},
|
{name: "XorInt64x8", argLength: 2, commutative: true},
|
||||||
{name: "AbsoluteInt8x16", argLength: 1, commutative: false},
|
{name: "AbsoluteInt8x16", argLength: 1, commutative: false},
|
||||||
|
|
@ -799,6 +943,11 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedPopCountUint16x16", argLength: 2, commutative: false},
|
{name: "MaskedPopCountUint16x16", argLength: 2, commutative: false},
|
||||||
{name: "MaskedSaturatedAddUint16x16", argLength: 3, commutative: true},
|
{name: "MaskedSaturatedAddUint16x16", argLength: 3, commutative: true},
|
||||||
{name: "MaskedSaturatedSubUint16x16", argLength: 3, commutative: false},
|
{name: "MaskedSaturatedSubUint16x16", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftUint16x16", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromUint16x16", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightUint16x16", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromUint16x16", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedUint16x16", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubUint16x16", argLength: 3, commutative: false},
|
{name: "MaskedSubUint16x16", argLength: 3, commutative: false},
|
||||||
{name: "MaxUint16x16", argLength: 2, commutative: true},
|
{name: "MaxUint16x16", argLength: 2, commutative: true},
|
||||||
{name: "MinUint16x16", argLength: 2, commutative: true},
|
{name: "MinUint16x16", argLength: 2, commutative: true},
|
||||||
|
|
@ -810,6 +959,13 @@ func simdGenericOps() []opData {
|
||||||
{name: "PopCountUint16x16", argLength: 1, commutative: false},
|
{name: "PopCountUint16x16", argLength: 1, commutative: false},
|
||||||
{name: "SaturatedAddUint16x16", argLength: 2, commutative: true},
|
{name: "SaturatedAddUint16x16", argLength: 2, commutative: true},
|
||||||
{name: "SaturatedSubUint16x16", argLength: 2, commutative: false},
|
{name: "SaturatedSubUint16x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllLeftUint16x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightUint16x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftUint16x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromUint16x16", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightUint16x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromUint16x16", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedUint16x16", argLength: 2, commutative: false},
|
||||||
{name: "SubUint16x16", argLength: 2, commutative: false},
|
{name: "SubUint16x16", argLength: 2, commutative: false},
|
||||||
{name: "XorUint16x16", argLength: 2, commutative: true},
|
{name: "XorUint16x16", argLength: 2, commutative: true},
|
||||||
{name: "AddUint16x32", argLength: 2, commutative: true},
|
{name: "AddUint16x32", argLength: 2, commutative: true},
|
||||||
|
|
@ -833,6 +989,11 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedPopCountUint16x32", argLength: 2, commutative: false},
|
{name: "MaskedPopCountUint16x32", argLength: 2, commutative: false},
|
||||||
{name: "MaskedSaturatedAddUint16x32", argLength: 3, commutative: true},
|
{name: "MaskedSaturatedAddUint16x32", argLength: 3, commutative: true},
|
||||||
{name: "MaskedSaturatedSubUint16x32", argLength: 3, commutative: false},
|
{name: "MaskedSaturatedSubUint16x32", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftUint16x32", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromUint16x32", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightUint16x32", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromUint16x32", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedUint16x32", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubUint16x32", argLength: 3, commutative: false},
|
{name: "MaskedSubUint16x32", argLength: 3, commutative: false},
|
||||||
{name: "MaxUint16x32", argLength: 2, commutative: true},
|
{name: "MaxUint16x32", argLength: 2, commutative: true},
|
||||||
{name: "MinUint16x32", argLength: 2, commutative: true},
|
{name: "MinUint16x32", argLength: 2, commutative: true},
|
||||||
|
|
@ -841,6 +1002,11 @@ func simdGenericOps() []opData {
|
||||||
{name: "PopCountUint16x32", argLength: 1, commutative: false},
|
{name: "PopCountUint16x32", argLength: 1, commutative: false},
|
||||||
{name: "SaturatedAddUint16x32", argLength: 2, commutative: true},
|
{name: "SaturatedAddUint16x32", argLength: 2, commutative: true},
|
||||||
{name: "SaturatedSubUint16x32", argLength: 2, commutative: false},
|
{name: "SaturatedSubUint16x32", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftUint16x32", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromUint16x32", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightUint16x32", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromUint16x32", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedUint16x32", argLength: 2, commutative: false},
|
||||||
{name: "SubUint16x32", argLength: 2, commutative: false},
|
{name: "SubUint16x32", argLength: 2, commutative: false},
|
||||||
{name: "AddUint16x8", argLength: 2, commutative: true},
|
{name: "AddUint16x8", argLength: 2, commutative: true},
|
||||||
{name: "AndUint16x8", argLength: 2, commutative: true},
|
{name: "AndUint16x8", argLength: 2, commutative: true},
|
||||||
|
|
@ -865,6 +1031,11 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedPopCountUint16x8", argLength: 2, commutative: false},
|
{name: "MaskedPopCountUint16x8", argLength: 2, commutative: false},
|
||||||
{name: "MaskedSaturatedAddUint16x8", argLength: 3, commutative: true},
|
{name: "MaskedSaturatedAddUint16x8", argLength: 3, commutative: true},
|
||||||
{name: "MaskedSaturatedSubUint16x8", argLength: 3, commutative: false},
|
{name: "MaskedSaturatedSubUint16x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftUint16x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromUint16x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightUint16x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromUint16x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedUint16x8", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubUint16x8", argLength: 3, commutative: false},
|
{name: "MaskedSubUint16x8", argLength: 3, commutative: false},
|
||||||
{name: "MaxUint16x8", argLength: 2, commutative: true},
|
{name: "MaxUint16x8", argLength: 2, commutative: true},
|
||||||
{name: "MinUint16x8", argLength: 2, commutative: true},
|
{name: "MinUint16x8", argLength: 2, commutative: true},
|
||||||
|
|
@ -876,6 +1047,13 @@ func simdGenericOps() []opData {
|
||||||
{name: "PopCountUint16x8", argLength: 1, commutative: false},
|
{name: "PopCountUint16x8", argLength: 1, commutative: false},
|
||||||
{name: "SaturatedAddUint16x8", argLength: 2, commutative: true},
|
{name: "SaturatedAddUint16x8", argLength: 2, commutative: true},
|
||||||
{name: "SaturatedSubUint16x8", argLength: 2, commutative: false},
|
{name: "SaturatedSubUint16x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllLeftUint16x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightUint16x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftUint16x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromUint16x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightUint16x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromUint16x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedUint16x8", argLength: 2, commutative: false},
|
||||||
{name: "SubUint16x8", argLength: 2, commutative: false},
|
{name: "SubUint16x8", argLength: 2, commutative: false},
|
||||||
{name: "XorUint16x8", argLength: 2, commutative: true},
|
{name: "XorUint16x8", argLength: 2, commutative: true},
|
||||||
{name: "AddUint32x16", argLength: 2, commutative: true},
|
{name: "AddUint32x16", argLength: 2, commutative: true},
|
||||||
|
|
@ -899,7 +1077,14 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedNotEqualUint32x16", argLength: 3, commutative: true},
|
{name: "MaskedNotEqualUint32x16", argLength: 3, commutative: true},
|
||||||
{name: "MaskedOrUint32x16", argLength: 3, commutative: true},
|
{name: "MaskedOrUint32x16", argLength: 3, commutative: true},
|
||||||
{name: "MaskedPopCountUint32x16", argLength: 2, commutative: false},
|
{name: "MaskedPopCountUint32x16", argLength: 2, commutative: false},
|
||||||
|
{name: "MaskedRotateLeftUint32x16", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedRotateRightUint32x16", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 4, commutative: false},
|
{name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftUint32x16", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromUint32x16", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightUint32x16", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromUint32x16", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedUint32x16", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubUint32x16", argLength: 3, commutative: false},
|
{name: "MaskedSubUint32x16", argLength: 3, commutative: false},
|
||||||
{name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 4, commutative: false},
|
{name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 4, commutative: false},
|
||||||
{name: "MaskedXorUint32x16", argLength: 3, commutative: true},
|
{name: "MaskedXorUint32x16", argLength: 3, commutative: true},
|
||||||
|
|
@ -908,7 +1093,14 @@ func simdGenericOps() []opData {
|
||||||
{name: "NotEqualUint32x16", argLength: 2, commutative: true},
|
{name: "NotEqualUint32x16", argLength: 2, commutative: true},
|
||||||
{name: "OrUint32x16", argLength: 2, commutative: true},
|
{name: "OrUint32x16", argLength: 2, commutative: true},
|
||||||
{name: "PopCountUint32x16", argLength: 1, commutative: false},
|
{name: "PopCountUint32x16", argLength: 1, commutative: false},
|
||||||
|
{name: "RotateLeftUint32x16", argLength: 2, commutative: false},
|
||||||
|
{name: "RotateRightUint32x16", argLength: 2, commutative: false},
|
||||||
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 3, commutative: false},
|
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftLeftUint32x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromUint32x16", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightUint32x16", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromUint32x16", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedUint32x16", argLength: 2, commutative: false},
|
||||||
{name: "SubUint32x16", argLength: 2, commutative: false},
|
{name: "SubUint32x16", argLength: 2, commutative: false},
|
||||||
{name: "UnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 3, commutative: false},
|
{name: "UnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 3, commutative: false},
|
||||||
{name: "XorUint32x16", argLength: 2, commutative: true},
|
{name: "XorUint32x16", argLength: 2, commutative: true},
|
||||||
|
|
@ -933,7 +1125,14 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedNotEqualUint32x4", argLength: 3, commutative: true},
|
{name: "MaskedNotEqualUint32x4", argLength: 3, commutative: true},
|
||||||
{name: "MaskedOrUint32x4", argLength: 3, commutative: true},
|
{name: "MaskedOrUint32x4", argLength: 3, commutative: true},
|
||||||
{name: "MaskedPopCountUint32x4", argLength: 2, commutative: false},
|
{name: "MaskedPopCountUint32x4", argLength: 2, commutative: false},
|
||||||
|
{name: "MaskedRotateLeftUint32x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedRotateRightUint32x4", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 4, commutative: false},
|
{name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftUint32x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromUint32x4", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightUint32x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromUint32x4", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedUint32x4", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubUint32x4", argLength: 3, commutative: false},
|
{name: "MaskedSubUint32x4", argLength: 3, commutative: false},
|
||||||
{name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 4, commutative: false},
|
{name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 4, commutative: false},
|
||||||
{name: "MaskedXorUint32x4", argLength: 3, commutative: true},
|
{name: "MaskedXorUint32x4", argLength: 3, commutative: true},
|
||||||
|
|
@ -945,7 +1144,16 @@ func simdGenericOps() []opData {
|
||||||
{name: "PairwiseAddUint32x4", argLength: 2, commutative: false},
|
{name: "PairwiseAddUint32x4", argLength: 2, commutative: false},
|
||||||
{name: "PairwiseSubUint32x4", argLength: 2, commutative: false},
|
{name: "PairwiseSubUint32x4", argLength: 2, commutative: false},
|
||||||
{name: "PopCountUint32x4", argLength: 1, commutative: false},
|
{name: "PopCountUint32x4", argLength: 1, commutative: false},
|
||||||
|
{name: "RotateLeftUint32x4", argLength: 2, commutative: false},
|
||||||
|
{name: "RotateRightUint32x4", argLength: 2, commutative: false},
|
||||||
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 3, commutative: false},
|
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftAllLeftUint32x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightUint32x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftUint32x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromUint32x4", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightUint32x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromUint32x4", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedUint32x4", argLength: 2, commutative: false},
|
||||||
{name: "SubUint32x4", argLength: 2, commutative: false},
|
{name: "SubUint32x4", argLength: 2, commutative: false},
|
||||||
{name: "UnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 3, commutative: false},
|
{name: "UnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 3, commutative: false},
|
||||||
{name: "XorUint32x4", argLength: 2, commutative: true},
|
{name: "XorUint32x4", argLength: 2, commutative: true},
|
||||||
|
|
@ -970,7 +1178,14 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedNotEqualUint32x8", argLength: 3, commutative: true},
|
{name: "MaskedNotEqualUint32x8", argLength: 3, commutative: true},
|
||||||
{name: "MaskedOrUint32x8", argLength: 3, commutative: true},
|
{name: "MaskedOrUint32x8", argLength: 3, commutative: true},
|
||||||
{name: "MaskedPopCountUint32x8", argLength: 2, commutative: false},
|
{name: "MaskedPopCountUint32x8", argLength: 2, commutative: false},
|
||||||
|
{name: "MaskedRotateLeftUint32x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedRotateRightUint32x8", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 4, commutative: false},
|
{name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftUint32x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromUint32x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightUint32x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromUint32x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedUint32x8", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubUint32x8", argLength: 3, commutative: false},
|
{name: "MaskedSubUint32x8", argLength: 3, commutative: false},
|
||||||
{name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 4, commutative: false},
|
{name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 4, commutative: false},
|
||||||
{name: "MaskedXorUint32x8", argLength: 3, commutative: true},
|
{name: "MaskedXorUint32x8", argLength: 3, commutative: true},
|
||||||
|
|
@ -982,7 +1197,16 @@ func simdGenericOps() []opData {
|
||||||
{name: "PairwiseAddUint32x8", argLength: 2, commutative: false},
|
{name: "PairwiseAddUint32x8", argLength: 2, commutative: false},
|
||||||
{name: "PairwiseSubUint32x8", argLength: 2, commutative: false},
|
{name: "PairwiseSubUint32x8", argLength: 2, commutative: false},
|
||||||
{name: "PopCountUint32x8", argLength: 1, commutative: false},
|
{name: "PopCountUint32x8", argLength: 1, commutative: false},
|
||||||
|
{name: "RotateLeftUint32x8", argLength: 2, commutative: false},
|
||||||
|
{name: "RotateRightUint32x8", argLength: 2, commutative: false},
|
||||||
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 3, commutative: false},
|
{name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftAllLeftUint32x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightUint32x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftUint32x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromUint32x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightUint32x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromUint32x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedUint32x8", argLength: 2, commutative: false},
|
||||||
{name: "SubUint32x8", argLength: 2, commutative: false},
|
{name: "SubUint32x8", argLength: 2, commutative: false},
|
||||||
{name: "UnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 3, commutative: false},
|
{name: "UnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 3, commutative: false},
|
||||||
{name: "XorUint32x8", argLength: 2, commutative: true},
|
{name: "XorUint32x8", argLength: 2, commutative: true},
|
||||||
|
|
@ -1008,6 +1232,15 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedNotEqualUint64x2", argLength: 3, commutative: true},
|
{name: "MaskedNotEqualUint64x2", argLength: 3, commutative: true},
|
||||||
{name: "MaskedOrUint64x2", argLength: 3, commutative: true},
|
{name: "MaskedOrUint64x2", argLength: 3, commutative: true},
|
||||||
{name: "MaskedPopCountUint64x2", argLength: 2, commutative: false},
|
{name: "MaskedPopCountUint64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "MaskedRotateLeftUint64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedRotateRightUint64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllLeftUint64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllRightUint64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftUint64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromUint64x2", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightUint64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromUint64x2", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedUint64x2", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubUint64x2", argLength: 3, commutative: false},
|
{name: "MaskedSubUint64x2", argLength: 3, commutative: false},
|
||||||
{name: "MaskedXorUint64x2", argLength: 3, commutative: true},
|
{name: "MaskedXorUint64x2", argLength: 3, commutative: true},
|
||||||
{name: "MaxUint64x2", argLength: 2, commutative: true},
|
{name: "MaxUint64x2", argLength: 2, commutative: true},
|
||||||
|
|
@ -1016,6 +1249,15 @@ func simdGenericOps() []opData {
|
||||||
{name: "NotEqualUint64x2", argLength: 2, commutative: true},
|
{name: "NotEqualUint64x2", argLength: 2, commutative: true},
|
||||||
{name: "OrUint64x2", argLength: 2, commutative: true},
|
{name: "OrUint64x2", argLength: 2, commutative: true},
|
||||||
{name: "PopCountUint64x2", argLength: 1, commutative: false},
|
{name: "PopCountUint64x2", argLength: 1, commutative: false},
|
||||||
|
{name: "RotateLeftUint64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "RotateRightUint64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllLeftUint64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightUint64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftUint64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromUint64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightUint64x2", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromUint64x2", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedUint64x2", argLength: 2, commutative: false},
|
||||||
{name: "SubUint64x2", argLength: 2, commutative: false},
|
{name: "SubUint64x2", argLength: 2, commutative: false},
|
||||||
{name: "XorUint64x2", argLength: 2, commutative: true},
|
{name: "XorUint64x2", argLength: 2, commutative: true},
|
||||||
{name: "AddUint64x4", argLength: 2, commutative: true},
|
{name: "AddUint64x4", argLength: 2, commutative: true},
|
||||||
|
|
@ -1040,6 +1282,15 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedNotEqualUint64x4", argLength: 3, commutative: true},
|
{name: "MaskedNotEqualUint64x4", argLength: 3, commutative: true},
|
||||||
{name: "MaskedOrUint64x4", argLength: 3, commutative: true},
|
{name: "MaskedOrUint64x4", argLength: 3, commutative: true},
|
||||||
{name: "MaskedPopCountUint64x4", argLength: 2, commutative: false},
|
{name: "MaskedPopCountUint64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "MaskedRotateLeftUint64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedRotateRightUint64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllLeftUint64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllRightUint64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftUint64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromUint64x4", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightUint64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromUint64x4", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedUint64x4", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubUint64x4", argLength: 3, commutative: false},
|
{name: "MaskedSubUint64x4", argLength: 3, commutative: false},
|
||||||
{name: "MaskedXorUint64x4", argLength: 3, commutative: true},
|
{name: "MaskedXorUint64x4", argLength: 3, commutative: true},
|
||||||
{name: "MaxUint64x4", argLength: 2, commutative: true},
|
{name: "MaxUint64x4", argLength: 2, commutative: true},
|
||||||
|
|
@ -1048,6 +1299,15 @@ func simdGenericOps() []opData {
|
||||||
{name: "NotEqualUint64x4", argLength: 2, commutative: true},
|
{name: "NotEqualUint64x4", argLength: 2, commutative: true},
|
||||||
{name: "OrUint64x4", argLength: 2, commutative: true},
|
{name: "OrUint64x4", argLength: 2, commutative: true},
|
||||||
{name: "PopCountUint64x4", argLength: 1, commutative: false},
|
{name: "PopCountUint64x4", argLength: 1, commutative: false},
|
||||||
|
{name: "RotateLeftUint64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "RotateRightUint64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllLeftUint64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightUint64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftUint64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromUint64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightUint64x4", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromUint64x4", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedUint64x4", argLength: 2, commutative: false},
|
||||||
{name: "SubUint64x4", argLength: 2, commutative: false},
|
{name: "SubUint64x4", argLength: 2, commutative: false},
|
||||||
{name: "XorUint64x4", argLength: 2, commutative: true},
|
{name: "XorUint64x4", argLength: 2, commutative: true},
|
||||||
{name: "AddUint64x8", argLength: 2, commutative: true},
|
{name: "AddUint64x8", argLength: 2, commutative: true},
|
||||||
|
|
@ -1072,6 +1332,15 @@ func simdGenericOps() []opData {
|
||||||
{name: "MaskedNotEqualUint64x8", argLength: 3, commutative: true},
|
{name: "MaskedNotEqualUint64x8", argLength: 3, commutative: true},
|
||||||
{name: "MaskedOrUint64x8", argLength: 3, commutative: true},
|
{name: "MaskedOrUint64x8", argLength: 3, commutative: true},
|
||||||
{name: "MaskedPopCountUint64x8", argLength: 2, commutative: false},
|
{name: "MaskedPopCountUint64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "MaskedRotateLeftUint64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedRotateRightUint64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllLeftUint64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftAllRightUint64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftUint64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftLeftAndFillUpperFromUint64x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightUint64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "MaskedShiftRightAndFillUpperFromUint64x8", argLength: 4, commutative: false},
|
||||||
|
{name: "MaskedShiftRightSignExtendedUint64x8", argLength: 3, commutative: false},
|
||||||
{name: "MaskedSubUint64x8", argLength: 3, commutative: false},
|
{name: "MaskedSubUint64x8", argLength: 3, commutative: false},
|
||||||
{name: "MaskedXorUint64x8", argLength: 3, commutative: true},
|
{name: "MaskedXorUint64x8", argLength: 3, commutative: true},
|
||||||
{name: "MaxUint64x8", argLength: 2, commutative: true},
|
{name: "MaxUint64x8", argLength: 2, commutative: true},
|
||||||
|
|
@ -1080,6 +1349,15 @@ func simdGenericOps() []opData {
|
||||||
{name: "NotEqualUint64x8", argLength: 2, commutative: true},
|
{name: "NotEqualUint64x8", argLength: 2, commutative: true},
|
||||||
{name: "OrUint64x8", argLength: 2, commutative: true},
|
{name: "OrUint64x8", argLength: 2, commutative: true},
|
||||||
{name: "PopCountUint64x8", argLength: 1, commutative: false},
|
{name: "PopCountUint64x8", argLength: 1, commutative: false},
|
||||||
|
{name: "RotateLeftUint64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "RotateRightUint64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllLeftUint64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftAllRightUint64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftUint64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftLeftAndFillUpperFromUint64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightUint64x8", argLength: 2, commutative: false},
|
||||||
|
{name: "ShiftRightAndFillUpperFromUint64x8", argLength: 3, commutative: false},
|
||||||
|
{name: "ShiftRightSignExtendedUint64x8", argLength: 2, commutative: false},
|
||||||
{name: "SubUint64x8", argLength: 2, commutative: false},
|
{name: "SubUint64x8", argLength: 2, commutative: false},
|
||||||
{name: "XorUint64x8", argLength: 2, commutative: true},
|
{name: "XorUint64x8", argLength: 2, commutative: true},
|
||||||
{name: "AddUint8x16", argLength: 2, commutative: true},
|
{name: "AddUint8x16", argLength: 2, commutative: true},
|
||||||
|
|
@ -1372,20 +1650,140 @@ func simdGenericOps() []opData {
|
||||||
{name: "RoundWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
{name: "RoundWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
{name: "TruncSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
{name: "TruncSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
{name: "TruncWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
{name: "TruncWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromInt16x16", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromInt16x16", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromInt16x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromInt16x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromInt16x32", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromInt16x32", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromInt16x32", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromInt16x32", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
{name: "GetElemInt16x8", argLength: 1, commutative: false, aux: "Int8"},
|
{name: "GetElemInt16x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromInt16x8", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromInt16x8", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
{name: "SetElemInt16x8", argLength: 2, commutative: false, aux: "Int8"},
|
{name: "SetElemInt16x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromInt16x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromInt16x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllLeftInt32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllRightInt32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromInt32x16", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromInt32x16", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllLeftInt32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllRightInt32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromInt32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromInt32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
{name: "GetElemInt32x4", argLength: 1, commutative: false, aux: "Int8"},
|
{name: "GetElemInt32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllLeftInt32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllRightInt32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromInt32x4", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromInt32x4", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllLeftInt32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllRightInt32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
{name: "SetElemInt32x4", argLength: 2, commutative: false, aux: "Int8"},
|
{name: "SetElemInt32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromInt32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromInt32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllLeftInt32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllRightInt32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromInt32x8", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromInt32x8", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllLeftInt32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllRightInt32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromInt32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromInt32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
{name: "GetElemInt64x2", argLength: 1, commutative: false, aux: "Int8"},
|
{name: "GetElemInt64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllLeftInt64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllRightInt64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromInt64x2", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromInt64x2", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllLeftInt64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllRightInt64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
{name: "SetElemInt64x2", argLength: 2, commutative: false, aux: "Int8"},
|
{name: "SetElemInt64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromInt64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromInt64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllLeftInt64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllRightInt64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromInt64x4", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromInt64x4", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllLeftInt64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllRightInt64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromInt64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromInt64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllLeftInt64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllRightInt64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromInt64x8", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromInt64x8", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllLeftInt64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllRightInt64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromInt64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromInt64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
{name: "GetElemInt8x16", argLength: 1, commutative: false, aux: "Int8"},
|
{name: "GetElemInt8x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
{name: "SetElemInt8x16", argLength: 2, commutative: false, aux: "Int8"},
|
{name: "SetElemInt8x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromUint16x16", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromUint16x16", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromUint16x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromUint16x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromUint16x32", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromUint16x32", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromUint16x32", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromUint16x32", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
{name: "GetElemUint16x8", argLength: 1, commutative: false, aux: "Int8"},
|
{name: "GetElemUint16x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromUint16x8", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromUint16x8", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
{name: "SetElemUint16x8", argLength: 2, commutative: false, aux: "Int8"},
|
{name: "SetElemUint16x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromUint16x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromUint16x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllLeftUint32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllRightUint32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromUint32x16", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromUint32x16", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllLeftUint32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllRightUint32x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromUint32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromUint32x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
{name: "GetElemUint32x4", argLength: 1, commutative: false, aux: "Int8"},
|
{name: "GetElemUint32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllLeftUint32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllRightUint32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromUint32x4", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromUint32x4", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllLeftUint32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllRightUint32x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
{name: "SetElemUint32x4", argLength: 2, commutative: false, aux: "Int8"},
|
{name: "SetElemUint32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromUint32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromUint32x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllLeftUint32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllRightUint32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromUint32x8", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromUint32x8", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllLeftUint32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllRightUint32x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromUint32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromUint32x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
{name: "GetElemUint64x2", argLength: 1, commutative: false, aux: "Int8"},
|
{name: "GetElemUint64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllLeftUint64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllRightUint64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromUint64x2", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromUint64x2", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllLeftUint64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllRightUint64x2", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
{name: "SetElemUint64x2", argLength: 2, commutative: false, aux: "Int8"},
|
{name: "SetElemUint64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromUint64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromUint64x2", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllLeftUint64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllRightUint64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromUint64x4", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromUint64x4", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllLeftUint64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllRightUint64x4", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromUint64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromUint64x4", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllLeftUint64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedRotateAllRightUint64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllLeftAndFillUpperFromUint64x8", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "MaskedShiftAllRightAndFillUpperFromUint64x8", argLength: 3, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllLeftUint64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "RotateAllRightUint64x8", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllLeftAndFillUpperFromUint64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
|
{name: "ShiftAllRightAndFillUpperFromUint64x8", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
{name: "GetElemUint8x16", argLength: 1, commutative: false, aux: "Int8"},
|
{name: "GetElemUint8x16", argLength: 1, commutative: false, aux: "Int8"},
|
||||||
{name: "SetElemUint8x16", argLength: 2, commutative: false, aux: "Int8"},
|
{name: "SetElemUint8x16", argLength: 2, commutative: false, aux: "Int8"},
|
||||||
}
|
}
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -915,6 +915,54 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
||||||
addF(simdPackage, "Uint64x2.MaskedPopCount", opLen2(ssa.OpMaskedPopCountUint64x2, types.TypeVec128), sys.AMD64)
|
addF(simdPackage, "Uint64x2.MaskedPopCount", opLen2(ssa.OpMaskedPopCountUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
addF(simdPackage, "Uint64x4.MaskedPopCount", opLen2(ssa.OpMaskedPopCountUint64x4, types.TypeVec256), sys.AMD64)
|
addF(simdPackage, "Uint64x4.MaskedPopCount", opLen2(ssa.OpMaskedPopCountUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
addF(simdPackage, "Uint64x8.MaskedPopCount", opLen2(ssa.OpMaskedPopCountUint64x8, types.TypeVec512), sys.AMD64)
|
addF(simdPackage, "Uint64x8.MaskedPopCount", opLen2(ssa.OpMaskedPopCountUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftInt32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftInt32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftInt32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftInt64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftInt64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftInt64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftUint32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftUint32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftUint32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftUint64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftUint64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.MaskedRotateAllLeft", opLen2Imm8(ssa.OpMaskedRotateAllLeftUint64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightInt32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightInt32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightInt32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightInt64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightInt64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightInt64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightUint32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightUint32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightUint32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightUint64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightUint64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.MaskedRotateAllRight", opLen2Imm8(ssa.OpMaskedRotateAllRightUint64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.MaskedRotateLeft", opLen3(ssa.OpMaskedRotateLeftUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.MaskedRotateRight", opLen3(ssa.OpMaskedRotateRightUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
addF(simdPackage, "Float32x4.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
addF(simdPackage, "Float32x4.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat32x4, types.TypeVec128, 4), sys.AMD64)
|
||||||
addF(simdPackage, "Float32x8.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
addF(simdPackage, "Float32x8.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat32x8, types.TypeVec256, 4), sys.AMD64)
|
||||||
addF(simdPackage, "Float32x16.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
addF(simdPackage, "Float32x16.MaskedRoundSuppressExceptionWithPrecision", opLen2Imm8(ssa.OpMaskedRoundSuppressExceptionWithPrecisionFloat32x16, types.TypeVec512, 4), sys.AMD64)
|
||||||
|
|
@ -963,6 +1011,147 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
||||||
addF(simdPackage, "Uint32x4.MaskedSaturatedUnsignedSignedQuadDotProdAccumulate", opLen4(ssa.OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4, types.TypeVec128), sys.AMD64)
|
addF(simdPackage, "Uint32x4.MaskedSaturatedUnsignedSignedQuadDotProdAccumulate", opLen4(ssa.OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
addF(simdPackage, "Uint32x8.MaskedSaturatedUnsignedSignedQuadDotProdAccumulate", opLen4(ssa.OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8, types.TypeVec256), sys.AMD64)
|
addF(simdPackage, "Uint32x8.MaskedSaturatedUnsignedSignedQuadDotProdAccumulate", opLen4(ssa.OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
addF(simdPackage, "Uint32x16.MaskedSaturatedUnsignedSignedQuadDotProdAccumulate", opLen4(ssa.OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16, types.TypeVec512), sys.AMD64)
|
addF(simdPackage, "Uint32x16.MaskedSaturatedUnsignedSignedQuadDotProdAccumulate", opLen4(ssa.OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedShiftAllLeft", opLen3(ssa.OpMaskedShiftAllLeftInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedShiftAllLeft", opLen3(ssa.OpMaskedShiftAllLeftInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedShiftAllLeft", opLen3(ssa.OpMaskedShiftAllLeftInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.MaskedShiftAllLeft", opLen3(ssa.OpMaskedShiftAllLeftUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.MaskedShiftAllLeft", opLen3(ssa.OpMaskedShiftAllLeftUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.MaskedShiftAllLeft", opLen3(ssa.OpMaskedShiftAllLeftUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt16x8, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt16x16, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt16x32, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromInt64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint16x8, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint16x16, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint16x32, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.MaskedShiftAllLeftAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllLeftAndFillUpperFromUint64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedShiftAllRight", opLen3(ssa.OpMaskedShiftAllRightInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedShiftAllRight", opLen3(ssa.OpMaskedShiftAllRightInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedShiftAllRight", opLen3(ssa.OpMaskedShiftAllRightInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.MaskedShiftAllRight", opLen3(ssa.OpMaskedShiftAllRightUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.MaskedShiftAllRight", opLen3(ssa.OpMaskedShiftAllRightUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.MaskedShiftAllRight", opLen3(ssa.OpMaskedShiftAllRightUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt16x8, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt16x16, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt16x32, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromInt64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint16x8, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint16x16, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint16x32, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.MaskedShiftAllRightAndFillUpperFrom", opLen3Imm8(ssa.OpMaskedShiftAllRightAndFillUpperFromUint64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedShiftAllRightSignExtended", opLen3(ssa.OpMaskedShiftAllRightSignExtendedInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedShiftAllRightSignExtended", opLen3(ssa.OpMaskedShiftAllRightSignExtendedInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedShiftAllRightSignExtended", opLen3(ssa.OpMaskedShiftAllRightSignExtendedInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.MaskedShiftLeft", opLen3(ssa.OpMaskedShiftLeftUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.MaskedShiftLeftAndFillUpperFrom", opLen4(ssa.OpMaskedShiftLeftAndFillUpperFromUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.MaskedShiftRight", opLen3(ssa.OpMaskedShiftRightUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.MaskedShiftRightAndFillUpperFrom", opLen4(ssa.OpMaskedShiftRightAndFillUpperFromUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.MaskedShiftRightSignExtended", opLen3(ssa.OpMaskedShiftRightSignExtendedUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
addF(simdPackage, "Float32x4.MaskedSqrt", opLen2(ssa.OpMaskedSqrtFloat32x4, types.TypeVec128), sys.AMD64)
|
addF(simdPackage, "Float32x4.MaskedSqrt", opLen2(ssa.OpMaskedSqrtFloat32x4, types.TypeVec128), sys.AMD64)
|
||||||
addF(simdPackage, "Float32x8.MaskedSqrt", opLen2(ssa.OpMaskedSqrtFloat32x8, types.TypeVec256), sys.AMD64)
|
addF(simdPackage, "Float32x8.MaskedSqrt", opLen2(ssa.OpMaskedSqrtFloat32x8, types.TypeVec256), sys.AMD64)
|
||||||
addF(simdPackage, "Float32x16.MaskedSqrt", opLen2(ssa.OpMaskedSqrtFloat32x16, types.TypeVec512), sys.AMD64)
|
addF(simdPackage, "Float32x16.MaskedSqrt", opLen2(ssa.OpMaskedSqrtFloat32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
|
@ -1242,6 +1431,54 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
||||||
addF(simdPackage, "Uint64x2.PopCount", opLen1(ssa.OpPopCountUint64x2, types.TypeVec128), sys.AMD64)
|
addF(simdPackage, "Uint64x2.PopCount", opLen1(ssa.OpPopCountUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
addF(simdPackage, "Uint64x4.PopCount", opLen1(ssa.OpPopCountUint64x4, types.TypeVec256), sys.AMD64)
|
addF(simdPackage, "Uint64x4.PopCount", opLen1(ssa.OpPopCountUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
addF(simdPackage, "Uint64x8.PopCount", opLen1(ssa.OpPopCountUint64x8, types.TypeVec512), sys.AMD64)
|
addF(simdPackage, "Uint64x8.PopCount", opLen1(ssa.OpPopCountUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftInt64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.RotateAllLeft", opLen1Imm8(ssa.OpRotateAllLeftUint64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightInt64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.RotateAllRight", opLen1Imm8(ssa.OpRotateAllRightUint64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.RotateLeft", opLen2(ssa.OpRotateLeftInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.RotateLeft", opLen2(ssa.OpRotateLeftInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.RotateLeft", opLen2(ssa.OpRotateLeftInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.RotateLeft", opLen2(ssa.OpRotateLeftInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.RotateLeft", opLen2(ssa.OpRotateLeftInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.RotateLeft", opLen2(ssa.OpRotateLeftInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.RotateLeft", opLen2(ssa.OpRotateLeftUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.RotateLeft", opLen2(ssa.OpRotateLeftUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.RotateLeft", opLen2(ssa.OpRotateLeftUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.RotateLeft", opLen2(ssa.OpRotateLeftUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.RotateLeft", opLen2(ssa.OpRotateLeftUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.RotateLeft", opLen2(ssa.OpRotateLeftUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.RotateRight", opLen2(ssa.OpRotateRightInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.RotateRight", opLen2(ssa.OpRotateRightInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.RotateRight", opLen2(ssa.OpRotateRightInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.RotateRight", opLen2(ssa.OpRotateRightInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.RotateRight", opLen2(ssa.OpRotateRightInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.RotateRight", opLen2(ssa.OpRotateRightInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.RotateRight", opLen2(ssa.OpRotateRightUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.RotateRight", opLen2(ssa.OpRotateRightUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.RotateRight", opLen2(ssa.OpRotateRightUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.RotateRight", opLen2(ssa.OpRotateRightUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.RotateRight", opLen2(ssa.OpRotateRightUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.RotateRight", opLen2(ssa.OpRotateRightUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
addF(simdPackage, "Float32x4.Round", opLen1(ssa.OpRoundFloat32x4, types.TypeVec128), sys.AMD64)
|
addF(simdPackage, "Float32x4.Round", opLen1(ssa.OpRoundFloat32x4, types.TypeVec128), sys.AMD64)
|
||||||
addF(simdPackage, "Float32x8.Round", opLen1(ssa.OpRoundFloat32x8, types.TypeVec256), sys.AMD64)
|
addF(simdPackage, "Float32x8.Round", opLen1(ssa.OpRoundFloat32x8, types.TypeVec256), sys.AMD64)
|
||||||
addF(simdPackage, "Float64x2.Round", opLen1(ssa.OpRoundFloat64x2, types.TypeVec128), sys.AMD64)
|
addF(simdPackage, "Float64x2.Round", opLen1(ssa.OpRoundFloat64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
|
@ -1306,6 +1543,167 @@ func simdIntrinsics(addF func(pkg, fn string, b intrinsicBuilder, archFamilies .
|
||||||
addF(simdPackage, "Uint16x8.SetElem", opLen2Imm8(ssa.OpSetElemUint16x8, types.TypeVec128, 0), sys.AMD64)
|
addF(simdPackage, "Uint16x8.SetElem", opLen2Imm8(ssa.OpSetElemUint16x8, types.TypeVec128, 0), sys.AMD64)
|
||||||
addF(simdPackage, "Uint32x4.SetElem", opLen2Imm8(ssa.OpSetElemUint32x4, types.TypeVec128, 0), sys.AMD64)
|
addF(simdPackage, "Uint32x4.SetElem", opLen2Imm8(ssa.OpSetElemUint32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
addF(simdPackage, "Uint64x2.SetElem", opLen2Imm8(ssa.OpSetElemUint64x2, types.TypeVec128, 0), sys.AMD64)
|
addF(simdPackage, "Uint64x2.SetElem", opLen2Imm8(ssa.OpSetElemUint64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.ShiftAllLeft", opLen2(ssa.OpShiftAllLeftUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt16x8, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt16x16, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt16x32, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromInt64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint16x8, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint16x16, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint16x32, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.ShiftAllLeftAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllLeftAndFillUpperFromUint64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.ShiftAllRight", opLen2(ssa.OpShiftAllRightUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt16x8, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt16x16, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt16x32, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromInt64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint16x8, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint16x16, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint16x32, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint32x4, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint32x8, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint32x16, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint64x2, types.TypeVec128, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint64x4, types.TypeVec256, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.ShiftAllRightAndFillUpperFrom", opLen2Imm8(ssa.OpShiftAllRightAndFillUpperFromUint64x8, types.TypeVec512, 0), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.ShiftAllRightSignExtended", opLen2(ssa.OpShiftAllRightSignExtendedInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.ShiftLeft", opLen2(ssa.OpShiftLeftInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.ShiftLeft", opLen2(ssa.OpShiftLeftInt16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.ShiftLeft", opLen2(ssa.OpShiftLeftInt16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.ShiftLeft", opLen2(ssa.OpShiftLeftInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.ShiftLeft", opLen2(ssa.OpShiftLeftInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.ShiftLeft", opLen2(ssa.OpShiftLeftInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.ShiftLeft", opLen2(ssa.OpShiftLeftInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.ShiftLeft", opLen2(ssa.OpShiftLeftInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.ShiftLeft", opLen2(ssa.OpShiftLeftInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.ShiftLeft", opLen2(ssa.OpShiftLeftUint16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.ShiftLeft", opLen2(ssa.OpShiftLeftUint16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.ShiftLeft", opLen2(ssa.OpShiftLeftUint16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.ShiftLeft", opLen2(ssa.OpShiftLeftUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.ShiftLeft", opLen2(ssa.OpShiftLeftUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.ShiftLeft", opLen2(ssa.OpShiftLeftUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.ShiftLeft", opLen2(ssa.OpShiftLeftUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.ShiftLeft", opLen2(ssa.OpShiftLeftUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.ShiftLeft", opLen2(ssa.OpShiftLeftUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.ShiftLeftAndFillUpperFrom", opLen3(ssa.OpShiftLeftAndFillUpperFromUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.ShiftRight", opLen2(ssa.OpShiftRightInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.ShiftRight", opLen2(ssa.OpShiftRightInt16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.ShiftRight", opLen2(ssa.OpShiftRightInt16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.ShiftRight", opLen2(ssa.OpShiftRightInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.ShiftRight", opLen2(ssa.OpShiftRightInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.ShiftRight", opLen2(ssa.OpShiftRightInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.ShiftRight", opLen2(ssa.OpShiftRightInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.ShiftRight", opLen2(ssa.OpShiftRightInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.ShiftRight", opLen2(ssa.OpShiftRightInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.ShiftRight", opLen2(ssa.OpShiftRightUint16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.ShiftRight", opLen2(ssa.OpShiftRightUint16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.ShiftRight", opLen2(ssa.OpShiftRightUint16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.ShiftRight", opLen2(ssa.OpShiftRightUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.ShiftRight", opLen2(ssa.OpShiftRightUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.ShiftRight", opLen2(ssa.OpShiftRightUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.ShiftRight", opLen2(ssa.OpShiftRightUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.ShiftRight", opLen2(ssa.OpShiftRightUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.ShiftRight", opLen2(ssa.OpShiftRightUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.ShiftRightAndFillUpperFrom", opLen3(ssa.OpShiftRightAndFillUpperFromUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x8.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x16.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int16x32.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x4.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x8.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int32x16.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x2.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x4.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Int64x8.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedInt64x8, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x8.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x16.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint16x16, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint16x32.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint16x32, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x4.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint32x4, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x8.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint32x8, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint32x16.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint32x16, types.TypeVec512), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x2.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint64x2, types.TypeVec128), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x4.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint64x4, types.TypeVec256), sys.AMD64)
|
||||||
|
addF(simdPackage, "Uint64x8.ShiftRightSignExtended", opLen2(ssa.OpShiftRightSignExtendedUint64x8, types.TypeVec512), sys.AMD64)
|
||||||
addF(simdPackage, "Int8x16.Sign", opLen2(ssa.OpSignInt8x16, types.TypeVec128), sys.AMD64)
|
addF(simdPackage, "Int8x16.Sign", opLen2(ssa.OpSignInt8x16, types.TypeVec128), sys.AMD64)
|
||||||
addF(simdPackage, "Int8x32.Sign", opLen2(ssa.OpSignInt8x32, types.TypeVec256), sys.AMD64)
|
addF(simdPackage, "Int8x32.Sign", opLen2(ssa.OpSignInt8x32, types.TypeVec256), sys.AMD64)
|
||||||
addF(simdPackage, "Int16x8.Sign", opLen2(ssa.OpSignInt16x8, types.TypeVec128), sys.AMD64)
|
addF(simdPackage, "Int16x8.Sign", opLen2(ssa.OpSignInt16x8, types.TypeVec128), sys.AMD64)
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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Add table
Add a link
Reference in a new issue