Stowage/go
2
0
Fork 0
mirror of https://github.com/golang/go.git synced 2025-12-08 06:10:04 +00:00
Code Issues Projects Releases Packages Wiki Activity

cmd/internal/obj/loong64: add support for FSEL instruction

Browse source 
Go asm syntax:
	FSEL	FCC, FK, FJ, FD

Equivalent platform assembler syntax:
	fsel	fd, fj, fk, ca

Change-Id: If75f16fca0adfc03f4952f8a5143d22da33ed425
Reviewed-on: https://go-review.googlesource.com/c/go/+/693457
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Meidan Li <limeidan@loongson.cn>
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Mark Freeman <markfreeman@google.com>
This commit is contained in:
Xiaolin Zhao 2025-08-06 11:07:57 +08:00 • committed by abner chenc
parent 1f7ffca171
commit ee7bb8969a
4 changed files with 22 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/cmd/asm/internal/asm/testdata/loong64enc1.s vendored
View file

@ -376,6 +376,10 @@ lable2:
FTINTRNEVF F0, F2 // 02e41a01 FTINTRNEVF F0, F2 // 02e41a01
FTINTRNEVD F0, F2 // 02e81a01 FTINTRNEVD F0, F2 // 02e81a01
// FSEL instruction
FSEL FCC0, F1, F2, F3 // 4304000d
FSEL FCC1, F1, F2 // 4284000d
// LDX.{B,BU,H,HU,W,WU,D} instructions // LDX.{B,BU,H,HU,W,WU,D} instructions
MOVB (R14)(R13), R12 // cc350038 MOVB (R14)(R13), R12 // cc350038
MOVBU (R14)(R13), R12 // cc352038 MOVBU (R14)(R13), R12 // cc352038

3
src/cmd/internal/obj/loong64/a.out.go
View file

@ -748,6 +748,9 @@ const (
AFTINTRNEVF AFTINTRNEVF
AFTINTRNEVD AFTINTRNEVD
// 3.2.4.2
AFSEL
// LSX and LASX memory access instructions // LSX and LASX memory access instructions
AVMOVQ AVMOVQ
AXVMOVQ AXVMOVQ

1
src/cmd/internal/obj/loong64/anames.go
View file

@ -264,6 +264,7 @@ var Anames = []string{
"FTINTRNEWD", "FTINTRNEWD",
"FTINTRNEVF", "FTINTRNEVF",
"FTINTRNEVD", "FTINTRNEVD",
"FSEL",
"VMOVQ", "VMOVQ",
"XVMOVQ", "XVMOVQ",
"VADDB", "VADDB",

14
src/cmd/internal/obj/loong64/asm.go
View file

@ -154,6 +154,9 @@ var optab = []Optab{
{AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0}, {AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0},
{AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0}, {AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0},
{AFSEL, C_FCCREG, C_FREG, C_FREG, C_FREG, C_NONE, 33, 4, 0, 0},
{AFSEL, C_FCCREG, C_FREG, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
{AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
{AMOVWU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, {AMOVWU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
{AMOVV, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0}, {AMOVV, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
@ -1517,6 +1520,7 @@ func buildop(ctxt *obj.Link) {
AWORD, AWORD,
APRELD, APRELD,
APRELDX, APRELDX,
AFSEL,
obj.ANOP, obj.ANOP,
obj.ATEXT, obj.ATEXT,
obj.AFUNCDATA, obj.AFUNCDATA,
@ -2387,6 +2391,16 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
} }
o1 = OP_6IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg)) o1 = OP_6IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
case 33: // fsel ca, fk, [fj], fd
ca := uint32(p.From.Reg)
fk := uint32(p.Reg)
fd := uint32(p.To.Reg)
fj := fd
if len(p.RestArgs) > 0 {
fj = uint32(p.GetFrom3().Reg)
}
o1 = 0x340<<18 | (ca&0x7)<<15 | (fk&0x1F)<<10 | (fj&0x1F)<<5 | (fd & 0x1F)
case 34: // mov $con,fr case 34: // mov $con,fr
v := c.regoff(&p.From) v := c.regoff(&p.From)
a := AADDU a := AADDU