cmd/compile: retrieve Args from registers

in progress; doesn't fully work until they are also passed on
register on the caller side.

For #40724.

Change-Id: I29a6680e60bdbe9d132782530214f2a2b51fb8f6
Reviewed-on: https://go-review.googlesource.com/c/go/+/293394
Trust: David Chase <drchase@google.com>
Run-TryBot: David Chase <drchase@google.com>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
This commit is contained in:
David Chase 2021-02-13 10:49:37 -05:00
parent 06c72f3627
commit f2df1e3c34
8 changed files with 64 additions and 14 deletions

View file

@ -800,7 +800,8 @@ func (s *regAllocState) compatRegs(t *types.Type) regMask {
}
// regspec returns the regInfo for operation op.
func (s *regAllocState) regspec(op Op) regInfo {
func (s *regAllocState) regspec(v *Value) regInfo {
op := v.Op
if op == OpConvert {
// OpConvert is a generic op, so it doesn't have a
// register set in the static table. It can use any
@ -808,6 +809,20 @@ func (s *regAllocState) regspec(op Op) regInfo {
m := s.allocatable & s.f.Config.gpRegMask
return regInfo{inputs: []inputInfo{{regs: m}}, outputs: []outputInfo{{regs: m}}}
}
if op == OpArgIntReg {
reg := v.Block.Func.Config.intParamRegs[v.AuxInt8()]
return regInfo{outputs: []outputInfo{{regs: 1 << uint(reg)}}}
}
if op == OpArgFloatReg {
reg := v.Block.Func.Config.floatParamRegs[v.AuxInt8()]
return regInfo{outputs: []outputInfo{{regs: 1 << uint(reg)}}}
}
if op.IsCall() {
// TODO Panic if not okay
if ac, ok := v.Aux.(*AuxCall); ok && ac.reg != nil {
return *ac.reg
}
}
return opcodeTable[op].reg
}
@ -1163,7 +1178,7 @@ func (s *regAllocState) regalloc(f *Func) {
for i := len(oldSched) - 1; i >= 0; i-- {
v := oldSched[i]
prefs := desired.remove(v.ID)
regspec := s.regspec(v.Op)
regspec := s.regspec(v)
desired.clobber(regspec.clobbers)
for _, j := range regspec.inputs {
if countRegs(j.regs) != 1 {
@ -1193,7 +1208,7 @@ func (s *regAllocState) regalloc(f *Func) {
if s.f.pass.debug > regDebug {
fmt.Printf(" processing %s\n", v.LongString())
}
regspec := s.regspec(v.Op)
regspec := s.regspec(v)
if v.Op == OpPhi {
f.Fatalf("phi %s not at start of block", v)
}
@ -2447,7 +2462,7 @@ func (s *regAllocState) computeLive() {
// desired registers back though phi nodes.
continue
}
regspec := s.regspec(v.Op)
regspec := s.regspec(v)
// Cancel desired registers if they get clobbered.
desired.clobber(regspec.clobbers)
// Update desired registers if there are any fixed register inputs.