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cmd/compile: add support for GOARCH=mips{,le}
Change-Id: Ib489dc847787aaab7ba1be96792f885469e346ae Reviewed-on: https://go-review.googlesource.com/31479 Run-TryBot: Brad Fitzpatrick <bradfitz@golang.org> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
This commit is contained in:
Vladimir Stefanovic
Brad Fitzpatrick
parent
247fc4a98e
commit
f4c997578a
4 changed files with 1191 additions and 0 deletions
907
src/cmd/compile/internal/mips/ssa.go
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907
src/cmd/compile/internal/mips/ssa.go
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@ -0,0 +1,907 @@
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// Copyright 2016 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package mips
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import (
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"math"
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"cmd/compile/internal/gc"
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"cmd/compile/internal/ssa"
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"cmd/internal/obj"
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"cmd/internal/obj/mips"
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)
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// isFPreg returns whether r is an FP register
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func isFPreg(r int16) bool {
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return mips.REG_F0 <= r && r <= mips.REG_F31
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}
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// isHILO returns whether r is HI or LO register
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func isHILO(r int16) bool {
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return r == mips.REG_HI || r == mips.REG_LO
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}
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// loadByType returns the load instruction of the given type.
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func loadByType(t ssa.Type, r int16) obj.As {
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if isFPreg(r) {
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if t.Size() == 4 { // float32 or int32
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return mips.AMOVF
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} else { // float64 or int64
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return mips.AMOVD
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}
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} else {
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switch t.Size() {
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case 1:
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if t.IsSigned() {
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return mips.AMOVB
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} else {
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return mips.AMOVBU
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}
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case 2:
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if t.IsSigned() {
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return mips.AMOVH
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} else {
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return mips.AMOVHU
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}
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case 4:
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return mips.AMOVW
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}
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}
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panic("bad load type")
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}
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// storeByType returns the store instruction of the given type.
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func storeByType(t ssa.Type, r int16) obj.As {
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if isFPreg(r) {
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if t.Size() == 4 { // float32 or int32
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return mips.AMOVF
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} else { // float64 or int64
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return mips.AMOVD
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}
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} else {
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switch t.Size() {
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case 1:
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return mips.AMOVB
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case 2:
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return mips.AMOVH
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case 4:
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return mips.AMOVW
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}
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}
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panic("bad store type")
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}
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func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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s.SetLineno(v.Line)
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switch v.Op {
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case ssa.OpInitMem:
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// memory arg needs no code
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case ssa.OpArg:
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// input args need no code
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case ssa.OpSP, ssa.OpSB, ssa.OpGetG:
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// nothing to do
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case ssa.OpSelect0, ssa.OpSelect1:
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// nothing to do
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case ssa.OpCopy, ssa.OpMIPSMOVWconvert, ssa.OpMIPSMOVWreg:
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t := v.Type
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if t.IsMemory() {
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return
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}
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x := v.Args[0].Reg()
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y := v.Reg()
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if x == y {
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return
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}
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as := mips.AMOVW
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if isFPreg(x) && isFPreg(y) {
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as = mips.AMOVF
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if t.Size() == 8 {
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as = mips.AMOVD
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}
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}
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p := gc.Prog(as)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = y
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if isHILO(x) && isHILO(y) || isHILO(x) && isFPreg(y) || isFPreg(x) && isHILO(y) {
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// cannot move between special registers, use TMP as intermediate
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p.To.Reg = mips.REGTMP
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p = gc.Prog(mips.AMOVW)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = mips.REGTMP
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p.To.Type = obj.TYPE_REG
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p.To.Reg = y
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}
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case ssa.OpMIPSMOVWnop:
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if v.Reg() != v.Args[0].Reg() {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
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// nothing to do
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case ssa.OpLoadReg:
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if v.Type.IsFlags() {
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v.Fatalf("load flags not implemented: %v", v.LongString())
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return
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}
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r := v.Reg()
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p := gc.Prog(loadByType(v.Type, r))
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gc.AddrAuto(&p.From, v.Args[0])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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if isHILO(r) {
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// cannot directly load, load to TMP and move
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p.To.Reg = mips.REGTMP
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p = gc.Prog(mips.AMOVW)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = mips.REGTMP
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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}
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case ssa.OpStoreReg:
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if v.Type.IsFlags() {
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v.Fatalf("store flags not implemented: %v", v.LongString())
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return
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}
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r := v.Args[0].Reg()
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if isHILO(r) {
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// cannot directly store, move to TMP and store
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p := gc.Prog(mips.AMOVW)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = r
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p.To.Type = obj.TYPE_REG
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p.To.Reg = mips.REGTMP
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r = mips.REGTMP
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}
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p := gc.Prog(storeByType(v.Type, r))
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p.From.Type = obj.TYPE_REG
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p.From.Reg = r
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gc.AddrAuto(&p.To, v)
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case ssa.OpMIPSADD,
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ssa.OpMIPSSUB,
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ssa.OpMIPSAND,
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ssa.OpMIPSOR,
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ssa.OpMIPSXOR,
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ssa.OpMIPSNOR,
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ssa.OpMIPSSLL,
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ssa.OpMIPSSRL,
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ssa.OpMIPSSRA,
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ssa.OpMIPSADDF,
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ssa.OpMIPSADDD,
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ssa.OpMIPSSUBF,
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ssa.OpMIPSSUBD,
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ssa.OpMIPSMULF,
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ssa.OpMIPSMULD,
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ssa.OpMIPSDIVF,
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ssa.OpMIPSDIVD,
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ssa.OpMIPSMUL:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[1].Reg()
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p.Reg = v.Args[0].Reg()
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpMIPSSGT,
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ssa.OpMIPSSGTU:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[0].Reg()
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p.Reg = v.Args[1].Reg()
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpMIPSSGTzero,
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ssa.OpMIPSSGTUzero:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[0].Reg()
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p.Reg = mips.REGZERO
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpMIPSADDconst,
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ssa.OpMIPSSUBconst,
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ssa.OpMIPSANDconst,
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ssa.OpMIPSORconst,
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ssa.OpMIPSXORconst,
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ssa.OpMIPSNORconst,
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ssa.OpMIPSSLLconst,
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ssa.OpMIPSSRLconst,
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ssa.OpMIPSSRAconst,
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ssa.OpMIPSSGTconst,
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ssa.OpMIPSSGTUconst:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.Reg = v.Args[0].Reg()
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpMIPSMULT,
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ssa.OpMIPSMULTU,
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ssa.OpMIPSDIV,
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ssa.OpMIPSDIVU:
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// result in hi,lo
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[1].Reg()
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p.Reg = v.Args[0].Reg()
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case ssa.OpMIPSMOVWconst:
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r := v.Reg()
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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if isFPreg(r) || isHILO(r) {
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// cannot move into FP or special registers, use TMP as intermediate
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p.To.Reg = mips.REGTMP
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p = gc.Prog(mips.AMOVW)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = mips.REGTMP
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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}
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case ssa.OpMIPSMOVFconst,
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ssa.OpMIPSMOVDconst:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_FCONST
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p.From.Val = math.Float64frombits(uint64(v.AuxInt))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpMIPSCMOVZ:
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if v.Reg() != v.Args[0].Reg() {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[2].Reg()
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p.Reg = v.Args[1].Reg()
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpMIPSCMOVZzero:
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if v.Reg() != v.Args[0].Reg() {
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v.Fatalf("input[0] and output not in same register %s", v.LongString())
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}
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[1].Reg()
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p.Reg = mips.REGZERO
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpMIPSCMPEQF,
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ssa.OpMIPSCMPEQD,
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ssa.OpMIPSCMPGEF,
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ssa.OpMIPSCMPGED,
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ssa.OpMIPSCMPGTF,
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ssa.OpMIPSCMPGTD:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[0].Reg()
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p.Reg = v.Args[1].Reg()
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case ssa.OpMIPSMOVWaddr:
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p := gc.Prog(mips.AMOVW)
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p.From.Type = obj.TYPE_ADDR
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var wantreg string
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// MOVW $sym+off(base), R
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// the assembler expands it as the following:
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// - base is SP: add constant offset to SP (R29)
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// when constant is large, tmp register (R23) may be used
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// - base is SB: load external address with relocation
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switch v.Aux.(type) {
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default:
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v.Fatalf("aux is of unknown type %T", v.Aux)
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case *ssa.ExternSymbol:
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wantreg = "SB"
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gc.AddAux(&p.From, v)
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case *ssa.ArgSymbol, *ssa.AutoSymbol:
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wantreg = "SP"
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gc.AddAux(&p.From, v)
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case nil:
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// No sym, just MOVW $off(SP), R
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wantreg = "SP"
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p.From.Reg = mips.REGSP
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p.From.Offset = v.AuxInt
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}
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if reg := v.Args[0].RegName(); reg != wantreg {
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v.Fatalf("bad reg %s for symbol type %T, want %s", reg, v.Aux, wantreg)
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}
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpMIPSMOVBload,
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ssa.OpMIPSMOVBUload,
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ssa.OpMIPSMOVHload,
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ssa.OpMIPSMOVHUload,
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ssa.OpMIPSMOVWload,
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ssa.OpMIPSMOVFload,
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ssa.OpMIPSMOVDload:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[0].Reg()
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpMIPSMOVBstore,
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ssa.OpMIPSMOVHstore,
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ssa.OpMIPSMOVWstore,
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ssa.OpMIPSMOVFstore,
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ssa.OpMIPSMOVDstore:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[1].Reg()
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p.To.Type = obj.TYPE_MEM
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p.To.Reg = v.Args[0].Reg()
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gc.AddAux(&p.To, v)
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case ssa.OpMIPSMOVBstorezero,
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ssa.OpMIPSMOVHstorezero,
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ssa.OpMIPSMOVWstorezero:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = mips.REGZERO
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p.To.Type = obj.TYPE_MEM
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p.To.Reg = v.Args[0].Reg()
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gc.AddAux(&p.To, v)
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case ssa.OpMIPSMOVBreg,
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ssa.OpMIPSMOVBUreg,
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ssa.OpMIPSMOVHreg,
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ssa.OpMIPSMOVHUreg:
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a := v.Args[0]
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for a.Op == ssa.OpCopy || a.Op == ssa.OpMIPSMOVWreg || a.Op == ssa.OpMIPSMOVWnop {
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a = a.Args[0]
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}
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if a.Op == ssa.OpLoadReg {
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t := a.Type
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switch {
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case v.Op == ssa.OpMIPSMOVBreg && t.Size() == 1 && t.IsSigned(),
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v.Op == ssa.OpMIPSMOVBUreg && t.Size() == 1 && !t.IsSigned(),
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v.Op == ssa.OpMIPSMOVHreg && t.Size() == 2 && t.IsSigned(),
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v.Op == ssa.OpMIPSMOVHUreg && t.Size() == 2 && !t.IsSigned():
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// arg is a proper-typed load, already zero/sign-extended, don't extend again
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if v.Reg() == v.Args[0].Reg() {
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return
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}
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p := gc.Prog(mips.AMOVW)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[0].Reg()
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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return
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default:
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}
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}
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fallthrough
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case ssa.OpMIPSMOVWF,
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ssa.OpMIPSMOVWD,
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ssa.OpMIPSTRUNCFW,
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ssa.OpMIPSTRUNCDW,
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ssa.OpMIPSMOVFD,
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ssa.OpMIPSMOVDF,
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ssa.OpMIPSNEGF,
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ssa.OpMIPSNEGD,
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ssa.OpMIPSSQRTD,
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ssa.OpMIPSCLZ:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
|
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p.From.Reg = v.Args[0].Reg()
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p.To.Type = obj.TYPE_REG
|
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p.To.Reg = v.Reg()
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case ssa.OpMIPSNEG:
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// SUB from REGZERO
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p := gc.Prog(mips.ASUBU)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = v.Args[0].Reg()
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p.Reg = mips.REGZERO
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
|
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case ssa.OpMIPSLoweredZero:
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// SUBU $4, R1
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// MOVW R0, 4(R1)
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// ADDU $4, R1
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// BNE Rarg1, R1, -2(PC)
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// arg1 is the address of the last element to zero
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var sz int64
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var mov obj.As
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switch {
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case v.AuxInt%4 == 0:
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sz = 4
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mov = mips.AMOVW
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case v.AuxInt%2 == 0:
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sz = 2
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mov = mips.AMOVH
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default:
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sz = 1
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mov = mips.AMOVB
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}
|
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p := gc.Prog(mips.ASUBU)
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p.From.Type = obj.TYPE_CONST
|
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p.From.Offset = sz
|
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p.To.Type = obj.TYPE_REG
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p.To.Reg = mips.REG_R1
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p2 := gc.Prog(mov)
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p2.From.Type = obj.TYPE_REG
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p2.From.Reg = mips.REGZERO
|
||||
p2.To.Type = obj.TYPE_MEM
|
||||
p2.To.Reg = mips.REG_R1
|
||||
p2.To.Offset = sz
|
||||
p3 := gc.Prog(mips.AADDU)
|
||||
p3.From.Type = obj.TYPE_CONST
|
||||
p3.From.Offset = sz
|
||||
p3.To.Type = obj.TYPE_REG
|
||||
p3.To.Reg = mips.REG_R1
|
||||
p4 := gc.Prog(mips.ABNE)
|
||||
p4.From.Type = obj.TYPE_REG
|
||||
p4.From.Reg = v.Args[1].Reg()
|
||||
p4.Reg = mips.REG_R1
|
||||
p4.To.Type = obj.TYPE_BRANCH
|
||||
gc.Patch(p4, p2)
|
||||
case ssa.OpMIPSLoweredMove:
|
||||
// SUBU $4, R1
|
||||
// MOVW 4(R1), Rtmp
|
||||
// MOVW Rtmp, (R2)
|
||||
// ADDU $4, R1
|
||||
// ADDU $4, R2
|
||||
// BNE Rarg2, R1, -4(PC)
|
||||
// arg2 is the address of the last element of src
|
||||
var sz int64
|
||||
var mov obj.As
|
||||
switch {
|
||||
case v.AuxInt%4 == 0:
|
||||
sz = 4
|
||||
mov = mips.AMOVW
|
||||
case v.AuxInt%2 == 0:
|
||||
sz = 2
|
||||
mov = mips.AMOVH
|
||||
default:
|
||||
sz = 1
|
||||
mov = mips.AMOVB
|
||||
}
|
||||
p := gc.Prog(mips.ASUBU)
|
||||
p.From.Type = obj.TYPE_CONST
|
||||
p.From.Offset = sz
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = mips.REG_R1
|
||||
p2 := gc.Prog(mov)
|
||||
p2.From.Type = obj.TYPE_MEM
|
||||
p2.From.Reg = mips.REG_R1
|
||||
p2.From.Offset = sz
|
||||
p2.To.Type = obj.TYPE_REG
|
||||
p2.To.Reg = mips.REGTMP
|
||||
p3 := gc.Prog(mov)
|
||||
p3.From.Type = obj.TYPE_REG
|
||||
p3.From.Reg = mips.REGTMP
|
||||
p3.To.Type = obj.TYPE_MEM
|
||||
p3.To.Reg = mips.REG_R2
|
||||
p4 := gc.Prog(mips.AADDU)
|
||||
p4.From.Type = obj.TYPE_CONST
|
||||
p4.From.Offset = sz
|
||||
p4.To.Type = obj.TYPE_REG
|
||||
p4.To.Reg = mips.REG_R1
|
||||
p5 := gc.Prog(mips.AADDU)
|
||||
p5.From.Type = obj.TYPE_CONST
|
||||
p5.From.Offset = sz
|
||||
p5.To.Type = obj.TYPE_REG
|
||||
p5.To.Reg = mips.REG_R2
|
||||
p6 := gc.Prog(mips.ABNE)
|
||||
p6.From.Type = obj.TYPE_REG
|
||||
p6.From.Reg = v.Args[2].Reg()
|
||||
p6.Reg = mips.REG_R1
|
||||
p6.To.Type = obj.TYPE_BRANCH
|
||||
gc.Patch(p6, p2)
|
||||
case ssa.OpMIPSCALLstatic:
|
||||
if v.Aux.(*gc.Sym) == gc.Deferreturn.Sym {
|
||||
// Deferred calls will appear to be returning to
|
||||
// the CALL deferreturn(SB) that we are about to emit.
|
||||
// However, the stack trace code will show the line
|
||||
// of the instruction byte before the return PC.
|
||||
// To avoid that being an unrelated instruction,
|
||||
// insert an actual hardware NOP that will have the right line number.
|
||||
// This is different from obj.ANOP, which is a virtual no-op
|
||||
// that doesn't make it into the instruction stream.
|
||||
ginsnop()
|
||||
}
|
||||
p := gc.Prog(obj.ACALL)
|
||||
p.To.Type = obj.TYPE_MEM
|
||||
p.To.Name = obj.NAME_EXTERN
|
||||
p.To.Sym = gc.Linksym(v.Aux.(*gc.Sym))
|
||||
if gc.Maxarg < v.AuxInt {
|
||||
gc.Maxarg = v.AuxInt
|
||||
}
|
||||
case ssa.OpMIPSCALLclosure:
|
||||
p := gc.Prog(obj.ACALL)
|
||||
p.To.Type = obj.TYPE_MEM
|
||||
p.To.Offset = 0
|
||||
p.To.Reg = v.Args[0].Reg()
|
||||
if gc.Maxarg < v.AuxInt {
|
||||
gc.Maxarg = v.AuxInt
|
||||
}
|
||||
case ssa.OpMIPSCALLdefer:
|
||||
p := gc.Prog(obj.ACALL)
|
||||
p.To.Type = obj.TYPE_MEM
|
||||
p.To.Name = obj.NAME_EXTERN
|
||||
p.To.Sym = gc.Linksym(gc.Deferproc.Sym)
|
||||
if gc.Maxarg < v.AuxInt {
|
||||
gc.Maxarg = v.AuxInt
|
||||
}
|
||||
case ssa.OpMIPSCALLgo:
|
||||
p := gc.Prog(obj.ACALL)
|
||||
p.To.Type = obj.TYPE_MEM
|
||||
p.To.Name = obj.NAME_EXTERN
|
||||
p.To.Sym = gc.Linksym(gc.Newproc.Sym)
|
||||
if gc.Maxarg < v.AuxInt {
|
||||
gc.Maxarg = v.AuxInt
|
||||
}
|
||||
case ssa.OpMIPSCALLinter:
|
||||
p := gc.Prog(obj.ACALL)
|
||||
p.To.Type = obj.TYPE_MEM
|
||||
p.To.Offset = 0
|
||||
p.To.Reg = v.Args[0].Reg()
|
||||
if gc.Maxarg < v.AuxInt {
|
||||
gc.Maxarg = v.AuxInt
|
||||
}
|
||||
case ssa.OpMIPSLoweredAtomicLoad:
|
||||
gc.Prog(mips.ASYNC)
|
||||
|
||||
p := gc.Prog(mips.AMOVW)
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Reg = v.Args[0].Reg()
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = v.Reg0()
|
||||
|
||||
gc.Prog(mips.ASYNC)
|
||||
case ssa.OpMIPSLoweredAtomicStore:
|
||||
gc.Prog(mips.ASYNC)
|
||||
|
||||
p := gc.Prog(mips.AMOVW)
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = v.Args[1].Reg()
|
||||
p.To.Type = obj.TYPE_MEM
|
||||
p.To.Reg = v.Args[0].Reg()
|
||||
|
||||
gc.Prog(mips.ASYNC)
|
||||
case ssa.OpMIPSLoweredAtomicStorezero:
|
||||
gc.Prog(mips.ASYNC)
|
||||
|
||||
p := gc.Prog(mips.AMOVW)
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = mips.REGZERO
|
||||
p.To.Type = obj.TYPE_MEM
|
||||
p.To.Reg = v.Args[0].Reg()
|
||||
|
||||
gc.Prog(mips.ASYNC)
|
||||
case ssa.OpMIPSLoweredAtomicExchange:
|
||||
// SYNC
|
||||
// MOVW Rarg1, Rtmp
|
||||
// LL (Rarg0), Rout
|
||||
// SC Rtmp, (Rarg0)
|
||||
// BEQ Rtmp, -3(PC)
|
||||
// SYNC
|
||||
gc.Prog(mips.ASYNC)
|
||||
|
||||
p := gc.Prog(mips.AMOVW)
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = v.Args[1].Reg()
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = mips.REGTMP
|
||||
|
||||
p1 := gc.Prog(mips.ALL)
|
||||
p1.From.Type = obj.TYPE_MEM
|
||||
p1.From.Reg = v.Args[0].Reg()
|
||||
p1.To.Type = obj.TYPE_REG
|
||||
p1.To.Reg = v.Reg0()
|
||||
|
||||
p2 := gc.Prog(mips.ASC)
|
||||
p2.From.Type = obj.TYPE_REG
|
||||
p2.From.Reg = mips.REGTMP
|
||||
p2.To.Type = obj.TYPE_MEM
|
||||
p2.To.Reg = v.Args[0].Reg()
|
||||
|
||||
p3 := gc.Prog(mips.ABEQ)
|
||||
p3.From.Type = obj.TYPE_REG
|
||||
p3.From.Reg = mips.REGTMP
|
||||
p3.To.Type = obj.TYPE_BRANCH
|
||||
gc.Patch(p3, p)
|
||||
|
||||
gc.Prog(mips.ASYNC)
|
||||
case ssa.OpMIPSLoweredAtomicAdd:
|
||||
// SYNC
|
||||
// LL (Rarg0), Rout
|
||||
// ADDU Rarg1, Rout, Rtmp
|
||||
// SC Rtmp, (Rarg0)
|
||||
// BEQ Rtmp, -3(PC)
|
||||
// SYNC
|
||||
// ADDU Rarg1, Rout
|
||||
gc.Prog(mips.ASYNC)
|
||||
|
||||
p := gc.Prog(mips.ALL)
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Reg = v.Args[0].Reg()
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = v.Reg0()
|
||||
|
||||
p1 := gc.Prog(mips.AADDU)
|
||||
p1.From.Type = obj.TYPE_REG
|
||||
p1.From.Reg = v.Args[1].Reg()
|
||||
p1.Reg = v.Reg0()
|
||||
p1.To.Type = obj.TYPE_REG
|
||||
p1.To.Reg = mips.REGTMP
|
||||
|
||||
p2 := gc.Prog(mips.ASC)
|
||||
p2.From.Type = obj.TYPE_REG
|
||||
p2.From.Reg = mips.REGTMP
|
||||
p2.To.Type = obj.TYPE_MEM
|
||||
p2.To.Reg = v.Args[0].Reg()
|
||||
|
||||
p3 := gc.Prog(mips.ABEQ)
|
||||
p3.From.Type = obj.TYPE_REG
|
||||
p3.From.Reg = mips.REGTMP
|
||||
p3.To.Type = obj.TYPE_BRANCH
|
||||
gc.Patch(p3, p)
|
||||
|
||||
gc.Prog(mips.ASYNC)
|
||||
|
||||
p4 := gc.Prog(mips.AADDU)
|
||||
p4.From.Type = obj.TYPE_REG
|
||||
p4.From.Reg = v.Args[1].Reg()
|
||||
p4.Reg = v.Reg0()
|
||||
p4.To.Type = obj.TYPE_REG
|
||||
p4.To.Reg = v.Reg0()
|
||||
|
||||
case ssa.OpMIPSLoweredAtomicAddconst:
|
||||
// SYNC
|
||||
// LL (Rarg0), Rout
|
||||
// ADDU $auxInt, Rout, Rtmp
|
||||
// SC Rtmp, (Rarg0)
|
||||
// BEQ Rtmp, -3(PC)
|
||||
// SYNC
|
||||
// ADDU $auxInt, Rout
|
||||
gc.Prog(mips.ASYNC)
|
||||
|
||||
p := gc.Prog(mips.ALL)
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Reg = v.Args[0].Reg()
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = v.Reg0()
|
||||
|
||||
p1 := gc.Prog(mips.AADDU)
|
||||
p1.From.Type = obj.TYPE_CONST
|
||||
p1.From.Offset = v.AuxInt
|
||||
p1.Reg = v.Reg0()
|
||||
p1.To.Type = obj.TYPE_REG
|
||||
p1.To.Reg = mips.REGTMP
|
||||
|
||||
p2 := gc.Prog(mips.ASC)
|
||||
p2.From.Type = obj.TYPE_REG
|
||||
p2.From.Reg = mips.REGTMP
|
||||
p2.To.Type = obj.TYPE_MEM
|
||||
p2.To.Reg = v.Args[0].Reg()
|
||||
|
||||
p3 := gc.Prog(mips.ABEQ)
|
||||
p3.From.Type = obj.TYPE_REG
|
||||
p3.From.Reg = mips.REGTMP
|
||||
p3.To.Type = obj.TYPE_BRANCH
|
||||
gc.Patch(p3, p)
|
||||
|
||||
gc.Prog(mips.ASYNC)
|
||||
|
||||
p4 := gc.Prog(mips.AADDU)
|
||||
p4.From.Type = obj.TYPE_CONST
|
||||
p4.From.Offset = v.AuxInt
|
||||
p4.Reg = v.Reg0()
|
||||
p4.To.Type = obj.TYPE_REG
|
||||
p4.To.Reg = v.Reg0()
|
||||
|
||||
case ssa.OpMIPSLoweredAtomicAnd,
|
||||
ssa.OpMIPSLoweredAtomicOr:
|
||||
// SYNC
|
||||
// LL (Rarg0), Rtmp
|
||||
// AND/OR Rarg1, Rtmp
|
||||
// SC Rtmp, (Rarg0)
|
||||
// BEQ Rtmp, -3(PC)
|
||||
// SYNC
|
||||
gc.Prog(mips.ASYNC)
|
||||
|
||||
p := gc.Prog(mips.ALL)
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Reg = v.Args[0].Reg()
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = mips.REGTMP
|
||||
|
||||
p1 := gc.Prog(v.Op.Asm())
|
||||
p1.From.Type = obj.TYPE_REG
|
||||
p1.From.Reg = v.Args[1].Reg()
|
||||
p1.Reg = mips.REGTMP
|
||||
p1.To.Type = obj.TYPE_REG
|
||||
p1.To.Reg = mips.REGTMP
|
||||
|
||||
p2 := gc.Prog(mips.ASC)
|
||||
p2.From.Type = obj.TYPE_REG
|
||||
p2.From.Reg = mips.REGTMP
|
||||
p2.To.Type = obj.TYPE_MEM
|
||||
p2.To.Reg = v.Args[0].Reg()
|
||||
|
||||
p3 := gc.Prog(mips.ABEQ)
|
||||
p3.From.Type = obj.TYPE_REG
|
||||
p3.From.Reg = mips.REGTMP
|
||||
p3.To.Type = obj.TYPE_BRANCH
|
||||
gc.Patch(p3, p)
|
||||
|
||||
gc.Prog(mips.ASYNC)
|
||||
|
||||
case ssa.OpMIPSLoweredAtomicCas:
|
||||
// MOVW $0, Rout
|
||||
// SYNC
|
||||
// LL (Rarg0), Rtmp
|
||||
// BNE Rtmp, Rarg1, 4(PC)
|
||||
// MOVW Rarg2, Rout
|
||||
// SC Rout, (Rarg0)
|
||||
// BEQ Rout, -4(PC)
|
||||
// SYNC
|
||||
p := gc.Prog(mips.AMOVW)
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = mips.REGZERO
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = v.Reg0()
|
||||
|
||||
gc.Prog(mips.ASYNC)
|
||||
|
||||
p1 := gc.Prog(mips.ALL)
|
||||
p1.From.Type = obj.TYPE_MEM
|
||||
p1.From.Reg = v.Args[0].Reg()
|
||||
p1.To.Type = obj.TYPE_REG
|
||||
p1.To.Reg = mips.REGTMP
|
||||
|
||||
p2 := gc.Prog(mips.ABNE)
|
||||
p2.From.Type = obj.TYPE_REG
|
||||
p2.From.Reg = v.Args[1].Reg()
|
||||
p2.Reg = mips.REGTMP
|
||||
p2.To.Type = obj.TYPE_BRANCH
|
||||
|
||||
p3 := gc.Prog(mips.AMOVW)
|
||||
p3.From.Type = obj.TYPE_REG
|
||||
p3.From.Reg = v.Args[2].Reg()
|
||||
p3.To.Type = obj.TYPE_REG
|
||||
p3.To.Reg = v.Reg0()
|
||||
|
||||
p4 := gc.Prog(mips.ASC)
|
||||
p4.From.Type = obj.TYPE_REG
|
||||
p4.From.Reg = v.Reg0()
|
||||
p4.To.Type = obj.TYPE_MEM
|
||||
p4.To.Reg = v.Args[0].Reg()
|
||||
|
||||
p5 := gc.Prog(mips.ABEQ)
|
||||
p5.From.Type = obj.TYPE_REG
|
||||
p5.From.Reg = v.Reg0()
|
||||
p5.To.Type = obj.TYPE_BRANCH
|
||||
gc.Patch(p5, p1)
|
||||
|
||||
gc.Prog(mips.ASYNC)
|
||||
|
||||
p6 := gc.Prog(obj.ANOP)
|
||||
gc.Patch(p2, p6)
|
||||
|
||||
case ssa.OpVarDef:
|
||||
gc.Gvardef(v.Aux.(*gc.Node))
|
||||
case ssa.OpVarKill:
|
||||
gc.Gvarkill(v.Aux.(*gc.Node))
|
||||
case ssa.OpVarLive:
|
||||
gc.Gvarlive(v.Aux.(*gc.Node))
|
||||
case ssa.OpKeepAlive:
|
||||
gc.KeepAlive(v)
|
||||
case ssa.OpPhi:
|
||||
gc.CheckLoweredPhi(v)
|
||||
case ssa.OpMIPSLoweredNilCheck:
|
||||
// Issue a load which will fault if arg is nil.
|
||||
p := gc.Prog(mips.AMOVB)
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Reg = v.Args[0].Reg()
|
||||
gc.AddAux(&p.From, v)
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = mips.REGTMP
|
||||
if gc.Debug_checknil != 0 && v.Line > 1 { // v.Line==1 in generated wrappers
|
||||
gc.Warnl(v.Line, "generated nil check")
|
||||
}
|
||||
case ssa.OpMIPSFPFlagTrue,
|
||||
ssa.OpMIPSFPFlagFalse:
|
||||
// MOVW $1, r
|
||||
// CMOVF R0, r
|
||||
|
||||
cmov := mips.ACMOVF
|
||||
if v.Op == ssa.OpMIPSFPFlagFalse {
|
||||
cmov = mips.ACMOVT
|
||||
}
|
||||
p := gc.Prog(mips.AMOVW)
|
||||
p.From.Type = obj.TYPE_CONST
|
||||
p.From.Offset = 1
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = v.Reg()
|
||||
p1 := gc.Prog(cmov)
|
||||
p1.From.Type = obj.TYPE_REG
|
||||
p1.From.Reg = mips.REGZERO
|
||||
p1.To.Type = obj.TYPE_REG
|
||||
p1.To.Reg = v.Reg()
|
||||
|
||||
case ssa.OpMIPSLoweredGetClosurePtr:
|
||||
// Closure pointer is R22 (mips.REGCTXT).
|
||||
gc.CheckLoweredGetClosurePtr(v)
|
||||
default:
|
||||
v.Fatalf("genValue not implemented: %s", v.LongString())
|
||||
}
|
||||
}
|
||||
|
||||
var blockJump = map[ssa.BlockKind]struct {
|
||||
asm, invasm obj.As
|
||||
}{
|
||||
ssa.BlockMIPSEQ: {mips.ABEQ, mips.ABNE},
|
||||
ssa.BlockMIPSNE: {mips.ABNE, mips.ABEQ},
|
||||
ssa.BlockMIPSLTZ: {mips.ABLTZ, mips.ABGEZ},
|
||||
ssa.BlockMIPSGEZ: {mips.ABGEZ, mips.ABLTZ},
|
||||
ssa.BlockMIPSLEZ: {mips.ABLEZ, mips.ABGTZ},
|
||||
ssa.BlockMIPSGTZ: {mips.ABGTZ, mips.ABLEZ},
|
||||
ssa.BlockMIPSFPT: {mips.ABFPT, mips.ABFPF},
|
||||
ssa.BlockMIPSFPF: {mips.ABFPF, mips.ABFPT},
|
||||
}
|
||||
|
||||
func ssaGenBlock(s *gc.SSAGenState, b, next *ssa.Block) {
|
||||
s.SetLineno(b.Line)
|
||||
|
||||
switch b.Kind {
|
||||
case ssa.BlockPlain:
|
||||
if b.Succs[0].Block() != next {
|
||||
p := gc.Prog(obj.AJMP)
|
||||
p.To.Type = obj.TYPE_BRANCH
|
||||
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
|
||||
}
|
||||
case ssa.BlockDefer:
|
||||
// defer returns in R1:
|
||||
// 0 if we should continue executing
|
||||
// 1 if we should jump to deferreturn call
|
||||
p := gc.Prog(mips.ABNE)
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = mips.REGZERO
|
||||
p.Reg = mips.REG_R1
|
||||
p.To.Type = obj.TYPE_BRANCH
|
||||
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[1].Block()})
|
||||
if b.Succs[0].Block() != next {
|
||||
p := gc.Prog(obj.AJMP)
|
||||
p.To.Type = obj.TYPE_BRANCH
|
||||
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
|
||||
}
|
||||
case ssa.BlockExit:
|
||||
gc.Prog(obj.AUNDEF) // tell plive.go that we never reach here
|
||||
case ssa.BlockRet:
|
||||
gc.Prog(obj.ARET)
|
||||
case ssa.BlockRetJmp:
|
||||
p := gc.Prog(obj.ARET)
|
||||
p.To.Type = obj.TYPE_MEM
|
||||
p.To.Name = obj.NAME_EXTERN
|
||||
p.To.Sym = gc.Linksym(b.Aux.(*gc.Sym))
|
||||
case ssa.BlockMIPSEQ, ssa.BlockMIPSNE,
|
||||
ssa.BlockMIPSLTZ, ssa.BlockMIPSGEZ,
|
||||
ssa.BlockMIPSLEZ, ssa.BlockMIPSGTZ,
|
||||
ssa.BlockMIPSFPT, ssa.BlockMIPSFPF:
|
||||
jmp := blockJump[b.Kind]
|
||||
var p *obj.Prog
|
||||
switch next {
|
||||
case b.Succs[0].Block():
|
||||
p = gc.Prog(jmp.invasm)
|
||||
p.To.Type = obj.TYPE_BRANCH
|
||||
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[1].Block()})
|
||||
case b.Succs[1].Block():
|
||||
p = gc.Prog(jmp.asm)
|
||||
p.To.Type = obj.TYPE_BRANCH
|
||||
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
|
||||
default:
|
||||
p = gc.Prog(jmp.asm)
|
||||
p.To.Type = obj.TYPE_BRANCH
|
||||
s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
|
||||
q := gc.Prog(obj.AJMP)
|
||||
q.To.Type = obj.TYPE_BRANCH
|
||||
s.Branches = append(s.Branches, gc.Branch{P: q, B: b.Succs[1].Block()})
|
||||
}
|
||||
if !b.Control.Type.IsFlags() {
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = b.Control.Reg()
|
||||
}
|
||||
default:
|
||||
b.Fatalf("branch not implemented: %s. Control: %s", b.LongString(), b.Control.LongString())
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue